On Mon, Aug 15, 2022 at 1:26 PM Richard Henderson
wrote:
>
> On 8/15/22 14:03, Peter Maydell wrote:
> > The riscv target incorrectly enabled semihosting always, whether the
> > user asked for it or not. Call semihosting_enabled() passing the
> > correct value to the is_userspace argument, which f
On Sun, Aug 14, 2022 at 3:04 PM Alistair Francis wrote:
>
> On Sat, Aug 13, 2022 at 8:20 PM Peter Maydell
> wrote:
> >
> > On Sat, 13 Aug 2022 at 01:53, Furquan Shaikh wrote:
> > > I ran into a problem when I was testing a project (with a microkernel
> > &
On Fri, Aug 12, 2022 at 7:32 PM Richard Henderson
wrote:
>
> On 8/12/22 17:50, Furquan Shaikh wrote:
> >> Why do you need such fine-grained control? What is the use-case?
> >
> > I ran into a problem when I was testing a project (with a microkernel
> > in M-mo
On Fri, Aug 12, 2022 at 5:30 PM Richard Henderson
wrote:
>
> On 8/12/22 16:57, Furquan Shaikh wrote:
> > I am not sure if I understood your comment correctly. Currently, qemu
> > has a check in `riscv_cpu_do_interrupt` to allow semihosting calls
> > only in S an
On Fri, Aug 12, 2022 at 4:42 PM Richard Henderson
wrote:
>
> On 8/12/22 16:27, Richard Henderson wrote:
> > On 8/11/22 13:41, Furquan Shaikh wrote:
> >> Unlike ARM, RISC-V does not define a separate breakpoint type for
> >> semihosting. Instead, it is entirely ABI. T
On Fri, Aug 12, 2022 at 4:00 PM Palmer Dabbelt wrote:
>
> On Fri, 12 Aug 2022 15:05:08 PDT (-0700), furq...@rivosinc.com wrote:
> > On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones
> > wrote:
> >>
> >> On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh w
-spec/blob/release/riscv-debug-release.pdf
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Andrew Jones
Signed-off-by: Furquan Shaikh
---
v2: Updated qemu-options.hx to document the ebreak options.
Retained Reviewed-by from Philippe and Andrew since no
functional change in this version
On Fri, Aug 12, 2022 at 4:28 AM Peter Maydell wrote:
>
> On Thu, 11 Aug 2022 at 21:47, Furquan Shaikh wrote:
> >
> > Unlike ARM, RISC-V does not define a separate breakpoint type for
> > semihosting. Instead, it is entirely ABI. Thus, we need an option
> > to all
On Fri, Aug 12, 2022 at 4:04 AM Andrew Jones wrote:
>
> On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> > Unlike ARM, RISC-V does not define a separate breakpoint type for
> > semihosting. Instead, it is entirely ABI. Thus, we need an option
> > to allow
...@mail.gmail.com/
[2] https://lists.gnu.org/archive/html/qemu-devel/2022-08/msg01905.html
On Thu, Aug 11, 2022 at 1:41 PM Furquan Shaikh wrote:
>
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely ABI. Thus, we need an option
> to al
-spec/blob/release/riscv-debug-release.pdf
Signed-off-by: Furquan Shaikh
---
target/riscv/cpu.c| 8
target/riscv/cpu.h| 7 +++
target/riscv/cpu_helper.c | 26 +-
3 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b
Hello All,
I had a doubt about the COW implementation of QCOW2.
Suppose two clusters point to the same address, then in that case, the
QCOW_OFLAG_COPIED is cleared in the l2 entries for both the clusters.
Now suppose a write is made to any one of the clusters, then how is the
other cluster identif
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