From: Frank Chang
Add the missing implied rule for standard B extension.
Standard B extension implies Zba, Zbb, Zbs extensions.
RISC-V B spec: https://github.com/riscv/riscv-b
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Reviewed-by: Jim Shu
---
target/riscv/cpu.c | 14
From: Jim Shu
Add the missing implied rule from G to imafd_zicsr_zifencei.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
target/riscv/cpu.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d92874baa0
Reviewed-by: Frank Chang
Daniel Henrique Barboza 於 2025年3月27日 週四 下午9:04寫道：
>
> Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and
> made it default for qemu-system-riscv32/64. It was the first RISC-V
> machine added in QEMU so setting it as default w
and 'rnmi-exception-vector' as the
> property
> > of the harts. It’s very easy for users to set the address based on their
> > expectation. This patch also adds the functionality to handle the RNMI
> signals.
> >
> > Signed-off-by: Frank Chang
> > Signed-of
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Daniel Henrique Barboza
---
hw/riscv/riscv_hart.c | 41
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/c
> > mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
> > interrupts will be disabled. Since our current OpenSBI does not
> > support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for
> > now. We can re-enable it once OpenSBI include
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h
x27;s disable Smrnmi for the 'max' type CPU for
now. We can re-enable it once OpenSBI includes proper support for it.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 2 ++
targe
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
x27;s disable Smrnmi for the 'max' type CPU for
now. We can re-enable it once OpenSBI includes proper support for it.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 2 ++
targe
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Daniel Henrique Barboza
---
hw/riscv/riscv_hart.c | 42 -
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/c
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
gt; We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the
> property
> > of the harts. It’s very easy for users to set the address based on their
> > expectation. This patch also adds the functionality to handle the RNMI
> signals.
> &g
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 40 +
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/cpu.h| 3 ++
target/riscv/c
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Frank Chang
When Smrnmi is present, the firmware (e.g., OpenSBI) must set
mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
interrupts will be disabled. Since our current OpenSBI does not
support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e6988f44c6..7a4aa235ce 100644
--- a/target/riscv
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of
pdate_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
> }
> +
> +/*
> + * ext_smrnmi requires OpenSBI changes that our current
> + * image does not have. Disable it for now.
> + */
> +isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false);
> }
>
> This will make
Hi,
A gentle ping on this.
Regards,
Frank Chang
於 2024年11月22日 週五 上午11:23寫道：
>
> From: Frank Chang
>
> This patchset added support for Smrnmi Extension in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
On Wed, Nov 20, 2024 at 11:29 AM Frank Chang wrote:
> On Mon, Nov 18, 2024 at 11:13 AM Alistair Francis
> wrote:
>
>> On Mon, Oct 21, 2024 at 1:06 PM wrote:
>> >
>> > From: Tommy Wu
>> >
>> > Because the RNMI interrupt trap handler address
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b402d8545b..6c91464a00 100644
--- a/target/riscv
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 40 +
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/cpu.h| 3 ++
target/riscv/c
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h
and 'rnmi-exception-vector' as the
> property
> > of the harts. It’s very easy for users to set the address based on their
> > expectation. This patch also adds the functionality to handle the RNMI
> signals.
> >
> > Signed-off-by: Frank Chang
> > Signe
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
tar
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 18
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/cpu.h| 6 +++
target/riscv/cpu_bits.h
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b3195da512..fed64741d1 100644
--- a/target/riscv
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
On Thu, Oct 17, 2024 at 7:18 PM Rajnesh Kanwal wrote:
> On Tue, Aug 27, 2024 at 10:28 AM Frank Chang
> wrote:
> >
> > Rajnesh Kanwal 於 2024年6月19日 週三 下午11:27寫道：
> > >
> > > This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
> > > sctrd
ode.
Otherwise, we may hit the assertion in:
riscv_pmu_cycle_update_priv(), and riscv_pmu_icount_update_priv()
The TLB will also not be flushed properly on the virt mode changed.
I will fix it in the next patchset.
Thanks,
Frank Chang
>
> Thanks,
>
> Clément
>
>
> > + return;
> > + }
>
>
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b3195da512..fed64741d1 100644
--- a/target/riscv
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
tar
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 18
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/cpu.h| 6 +++
target/riscv/cpu_bits.h
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
nt
Hi Clément,
Sorry for keeping you waiting. I've reviewed the comments from you and Alistair.
The comments should be straightforward to fix.
I will fix them and send out the patchset later today.
Hope that it makes things easier.
Regards,
Frank Chang
>
> > Alistair so
> &
Hi Daniel,
Thanks for the reminder.
I'll take over Tommy's work to send out the v7 patchset later this week.
Regards,
Frank Chang
On Fri, Oct 11, 2024 at 7:38 PM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Hi Tommy,
>
>
> Do you plan to send a n
gt; bool ext_smaia;
> bool ext_ssaia;
> +bool ext_smctr;
> +bool ext_ssctr;
Base on: https://github.com/riscv/riscv-control-transfer-records/pull/29
Smctr and Ssctr depend on both S-mode and Sscsrind.
We should add the implied rules for Smctr and Ssctr.
Regards,
Frank Chang
Reviewed-by: Frank Chang
Jason Chien 於 2024年7月23日 週二 上午1:51寫道：
>
> RVV spec allows implementations to set vl with values within
> [ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
> property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). Th
static RISCVException write_menvcfg(CPURISCVState
> *env, int csrno,
> (cfg->ext_sstc ? MENVCFG_STCE : 0) |
> (cfg->ext_svadu ? MENVCFG_ADUE : 0);
> }
> +/* Update PMM field only if the value is valid according to Zjpm v0.8 */
> +if (((val &
}
> } else {
> -val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
> +mask |= MSECCFG_RLB;
> +val &= ~(mask);
> }
>
> env->mseccfg = val;
> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
> index f5c10ce85c..ccff0eb
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 50
From: Frank Chang
Add multi extension implied rules to enable the implied extensions of
the multi extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/tcg/tcg-cpu.c | 119
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
On Fri, Jun 21, 2024 at 12:15 PM Alistair Francis
wrote:
> On Sun, Jun 16, 2024 at 12:48 PM wrote:
> >
> > From: Frank Chang
> >
> > Introduce helpers to enable the extensions based on the implied rules.
> > The implied extensions are enabled recursively, so w
Reviewed-by: Frank Chang
Max Chou 於 2024年6月14日 週五 上午1:52寫道：
>
> If there are not any QEMU plugin memory callback functions, checking
> before calling the qemu_plugin_vcpu_mem_cb function can reduce the
> function call overhead.
>
> Signed-off-by: Max Chou
> ---
> acc
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 119 -
1
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 50 +-
1
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a
From: Frank Chang
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 340
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
On Wed, Jun 5, 2024 at 2:32 PM wrote:
> From: Frank Chang
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
&g
Hi Alistair,
On Tue, Jun 11, 2024 at 9:35 AM Alistair Francis
wrote:
> On Wed, Jun 5, 2024 at 4:35 PM wrote:
> >
> > From: Frank Chang
> >
> > RISCVCPUImpliedExtsRule is created to store the implied rules.
> > 'is_misa' flag is used to distinguish wh
Reviewed-by: Frank Chang
Daniel Henrique Barboza 於 2024年5月24日 週五 上午1:42寫道：
>
> From: Tomasz Jeznach
>
> DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
> tr_response.
>
> The DBG cap is always enabled. No on/off toggle is provided for it.
>
Reviewed-by: Frank Chang
Daniel Henrique Barboza 於 2024年5月24日 週五 上午1:41寫道：
>
> From: Tomasz Jeznach
>
> Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
> This will add support for ATS translation requests in Fault/Event
> queues, Page-reque
gt; +.name = "riscv-iommu",
> +.unmigratable = 1
> +};
> +
> +static void riscv_iommu_pci_init(Object *obj)
> +{
> +RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj);
> +RISCVIOMMUState *iommu = &s->iommu;
> +
> +object_initialize_child(ob
Patchset resend:
https://lists.gnu.org/archive/html/qemu-riscv/2024-06/msg00130.html
於 2024年6月3日 週一 下午2:07寫道：
> From: Frank Chang
>
> Currently, the implied extensions are enabled and checked in
> riscv_cpu_validate_set_extensions(). However, the order of enabling the
> imp
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
---
target/riscv/tcg/tcg-cpu.c | 115 -
1 file changed, 115 deletions(-)
diff --git a/target
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
From: Frank Chang
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 340 +
1 file changed, 340 insertions(+)
diff --git a/target/riscv
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b
於 2024年6月3日 週一 下午2:06寫道：
>
> From: Frank Chang
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
>
Reviewed-by: Frank Chang
Fea.Wang 於 2024年6月3日 週一 下午1:48寫道：
>
> Fix the transmission return size because not all bytes could be
> transmitted successfully. So, return a successful length instead of a
> constant value.
>
> Signed-off-by: Fea.Wang
> ---
> hw/net/xilinx_ax
Reviewed-by: Frank Chang
Fea.Wang 於 2024年6月3日 週一 下午1:49寫道：
>
> Due to a description loading failure, adding a trace log makes observing
> the DMA behavior easy.
>
> Signed-off-by: Fea.Wang
> ---
> hw/dma/trace-events| 3 +++
> hw/dma/xilinx_axidma.c | 3 +
Reviewed-by: Frank Chang
Fea.Wang 於 2024年6月3日 週一 下午1:48寫道：
>
> When calling the loading a description function, it should be noticed
> that the function may return a failure value. Breaking the loop is one
> of the possible ways to handle it.
>
> Signed-off-by: Fea.Wan
Reviewed-by: Frank Chang
Fea.Wang 於 2024年6月3日 週一 下午1:48寫道：
>
> Loading a description from memory may cause a bus-error. In this
> case, the DMA should stop working, set the error flag, and return
> the error value.
>
> Signed-off-by: Fea.Wang
> ---
> hw/
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/tcg/tcg
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
---
target/riscv/cpu.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff
From: Frank Chang
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
---
target/riscv/cpu.c | 340 +
1 file changed, 340 insertions
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
---
target/riscv/tcg/tcg-cpu.c | 115 -
1 file changed, 115
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