From: Frank Chang
Add the missing implied rule for standard B extension.
Standard B extension implies Zba, Zbb, Zbs extensions.
RISC-V B spec: https://github.com/riscv/riscv-b
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Reviewed-by: Jim Shu
---
target/riscv/cpu.c | 14
From: Jim Shu
Add the missing implied rule from G to imafd_zicsr_zifencei.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
target/riscv/cpu.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d92874baa0
+ .diag_rc = DIAG_308_RC_INVAL_FOR_PV};
+
@Thomas: Is the formatting of the assignments correct or should there be
no assignment on lines containing "{}"?
Checkpatch is happy, though personally I find it hard to read.
Once that's clear or fixed:
Reviewed-by: Janosch Frank
On 4/17/25 2:37 PM, Gautam Gala wrote:
Replace an existing macro (s390_pv_cmd_exit) that looks like
a function with an actual function. The function will be used
when exiting PV instead of the macro.
Reviewed-by: Steffen Eiden
Signed-off-by: Gautam Gala
Reviewed-by: Janosch Frank
async(S390CcwMachineState *ms)
return true;
}
+#define DIAG_308_UV_RC_INVAL_HOSTKEY0x0108
s/DIAG_308_UV_RC_INVAL_HOSTKEY/UV_RC_SSC_INVAL_HOSTKEY/
The naming of the constant should reflect to which UV command this rc
belongs to.
Once changed:
Reviewed-by: Janosch Frank
On 4/17/25 9:40 AM, Gautam Gala wrote:
Extend DIAG308 subcode 10 to return the UVC RC, RRC and command code
in bit positions 32-47, 16-31, and 0-15 of register R1 + 1 if the
function does not complete successfully (in addition to the
previously returned diag response code in bit position 47-63).
Reviewed-by: Frank Chang
Daniel Henrique Barboza 於 2025年3月27日 週四 下午9:04寫道：
>
> Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and
> made it default for qemu-system-riscv32/64. It was the first RISC-V
> machine added in QEMU so setting it as default w
and 'rnmi-exception-vector' as the
> property
> > of the harts. It’s very easy for users to set the address based on their
> > expectation. This patch also adds the functionality to handle the RNMI
> signals.
> >
> > Signed-off-by: Frank Chang
> > Signed-of
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Daniel Henrique Barboza
---
hw/riscv/riscv_hart.c | 41
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/c
> > mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
> > interrupts will be disabled. Since our current OpenSBI does not
> > support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for
> > now. We can re-enable it once OpenSBI include
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h
x27;s disable Smrnmi for the 'max' type CPU for
now. We can re-enable it once OpenSBI includes proper support for it.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 2 ++
targe
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
x27;s disable Smrnmi for the 'max' type CPU for
now. We can re-enable it once OpenSBI includes proper support for it.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 2 ++
targe
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Daniel Henrique Barboza
---
hw/riscv/riscv_hart.c | 42 -
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/c
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
gt; We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the
> property
> > of the harts. It’s very easy for users to set the address based on their
> > expectation. This patch also adds the functionality to handle the RNMI
> signals.
> &g
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 40 +
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/cpu.h| 3 ++
target/riscv/c
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Frank Chang
When Smrnmi is present, the firmware (e.g., OpenSBI) must set
mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
interrupts will be disabled. Since our current OpenSBI does not
support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e6988f44c6..7a4aa235ce 100644
--- a/target/riscv
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of
On Mon, Dec 16, 2024 at 9:46 PM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Hi Frank,
>
> Sorry for the delay.
>
> It seems like this series is breaking the "make check-functional" test:
>
> $ make check-functional
> (...)
> 9/
Hi,
A gentle ping on this.
Regards,
Frank Chang
於 2024年11月22日 週五 上午11:23寫道：
>
> From: Frank Chang
>
> This patchset added support for Smrnmi Extension in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
Introduce a new PTFF subfunction to query-stamp events.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Janosch Frank
On 12/9/24 4:29 PM, Hendrik Brueckner wrote:
On Mon, Dec 09, 2024 at 04:04:19PM +0100, Janosch Frank wrote:
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
MSA11 introduces new HMAC subfunctions.
Consider this to be an ACK of the MSA patches.
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
The sequential instruction fetching facility provides few guarantees,
for example, to avoid stop machine calls on enabling/disabling kprobes.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Janosch Frank
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
This facility indicates reduced support for noncontrained
transactional-execution.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Janosch Frank
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
The Concurrent-functions facility introduces the new instruction
Perform Functions with Concurrent Results (PFCR) with few subfunctions.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Janosch Frank
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
This facility introduces few new instructions.
Signed-off-by: Hendrik Brueckner
---
Reviewed-by: Janosch Frank
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
The Vector Enhancements facility 3 introduces new instructions and
extends support for doubleword/quadword elements.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Janosch Frank
-by: Janosch Frank
On 12/9/24 4:54 PM, Hendrik Brueckner wrote:
On Mon, Dec 09, 2024 at 04:45:25PM +0100, Janosch Frank wrote:
On 12/9/24 4:24 PM, Hendrik Brueckner wrote:
On Mon, Dec 09, 2024 at 03:48:11PM +0100, Janosch Frank wrote:
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
MSA12 changes the KIMD/KLMD
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
MSA12 changes the KIMD/KLMD instruction format for SHA3/SHAKE.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Christian Borntraeger
MSA6 is a prereq, no?
On 12/9/24 4:24 PM, Hendrik Brueckner wrote:
On Mon, Dec 09, 2024 at 03:48:11PM +0100, Janosch Frank wrote:
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
MSA12 changes the KIMD/KLMD instruction format for SHA3/SHAKE.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Christian Borntraeger
MSA6
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
MSA11 introduces new HMAC subfunctions.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Christian Borntraeger
---
target/s390x/cpu_features.c | 2 ++
target/s390x/cpu_features_def.h.inc | 10 ++
target/s390x/cpu_models.c
On 12/6/24 1:27 PM, Hendrik Brueckner wrote:
MSA13 introduces query authentication information (QAI) subfunctions.
Signed-off-by: Hendrik Brueckner
Reviewed-by: Janosch Frank
On 12/6/24 3:14 PM, Richard Henderson wrote:
On 12/6/24 06:27, Hendrik Brueckner wrote:
Introducing the gen17 CPU model with feature indications
comprising of:
* Concurrent-function facility with subcodes
* More vector extensions
* Ineffective-nonconstrained-transaction facility
* Even more msa
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
On Wed, Nov 20, 2024 at 11:29 AM Frank Chang wrote:
> On Mon, Nov 18, 2024 at 11:13 AM Alistair Francis
> wrote:
>
>> On Mon, Oct 21, 2024 at 1:06 PM wrote:
>> >
>> > From: Tommy Wu
>> >
>> > Because the RNMI interrupt trap handler address
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b402d8545b..6c91464a00 100644
--- a/target/riscv
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 40 +
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/cpu.h| 3 ++
target/riscv/c
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h
and 'rnmi-exception-vector' as the
> property
> > of the harts. It’s very easy for users to set the address based on their
> > expectation. This patch also adds the functionality to handle the RNMI
> signals.
> >
> > Signed-off-by: Frank Chang
> > Signe
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
tar
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 18
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/cpu.h| 6 +++
target/riscv/cpu_bits.h
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b3195da512..fed64741d1 100644
--- a/target/riscv
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
On Thu, Oct 17, 2024 at 7:18 PM Rajnesh Kanwal wrote:
> On Tue, Aug 27, 2024 at 10:28 AM Frank Chang
> wrote:
> >
> > Rajnesh Kanwal 於 2024年6月19日 週三 下午11:27寫道：
> > >
> > > This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
> > > sctrd
ATUS_MNPV,
> > + env->virt_enabled);
> > + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPP,
> > + env->priv);
> > + env->mncause = cause | ((target_ulong)1U << (TARGET_LONG_BITS - 1));
> > + env->mnepc = env->pc;
> > + env->pc = env-&g
From: Tommy Wu
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/c
From: Tommy Wu
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b3195da512..fed64741d1 100644
--- a/target/riscv
From: Tommy Wu
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
tar
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
hw/riscv/riscv_hart.c | 18
include/hw/riscv/riscv_hart.h | 4 ++
target/riscv/cpu.c| 11 +
target/riscv/cpu.h| 6 +++
target/riscv/cpu_bits.h
From: Frank Chang
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741
nt
Hi Clément,
Sorry for keeping you waiting. I've reviewed the comments from you and Alistair.
The comments should be straightforward to fix.
I will fix them and send out the patchset later today.
Hope that it makes things easier.
Regards,
Frank Chang
>
> > Alistair so
> &
Hi Daniel,
Thanks for the reminder.
I'll take over Tommy's work to send out the v7 patchset later this week.
Regards,
Frank Chang
On Fri, Oct 11, 2024 at 7:38 PM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Hi Tommy,
>
>
> Do you plan to send a n
On 10/1/24 10:54 AM, David Hildenbrand wrote:
On 30.09.24 23:49, Halil Pasic wrote:
On Fri, 27 Sep 2024 20:29:19 +0200
David Hildenbrand wrote:
On 27.09.24 20:20, Halil Pasic wrote:
On Wed, 11 Sep 2024 21:09:27 +0200
David Hildenbrand wrote:
[...]
That is a valid point. But IMHO the ben
On 9/12/24 10:19 AM, Thomas Huth wrote:
On 10/09/2024 19.58, David Hildenbrand wrote:
[...]
diff --git a/hw/s390x/s390-hypercall.h b/hw/s390x/s390-hypercall.h
index b7ac29f444..f0ca62bcbb 100644
--- a/hw/s390x/s390-hypercall.h
+++ b/hw/s390x/s390-hypercall.h
@@ -18,6 +18,7 @@
#define DIAG5
On 9/10/24 7:57 PM, David Hildenbrand wrote:
This series introduces a new diag(500) "STORAGE LIMIT" subcode that will
be documented at [2] once this+kernel part go upstream.
Why not in Documentation/virt/kvm/s390/?
s390-diag.rst is very similar already.
I'd rather have it in a shared and bigge
argument
kvm_set_phys_mem: error registering slot: Invalid argument
Aborted (core dumped)
Let's handle that in a better way by rejecting such weird RAM sizes
right from the start:
Huh, I always assumed that ram is handled in multiples of 1MB in QEMU.
Acked-by: Janosch Frank
Hi Michael,
the patch is no longer required. The fix was applied with
da7c95920d027dbb00c6879c1da0216b19509191
I don't know if this was done independent of my proposal or not, but
anyway, I'm satisfied :-)
Thanks!
Frank
[1] https://github.com/qemu/q
gt; bool ext_smaia;
> bool ext_ssaia;
> +bool ext_smctr;
> +bool ext_ssctr;
Base on: https://github.com/riscv/riscv-control-transfer-records/pull/29
Smctr and Ssctr depend on both S-mode and Sscsrind.
We should add the implied rules for Smctr and Ssctr.
Regards,
Frank Chang
Reviewed-by: Frank Chang
Jason Chien 於 2024年7月23日 週二 上午1:51寫道：
>
> RVV spec allows implementations to set vl with values within
> [ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
> property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). Th
static RISCVException write_menvcfg(CPURISCVState
> *env, int csrno,
> (cfg->ext_sstc ? MENVCFG_STCE : 0) |
> (cfg->ext_svadu ? MENVCFG_ADUE : 0);
> }
> +/* Update PMM field only if the value is valid according to Zjpm v0.8 */
> +if (((val &
}
> } else {
> -val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
> +mask |= MSECCFG_RLB;
> +val &= ~(mask);
> }
>
> env->mseccfg = val;
> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
> index f5c10ce85c..ccff0eb
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 50
From: Frank Chang
Add multi extension implied rules to enable the implied extensions of
the multi extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/tcg/tcg-cpu.c | 119
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
On Fri, Jun 21, 2024 at 12:15 PM Alistair Francis
wrote:
> On Sun, Jun 16, 2024 at 12:48 PM wrote:
> >
> > From: Frank Chang
> >
> > Introduce helpers to enable the extensions based on the implied rules.
> > The implied extensions are enabled recursively, so w
Reviewed-by: Frank Chang
Max Chou 於 2024年6月14日 週五 上午1:52寫道：
>
> If there are not any QEMU plugin memory callback functions, checking
> before calling the qemu_plugin_vcpu_mem_cb function can reduce the
> function call overhead.
>
> Signed-off-by: Max Chou
> ---
> acc
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 119 -
1
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 50 +-
1
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a
From: Frank Chang
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 340
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
On Wed, Jun 5, 2024 at 2:32 PM wrote:
> From: Frank Chang
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
&g
Hi Alistair,
On Tue, Jun 11, 2024 at 9:35 AM Alistair Francis
wrote:
> On Wed, Jun 5, 2024 at 4:35 PM wrote:
> >
> > From: Frank Chang
> >
> > RISCVCPUImpliedExtsRule is created to store the implied rules.
> > 'is_misa' flag is used to distinguish wh
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