[PATCH] hw/char: sifive_uart: Avoid infinite delay of async xmit function

updating it if it is not already active. Signed-off-by: Florian Lugou --- hw/char/sifive_uart.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 0fc89e76d1..9bc697a67b 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char

[PATCH v2 1/2] target/riscv: Add scontext CSR handling

scontext size is 16 bits on RV32 and 32 bits on RV64, as recommended by version 1.0 2025-02-21 of the debug specification. When the Smstateen extension is implemented, accessibility to the scontext CSR is controlled by bit 57 of the [mh]stateen0 CSRs. Signed-off-by: Florian Lugou --- target

[PATCH v2 0/2] target/riscv: Support scontext-based trigger matching

Hello, v2: Rebasing the patch series on top of the maintainer's tree. Thank you, Florian Lugou (2): target/riscv: Add scontext CSR handling target/riscv: Support matching scontext in Sdtrig's textra CSRs target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 5 +++ target/r

[PATCH v2 2/2] target/riscv: Support matching scontext in Sdtrig's textra CSRs

Support setting textra32.sselect or textra64.sselect to 1 (scontext). The trigger will only match if the content of scontext matches the value in svalue, after it is masked as configured in sbytemask. Signed-off-by: Florian Lugou --- target/riscv/debug.c | 75

[PATCH 1/2] target/riscv: Add scontext CSR handling

scontext size is 16 bits on RV32 and 32 bits on RV64, as recommended by version 1.0 2025-02-21 of the debug specification. When the Smstateen extension is implemented, accessibility to the scontext CSR is controlled by bit 57 of the [mh]stateen0 CSRs. Signed-off-by: Florian Lugou --- target

[PATCH 2/2] target/riscv: Support matching scontext in Sdtrig's textra CSRs

Support setting textra32.sselect or textra64.sselect to 1 (scontext). The trigger will only match if the content of scontext matches the value in svalue, after it is masked as configured in sbytemask. Signed-off-by: Florian Lugou --- target/riscv/debug.c | 75

[PATCH 0/2] target/riscv: Support scontext-based trigger matching

Hi, These 2 patches allow scontext-based trigger matching as specified by the Sdtrig extension. Patch 1 allows access to the scontext CSR and patch 2 enforces scontext matching as specified by the textra CSRs. Florian Lugou (2): target/riscv: Add scontext CSR handling target/riscv: Support

Re: [PATCH] target/arm/helper: Fix timer interrupt masking when HCR_EL2.E2H == 0

> > $ aarch64-none-elf-gcc -ffreestanding -nostdlib -T > > qemu/tests/tcg/aarch64/system/kernel.ld -o test test.S > > > > $ qemu-system-aarch64 \ > > -machine virt,secure=on,gic-version=3 \ > > -cpu cortex-a57 \ > > -kernel test \ > > -display none \ > > -se

Re: [PATCH] target/arm/helper: Fix timer interrupt masking when HCR_EL2.E2H == 0

On Thu, Jun 20, 2024 at 08:01:01PM +0100, Peter Maydell wrote: > On Thu, 20 Jun 2024 at 14:56, Florian Lugou > wrote: > > > > On Thu, Jun 20, 2024 at 11:43:17AM +0100, Peter Maydell wrote: > > > For this timer check, we're doing I think the same thing

Re: [PATCH] target/arm/helper: Fix timer interrupt masking when HCR_EL2.E2H == 0

On Thu, Jun 20, 2024 at 11:43:17AM +0100, Peter Maydell wrote: > On Sat, 15 Jun 2024 at 19:56, Florian Lugou > wrote: > > > > CNTHCTL_EL2 based masking of timer interrupts was introduced in > > f6fc36deef6abcee406211f3e2f11ff894b87fa4. This masking was however > > e

[PATCH] target/arm/helper: Fix timer interrupt masking when HCR_EL2.E2H == 0

CNTHCTL_EL2 based masking of timer interrupts was introduced in f6fc36deef6abcee406211f3e2f11ff894b87fa4. This masking was however effective no matter whether EL2 was enabled in the current security state or not, contrary to arm specification. Signed-off-by: Florian Lugou --- target/arm

[PATCH] target/arm: Fix PAuth keys access checks for disabled SEL2

As per the description of the HCR_EL2.APK field in the ARMv8 ARM, Pointer Authentication keys accesses should only be trapped to Secure EL2 if it is enabled. Signed-off-by: Florian Lugou --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm