00
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Wed, Jul 02, 2025 at 05:02:13PM +0100, Jonathan Cameron wrote:
> > > > > From: Anisa Su
> > > > >
> > > > > FM DCD Management command 0x5602 implemented p
On Wed, Jul 02, 2025 at 05:02:17PM +0100, Jonathan Cameron wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section
> 7.6.7.6.6
>
> Signed-off-by: Anisa Su
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
>
On Wed, Jul 02, 2025 at 05:02:16PM +0100, Jonathan Cameron wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
>
> Signed-off-by: Anisa Su
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
Only a
n the event log.
>
> Moves definition for CXL_NUM_EXTENTS_SUPPORTED to cxl.h so it can be
> accessed by cxl-mailbox-utils.c and cxl-events.c, where the helper
> function is defined.
>
> Signed-off-by: Anisa Su
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan N
md_set_fm_dcd[256][256] = {
> CXL_MBOX_CONFIG_CHANGE_CXL_RESET |
> CXL_MBOX_IMMEDIATE_CONFIG_CHANGE |
> CXL_MBOX_IMMEDIATE_DATA_CHANGE) },
> +[FMAPI_DCD_MGMT][INITIATE_DC_RELEASE] = { "INIT_DC_RELEASE",
> +cmd_fm_initiate_dc_release, ~0,
> +(CXL_MBOX_CONFIG_CHANGE_COLD_RESET |
> + CXL_MBOX_CONFIG_CHANGE_CONV_RESET |
> + CXL_MBOX_CONFIG_CHANGE_CXL_RESET |
> + CXL_MBOX_IMMEDIATE_CONFIG_CHANGE |
> + CXL_MBOX_IMMEDIATE_DATA_CHANGE) },
> };
>
> /*
> --
> 2.47.2
>
--
Fan Ni (From gmail)
dpa, uint64_t len)
> {
> CXLDCExtentGroup *group;
>
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index 91ec1ba299..7be68d98c6 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -736,4 +736,8 @@ void cxl_create_dc_event_records_for_extents(CXLType3Dev
> *ct3d,
> CXLDCEventType type,
> CXLDCExtentRaw extents[],
> uint32_t ext_count);
> +bool cxl_extents_overlaps_dpa_range(CXLDCExtentList *list,
> +uint64_t dpa, uint64_t len);
> +bool cxl_extent_groups_overlaps_dpa_range(CXLDCExtentGroupList *list,
> + uint64_t dpa, uint64_t len);
> #endif
> --
> 2.47.2
>
--
Fan Ni (From gmail)
n the event log.
>
> Moves definition for CXL_NUM_EXTENTS_SUPPORTED to cxl.h so it can be
> accessed by cxl-mailbox-utils.c and cxl-events.c, where the helper
> function is defined.
>
> Signed-off-by: Anisa Su
Reviewed-by: Fan Ni
> ---
On Wed, Jun 25, 2025 at 03:22:34PM +0100, Alireza Sanaee wrote:
> On Thu, 23 May 2024 10:44:40 -0700
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > A git tree of this series can be found here (with one extra commit on
> > top for printing out accepte
On Fri, Jun 06, 2025 at 11:43:51AM -0700, Fan Ni wrote:
> On Thu, Jun 05, 2025 at 11:42:23PM +, anisa.su...@gmail.com wrote:
> > From: Anisa Su
> >
> > FM DCD Managment command 0x5605 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.6
> >
> >
On Thu, Jun 05, 2025 at 11:42:23PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Managment command 0x5605 implemented per CXL r3.2 Spec Section
> 7.6.7.6.6
>
> Signed-off-by: Anisa Su
See below ..
> ---
> hw/cxl/cxl-mailbox-utils.c | 62
On Thu, Jun 05, 2025 at 11:42:22PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
>
> Signed-off-by: Anisa Su
See below...
> ---
> hw/cxl/cxl-mailbox-utils.c | 152 +
On Thu, Jun 05, 2025 at 11:42:20PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section
> 7.6.7.6.3
>
> Signed-off-by: Anisa Su
> ---
One minor comment, otherwise LGTM.
> hw/cxl/cxl-mailbox-utils.c | 86 +++
;
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_pci.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h
> index d0855ed78b..3bb882ce89 100644
> --- a/include/hw/cxl/
On Tue, May 20, 2025 at 12:56:43PM -0700, nifan@gmail.com wrote:
> From: Fan Ni
>
> Per cxl r3.2 Section 9.13.3.3, extent capacity tracking should include
> extents in different states including added, pending, etc.
>
> Before the change, for the in-device extent number tr
On Thu, May 22, 2025 at 12:01:35PM +0530, Vinayak Holikatti wrote:
> CXL spec 3.2 section 7.6.7.5.2 describes Get Head Info.
>
> Signed-off-by: Vinayak Holikatti
> ---
> This patch is generated against Jonathan Cameron's branch cxl-2025-03-20
>
> hw/cxl/cxl-mailbox-utils.c | 21 +
> h
+{
> > +type_register_static(&cxl_fmw_info);
> > +}
> > +type_init(cxl_host_register_types)
> > diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> > index 70656157ca..9978398876 100644
> > --- a/hw/i386/pc.c
> > +++ b/hw/i386/pc.c
> > @@ -630,7 +630,7 @@ void pc_machine_done(Notifier *notifier, void *data)
> > &error_fatal);
> >
> > if (pcms->cxl_devices_state.is_enabled) {
> > -cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
> > +cxl_fmws_link_targets(&error_fatal);
> > }
> >
> > /* set the number of CPUs */
> > @@ -739,20 +739,28 @@ static uint64_t pc_get_cxl_range_start(PCMachineState
> > *pcms)
> > return cxl_base;
> > }
> >
> > -static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
> > +static int cxl_get_fmw_end(Object *obj, void *opaque)
> > {
> > -uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
> > +struct CXLFixedWindow *fw;
> > +uint64_t *start = opaque;
> >
> > -if (pcms->cxl_devices_state.fixed_windows) {
> > -GList *it;
> > -
> > -start = ROUND_UP(start, 256 * MiB);
> > -for (it = pcms->cxl_devices_state.fixed_windows; it; it =
> > it->next) {
> > -CXLFixedWindow *fw = it->data;
> > -start += fw->size;
> > -}
> > +if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) {
> > +return 0;
> > }
> > +fw = CXL_FMW(obj);
> > +
> > +*start += fw->size;
> >
> > +return 0;
> > +}
> > +
> > +static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
> > +{
> > +uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
> > +
> > +/* Ordering doesn't matter so no need to build a sorted list */
> > +object_child_foreach_recursive(object_get_root(), cxl_get_fmw_end,
> > + &start);
> > return start;
> > }
> >
> > @@ -954,23 +962,10 @@ void pc_memory_init(PCMachineState *pcms,
> > cxl_base = pc_get_cxl_range_start(pcms);
> > memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
> > memory_region_add_subregion(system_memory, cxl_base, mr);
> > -cxl_resv_end = cxl_base + cxl_size;
> > -if (pcms->cxl_devices_state.fixed_windows) {
> > -hwaddr cxl_fmw_base;
> > -GList *it;
> > -
> > -cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
> > -for (it = pcms->cxl_devices_state.fixed_windows; it; it =
> > it->next) {
> > -CXLFixedWindow *fw = it->data;
> > -
> > -fw->base = cxl_fmw_base;
> > -memory_region_init_io(&fw->mr, OBJECT(machine),
> > &cfmws_ops, fw,
> > - "cxl-fixed-memory-region", fw->size);
> > -memory_region_add_subregion(system_memory, fw->base,
> > &fw->mr);
> > -cxl_fmw_base += fw->size;
> > -cxl_resv_end = cxl_fmw_base;
> > -}
> > -}
> > +cxl_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
> > +
> > +cxl_resv_end = cxl_fmws_set_memmap_and_update_mmio(cxl_base,
> > + maxphysaddr);
> > }
> >
> > /* Initialize PC system firmware */
--
Fan Ni (From gmail)
ff-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl.h | 1 +
> hw/cxl/cxl-host.c| 9 ++---
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
> index 75e47b6864..b2bcce7ed6 100644
> ---
t; +++ b/include/hw/cxl/cxl_device.h
> @@ -824,4 +824,8 @@ bool ct3_test_region_block_backed(CXLType3Dev *ct3d,
> uint64_t dpa,
> void cxl_assign_event_header(CXLEventRecordHdr *hdr,
> const QemuUUID *uuid, uint32_t flags,
> uint8_t length, uint64_t timestamp);
> +bool cxl_extents_overlaps_dpa_range(CXLDCExtentList *list,
> +uint64_t dpa, uint64_t len);
> +bool cxl_extent_groups_overlaps_dpa_range(CXLDCExtentGroupList *list,
> + uint64_t dpa, uint64_t len);
> #endif
> diff --git a/include/hw/cxl/cxl_opcodes.h b/include/hw/cxl/cxl_opcodes.h
> index ad4e614daa..72ea0a7d44 100644
> --- a/include/hw/cxl/cxl_opcodes.h
> +++ b/include/hw/cxl/cxl_opcodes.h
> @@ -66,5 +66,6 @@ enum {
> #define GET_HOST_DC_REGION_CONFIG 0x1
> #define SET_DC_REGION_CONFIG 0x2
> #define GET_DC_REGION_EXTENT_LIST 0x3
> +#define INITIATE_DC_ADD 0x4
> GLOBAL_MEMORY_ACCESS_EP_MGMT = 0X59
> };
> --
> 2.47.2
>
--
Fan Ni
On Thu, May 08, 2025 at 12:01:04AM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5603 implemented per CXL r3.2 Spec Section
> 7.6.7.6.4
> Very similar to previously implemented command 0x4801.
>
> Signed-off-by: Anisa Su
6,11 @@
> #define CXL_MBOX_SECURITY_STATE_CHANGE (1 << 5)
> #define CXL_MBOX_BACKGROUND_OPERATION (1 << 6)
> #define CXL_MBOX_BACKGROUND_OPERATION_ABORT (1 << 7)
> +#define CXL_MBOX_SECONDARY_MBOX_SUPPORTED (1 << 8)
> +#define CXL_MBOX_REQUEST_ABORT_BACKGROUND_OP_SUPPORTED (1 << 9)
> +#define CXL_MBOX_CEL_10_TO_11_VALID (1 << 10)
> +#define CXL_MBOX_CONFIG_CHANGE_CONV_RESET (1 << 11)
> +#define CXL_MBOX_CONFIG_CHANGE_CXL_RESET (1 << 12)
>
> #define CXL_LOG_CAP_CLEAR_SUPPORTED (1 << 0)
> #define CXL_LOG_CAP_POPULATE_SUPPORTED (1 << 1)
> diff --git a/include/hw/cxl/cxl_opcodes.h b/include/hw/cxl/cxl_opcodes.h
> index 68ad68291c..ed4be23b75 100644
> --- a/include/hw/cxl/cxl_opcodes.h
> +++ b/include/hw/cxl/cxl_opcodes.h
> @@ -64,5 +64,6 @@ enum {
> FMAPI_DCD_MGMT = 0x56,
> #define GET_DCD_INFO 0x0
> #define GET_HOST_DC_REGION_CONFIG 0x1
> +#define SET_DC_REGION_CONFIG 0x2
> GLOBAL_MEMORY_ACCESS_EP_MGMT = 0X59
> };
> --
> 2.47.2
>
--
Fan Ni
touch the blk_bitmap to ensure the range
to access is backed by DC blocks through ct3_test_region_block_backed().
Otherwise,
Reviewed-by: Fan Ni
>
> Signed-off-by: Anisa Su
> ---
> hw/mem/cxl_type3.c | 4
> include/hw/cxl/cxl_device.h | 1 +
> 2 files change
On Thu, May 08, 2025 at 12:01:01AM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> Move definition/enum to cxl_events.h for shared use in next patch
>
> Signed-off-by: Anisa Su
> ---
Reviewed-by: Fan Ni
> hw/mem/cxl_type3.c | 15
On Thu, May 08, 2025 at 12:01:00AM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5601 implemented per CXL r3.2 Spec Section
> 7.6.7.6.2
>
> Signed-off-by: Anisa Su
One minor comment inline. Otherwise,
Reviewed-by: Fan Ni
> ---
/, otherwise
Reviewed-by: Fan Ni
> response.
>
> Signed-off-by: Anisa Su
> ---
> hw/mem/cxl_type3.c | 8 +++-
> include/hw/cxl/cxl_device.h | 15 +++
> 2 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/hw/mem/cxl_type3.c
On Thu, May 08, 2025 at 12:00:58AM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section
> 7.6.7.6.1.
>
> Signed-off-by: Anisa Su
LGTM. minor comments inline.
Reviewed-by: Fan Ni
> ---
> hw
#define GET_SCAN_MEDIA_CAPABILITIES 0x3
> +#define SCAN_MEDIA 0x4
> +#define GET_SCAN_MEDIA_RESULTS 0x5
> +DCD_CONFIG = 0x48,
> +#define GET_DC_CONFIG 0x0
> +#define GET_DYN_CAP_EXT_LIST 0x1
> +#define ADD_DYN_CAP_RSP0x2
> +#define RELEASE_DYN_CAP0x3
> +PHYSICAL_SWITCH = 0x51,
> +#define IDENTIFY_SWITCH_DEVICE 0x0
> +#define GET_PHYSICAL_PORT_STATE 0x1
> +TUNNEL = 0x53,
> +#define MANAGEMENT_COMMAND 0x0
> +MHD = 0x55,
> +#define GET_MHD_INFO 0x0
> +};
> --
> 2.47.2
>
--
Fan Ni
On Fri, May 02, 2025 at 10:01:55AM +0100, Jonathan Cameron wrote:
> On Thu, 1 May 2025 20:21:56 +
> Fan Ni wrote:
>
> > On Thu, Apr 24, 2025 at 11:42:59AM +0100, Jonathan Cameron wrote:
> > > On Mon, 17 Mar 2025 16:31:30 +
> > > anisa.su...@gmail.com wr
On Thu, Apr 24, 2025 at 11:42:59AM +0100, Jonathan Cameron wrote:
> On Mon, 17 Mar 2025 16:31:30 +
> anisa.su...@gmail.com wrote:
>
> > From: Anisa Su
> >
> > Add dsmas_flags field to DC Region struct in preparation for next
> > command, which returns the dsmas flags in the response.
> >
>
On Thu, Apr 24, 2025 at 12:23:08PM +0100, Jonathan Cameron wrote:
> On Mon, 17 Mar 2025 16:31:36 +
> anisa.su...@gmail.com wrote:
>
> > From: Anisa Su
> >
> > FM DCD Managment command 0x5605 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.6
> >
> > Signed-off-by: Anisa Su
> Similar comm
On Thu, Apr 24, 2025 at 12:19:59PM +0100, Jonathan Cameron wrote:
> On Mon, 17 Mar 2025 16:31:35 +
> anisa.su...@gmail.com wrote:
>
> > From: Anisa Su
> >
> > FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> > 7.6.7.6.5
> >
> > Signed-off-by: Anisa Su
> > ---
...
>
On Tue, Apr 08, 2025 at 11:04:20AM -0400, Gregory Price wrote:
> On Mon, Apr 07, 2025 at 09:20:27PM -0700, nifan@gmail.com wrote:
> > From: Fan Ni
> >
> > The RFC provides a way for FM emulation in Qemu. The goal is to provide
> > a context where we can have more F
On Wed, Mar 12, 2025 at 03:33:12PM -0400, Gregory Price wrote:
> On Wed, Mar 12, 2025 at 06:05:43PM +, Jonathan Cameron wrote:
> >
> > Longer term I remain a little unconvinced by whether this is the best
> > approach
> > because I also want a single management path (so fake CCI etc) and that
On Wed, Mar 12, 2025 at 03:33:12PM -0400, Gregory Price wrote:
> On Wed, Mar 12, 2025 at 06:05:43PM +, Jonathan Cameron wrote:
> >
> > Longer term I remain a little unconvinced by whether this is the best
> > approach
> > because I also want a single management path (so fake CCI etc) and that
On Thu, Feb 13, 2025 at 03:09:05PM +0800, Yuquan Wang wrote:
> On Tue, Feb 11, 2025 at 09:26:55AM +, Jonathan Cameron wrote:
> > On Tue, 11 Feb 2025 10:24:13 +0800
> > Yuquan Wang wrote:
> >
> > > The previous default value of sn is UI64_NULL which would cause the
> > > cookie of nd_interleav
> +typedef struct CXLValidEnableAlerts {
> +uint8_t lupwt:1;
> +uint8_t dotpwt:1;
> +uint8_t dutpwt:1;
> +uint8_t cvmepwt:1;
> +uint8_t cpmepwt:1;
> +uint8_t reserved:3;
> +} CXLValidEnableAlerts;
> +
> +typedef struct CXLAlertConfig {
> +CXLValidEnableAlerts valid_alerts;
> +CXLValidEnableAlerts enable_alerts;
> +uint8_t lucat;
> +uint8_t lupwt;
> +uint16_t dotcat;
> +uint16_t dutcat;
> +uint16_t dotpwt;
> +uint16_t dutpwt;
> +uint16_t cvmepwt;
> +uint16_t cpmepwt;
> +} QEMU_PACKED CXLAlertConfig;
> +
> struct CXLType3Dev {
> /* Private */
> PCIDevice parent_obj;
> @@ -605,6 +627,8 @@ struct CXLType3Dev {
> CXLCCI vdm_fm_owned_ld_mctp_cci;
> CXLCCI ld0_cci;
>
> +CXLAlertConfig alert_config;
> +
> /* PCIe link characteristics */
> PCIExpLinkSpeed speed;
> PCIExpLinkWidth width;
> --
> 2.34.1
>
--
Fan Ni (From gmail)
240409075846.85370-1-lizhij...@fujitsu.com/
>
Hi Zhijian,
Thanks for the pointer. With the fix applied, the issue goes away.
Fan
>
> On 15/01/2025 04:30, Fan Ni wrote:
> > Hi,
> >
> > Recently, while testing cxl with qemu setup, I found the memdev cannot
> > be e
;
> Reported-by: Peter Maydell
> Signed-off-by: Jonathan Cameron
> ---
> hw/cxl/cxl-mailbox-utils.c | 4
> 1 file changed, 4 insertions(+)
Reviewed-by: Fan Ni
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 2d4d62c454..ce9aa
the only possible failure would be if the mailbox itself isn't big
* enough.
"
Not sure how it avoids the case when the offset is too large.
Fan
> return CXL_MBOX_INVALID_INPUT;
> }
>
> --
> 2.43.0
>
--
Fan Ni
On Fri, Nov 01, 2024 at 01:39:16PM +, Jonathan Cameron wrote:
> The properties of the requested set command cannot be established if
> len_in is less than the size of the header.
>
> Reported-by: Esifiel
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
>
: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/cxl/cxl-mailbox-utils.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index f4a436e172..2d4d62c454 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-ma
s used to accumulate the full feature
s/fo/of/
> attribute set.
Other than that,
Reviewed-by: Fan Ni
>
> Reported-by: Esifiel
> Signed-off-by: Jonathan Cameron
> ---
> hw/cxl/cxl-mailbox-utils.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/hw/
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Fan Ni
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 5e571955b6..a40d81219c 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c
> @@ -151,6 +151,9 @@ static CXLRetC
t + get_log->length >= sizeof(cci->cel_log))
> {
> return CXL_MBOX_INVALID_INPUT;
Oh. This patch actually addresses my concern in the previous patch.
Maybe we can combine the changes in this patch and the previous one
together. Other than that
Reviewed-by: Fan Ni
o avoid this.
>
> Reported-by: Esifiel
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/cxl/cxl-mailbox-utils.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 3cb499a24
located as a duplicate of the incoming message buffer.
>
> Reported-by: Esifiel
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/cxl/cxl-mailbox-utils.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cx
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/cxl/cxl-mailbox-utils.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 17924410dd..e63140aefe 100644
> --- a/hw/cxl/cxl-mai
e second
> that there is enough for those elements to be accessed.
>
> Reported-by: Esifiel
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> hw/cxl/cxl-mailbox-utils.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/hw/cxl/cxl-m
nfig_write;
> k->realize = cxl_dsp_realize;
> k->exit = cxl_dsp_exitfn;
> @@ -243,7 +241,6 @@ static const TypeInfo cxl_dsp_info = {
> .name = TYPE_CXL_DSP,
> .instance_size = sizeof(CXLDownstreamPort),
> .parent = TYPE_PCIE_SLOT,
> -.instance_post_init = cxl_dsp_instance_post_init,
> .class_init = cxl_dsp_class_init,
> .interfaces = (InterfaceInfo[]) {
> { INTERFACE_PCIE_DEVICE },
> --
> 2.43.0
>
--
Fan Ni
res_reserve.mem_pref_64,
> -1),
> +DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
> +speed, PCIE_LINK_SPEED_64),
> +DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
> +width, PCIE_LINK_WIDTH_32),
> DEFINE_PROP_END_OF_LIST()
> };
LGTM.
Reviewed-by: Fan Ni
Fan
>
> --
> 2.43.0
>
--
Fan Ni
On Mon, Oct 14, 2024 at 12:23:22PM +0100, Jonathan Cameron wrote:
> On Fri, 11 Oct 2024 13:24:50 -0700
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > One DC extent add/release request can take multiple DC extents.
> > For each extent in the req
On Wed, Oct 16, 2024 at 05:01:38PM +0100, Jonathan Cameron wrote:
> On Tue, 8 Oct 2024 20:01:07 -0700
> Davidlohr Bueso wrote:
>
> > On Tue, 08 Oct 2024, nifan@gmail.com wrote:\n
> > >From: Fan Ni
> > >
> > >In the function cmd_firmware_update_get_
On Wed, Oct 09, 2024 at 06:41:57PM -0700, Davidlohr Bueso wrote:
> Add Get/Set Response Message Limit commands.
>
> Signed-off-by: Davidlohr Bueso
The commit log may include the cxl spec reference. Otherwise,
Reviewed-by: Fan Ni
> ---
> hw/cxl/cxl-mailb
On Wed, Sep 04, 2024 at 11:37:33AM -0500, Ira Weiny wrote:
> Jonathan Cameron wrote:
> > On Tue, 27 Aug 2024 09:40:05 -0700
> > nifan@gmail.com wrote:
> >
> > > From: Fan Ni
> > >
> > > When inserting multiple dynamic capacity event records gr
On Thu, Aug 08, 2024 at 11:13:27PM +0800, Shiyang Ruan wrote:
> CXL device can find&report memory problems, even before MCE is detected
> by CPU. AFAIK, the current kernel only traces POISON error event
> from FW-First/OS-First path, but it doesn't handle them, neither
> notify processes who are u
On Thu, Jul 18, 2024 at 05:07:53AM -0400, Yao Xingtao wrote:
> style="display:none
> !important;display:none;visibility:hidden;mso-hide:all;font-size:1px;color:#ff;line-height:1px;height:0px;max-height:0px;opacity:0;overflow:hidden;">
> When injecting a new poisoned region through qmp_cxl_in
V_CAP_ARRAY, CAP_COUNT, cap_count);
> +ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_ID, 0);
> +ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1);
> +ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_COUNT, cap_count);
>
> cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1, 2);
> device_reg_init_common(cxl_dstate);
> --
> 2.39.2
>
Reviewed-by: Fan Ni
On Fri, Sep 29, 2023 at 09:50:16AM +0200, Markus Armbruster wrote:
> Jonathan Cameron writes:
>
> > On Wed, 27 Sep 2023 19:13:35 +0000
> > Fan Ni wrote:
> >
> >> On Mon, Sep 25, 2023 at 04:22:58PM +0100, Jonathan Cameron wrote:
> >>
> >> >
is no longer an opaque structure.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/pci-bridge/cxl_upstream_port.h | 18 ++
> hw/pci-bridge/cxl_upstream.c | 11 +--
> 2 files changed, 19 insertions(+), 10 deletions(
; Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_device.h | 5 +++-
> hw/cxl/cxl-device-utils.c | 51 -
> hw/cxl/cxl-mailbox-utils.c | 43 ---
> 3 files changed, 64 insertions(+), 35
On Mon, Sep 25, 2023 at 05:11:08PM +0100, Jonathan Cameron wrote:
> Enables having multiple CCIs per devices. Each CCI (mailbox) has it's own
> state and command list, so they can't share a single structure.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: F
low
> for that.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_device.h | 7 +-
> hw/cxl/cxl-events.c | 2 +-
> hw/cxl/cxl-mailbox-utils.c | 222 +---
> 3 files changed, 132 insertions(+),
t;
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_device.h | 13
> hw/cxl/cxl-mailbox-utils.c | 121 +++-
> 2 files changed, 78 insertions(+), 56 deletions(-)
>
> diff --git a/include/hw/cxl/cxl_devic
On Mon, Sep 25, 2023 at 04:22:58PM +0100, Jonathan Cameron wrote:
> Rename the version not burried in the macro to cap_h.
The change looks good to me. Just one minor thing. why "version" get
involved here?
Fan
>
> Signed-off-by: Jonathan Cameron
> ---
>
> I had another instance of this in a se
On Fri, Sep 15, 2023 at 06:04:18PM +0100, Jonathan Cameron wrote:
> Michael Tsirkin observed that there were some unnecessarily
> long lines in the CXL code in a recent review.
> This patch is intended to rectify that where it does not
> hurt readability.
>
> Reviewed-by: Michael Tokarev
> Signed
On Fri, Sep 15, 2023 at 06:04:17PM +0100, Jonathan Cameron wrote:
> Done to reduce line lengths where this is used.
> Ext seems sufficiently obvious that it need not be spelt out
> fully.
>
> Signed-off-by: Jonathan Cameron
> Reviewed-by: Philippe Mathieu-Daudé
> ---
rce that the register storage is of the
> matching size, allowing fixed values to be used for divisors of
> the array indices.
>
> Suggested-by: Michael Tokarev
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> v2: Use switch statements. Note we coudl have renamed
hilippe Mathieu-Daudé
> ---
Reviewed-by: Fan Ni
> hw/cxl/cxl-device-utils.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
> index 517f06d869..cd0c45a2ed 100644
> --- a/hw/cxl/cxl-device
On Mon, Sep 18, 2023 at 04:02:59PM +0100, Jonathan Cameron wrote:
> These crossed with the previous fix to get rid of examples
> using aarch64 for which support is not yet upstream.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> docs/system/devices/cxl
: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/mem/cxl_type3.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index c5855d4e7d..ad3f0f6a9d 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1,3 +1,
On Mon, Sep 18, 2023 at 04:02:57PM +0100, Jonathan Cameron wrote:
> From: Dmitry Frolov
>
> According to cxl_interleave_ways_enc(), fw->num_targets is allowed to be up
> to 16. This also corresponds to CXL r3.0 spec. So, the fw->target_hbs[]
> array is iterated from 0 to 15. But it is staticaly
jian@cn.fujitsu.com__;!!EwVzqGoTKBqv-0DWAJBm!TWHVrdL5Ys7OOFU_w1CJQ5DC6mxu649kYA9GYDJ182CNPuQqpVkWYsB5mlJpVd_BAAmhxCD4Si2CkMERZI7ZE03kPz2c$
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> docs/system/devices/cxl.rst | 8
> 1 file changed, 4 insertions(+), 4
0, the BW is 100 GB/s. So the
> entry_base_unit should be changed from 1000 to 1024 given the comment notes
> it's 16GB/s for .latency_bandwidth.
>
> Fixes: 882877fc359d ("hw/pci-bridge/cxl-upstream: Add a CDAT table access
> DOE")
> Signed-off-by: Dave Jian
wed-by: Philippe Mathieu-Daudé
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> hw/cxl/cxl-host.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
> index 034c7805b3..f0920da956 100644
On Mon, Sep 04, 2023 at 05:18:46PM +0100, Jonathan Cameron wrote:
> From: Dave Jiang
>
> Add a simple _DSM call support for the ACPI0017 device to return a fake QTG
> ID value of 0 in all cases. The enabling is for _DSM plumbing testing
> from the OS.
>
> Following edited for readbility only
>
On Mon, Sep 04, 2023 at 05:18:45PM +0100, Jonathan Cameron wrote:
> Addition of QTG in following patch requires an update to the test
> data.
>
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file
On Mon, Sep 04, 2023 at 05:18:47PM +0100, Jonathan Cameron wrote:
> Description of change in previous patch.
>
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 -
> tests/data/acpi/q35/DSDT.cxl
On Mon, Sep 11, 2023 at 12:43:13PM +0100, Jonathan Cameron wrote:
> Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP
> and CXL Type 3 end points.
>
> Signed-off-by: Jonathan Cameron
>
> ---
One comment inline, other than that, looks good to me.
> v3: Factor out the hdm_in
so the bugs this
> fixes don't actually affect anything. Previously the offset didn't
> take into account that the write_msk etc are 4 byte fields.
>
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> --
> v3:
> New patch to separate this out from the additi
udé
> Signed-off-by: Jonathan Cameron
> ---
LGTM. Only one minor comment inline.
Reviewed-by: Fan Ni
> v3: No changes, picked up tags.
> v2: Thanks to Philippe Mathieu-Daudé
> - Expand both enc() and dec() functions to include full set of values
>defined in CXL r3.0
é
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> include/hw/cxl/cxl_component.h | 18 ++
> hw/cxl/cxl-component-utils.c | 18 ++
> 2 files changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/include/hw/
On Fri, Sep 08, 2023 at 01:00:16PM +, J?rgen Hansen wrote:
> On 7/25/23 20:39, Fan Ni wrote:
> > From: Fan Ni
> >
> > Per CXL spec 3.0, two mailbox commands are implemented:
> > Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
> > Relea
On Fri, Sep 08, 2023 at 01:12:45PM +, J?rgen Hansen wrote:
> On 7/25/23 20:39, Fan Ni wrote:
> > From: Fan Ni
> >
> > Add dynamic capacity extent list representative to the definition of
> > CXLType3Dev and add get DC extent list mailbox command per
&g
On Fri, Aug 25, 2023 at 12:42:56PM +0100, Jonathan Cameron wrote:
> On Thu, 24 Aug 2023 13:49:00 -0700
> Fan Ni wrote:
>
> > On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> > > On Tue, 25 Jul 2023 18:39:56 +
> > > Fan Ni
On Mon, Aug 07, 2023 at 09:53:42AM +0100, Jonathan Cameron wrote:
> On Tue, 25 Jul 2023 18:39:56 +
> Fan Ni wrote:
>
> > From: Fan Ni
> >
> > Not all dpa range in the dc regions is valid to access until an extent
> > covering the range has been added
n use
numactl --membind=numa_id app_name
#numa_id is the dedicated numa node where cxl memory sits.
One thing to notes, kvm will not work correctly with Qemu emulation when
you try to use cxl memory for an application, so do not enable kvm.
Fan
> On Thu, 10 Aug 2023 at 22:03, Fan Ni wrote:
On Wed, Aug 09, 2023 at 04:21:47AM +0530, Maverickk 78 wrote:
> Hello,
>
> I am running qemu-system-x86_64
>
> qemu-system-x86_64 --version
> QEMU emulator version 8.0.92 (v8.1.0-rc2-80-g0450cf0897)
>
> qemu-system-x86_64 \
> -m 2G,slots=4,maxmem=4G \
> -smp 4 \
> -machine type=q35,accel=kvm,cxl=on
From: Fan Ni
Per cxl spec 3.0, add dynamic capacity region representative based on
Table 8-126 and extend the cxl type3 device definition to include dc region
information. Also, based on info in 8.2.9.8.9.1, add 'Get Dynamic Capacity
Configuration' mailbox support.
Signed-off-
From: Fan Ni
Not all dpa range in the dc regions is valid to access until an extent
covering the range has been added. Add a bitmap for each region to
record whether a dc block in the region has been backed by dc extent.
For the bitmap, a bit in the bitmap represents a dc block. When a dc
extent
From: Fan Ni
Rename mem_size as static_mem_size for type3 memdev to cover static RAM and
pmem capacity, preparing for the introduction of dynamic capacity to support
dynamic capacity devices.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 5 +++--
hw/mem/cxl_type3.c | 8
From: Fan Ni
Add (file/memory backed) host backend, all the dynamic capacity regions
will share a single, large enough host backend. Set up address space for
DC regions to support read/write operations to dynamic capacity for DCD.
With the change, following supports are added:
1. add a new
From: Fan Ni
Since fabric manager emulation is not supported yet, the change implements
the functions to add/release dynamic capacity extents as QMP interfaces.
1. Add dynamic capacity extents:
For example, the command to add two continuous extents (each is 128MB long)
to region 0 (starting at
b2945b@iweiny-mobl.notmuch/T/#m09983a3dbaa9135a850e345d86714bf2ab957ef6
Fan Ni (9):
hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output
payload of identify memory device command
hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative
and mailbox command support
From: Fan Ni
Per CXL spec 3.0, two mailbox commands are implemented:
Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and
Release Dynamic Capacity (Opcode 4803h) 8.2.9.8.9.4.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 253
include/hw
From: Fan Ni
Add dynamic capacity extent list representative to the definition of
CXLType3Dev and add get DC extent list mailbox command per
CXL.spec.3.0:.8.2.9.8.9.2.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox-utils.c | 71 +
hw/mem/cxl_type3.c
From: Fan Ni
Based on CXL spec 3.0 Table 8-94 (Identify Memory Device Output
Payload), dynamic capacity event log size should be part of
output of the Identify command.
Add dc_event_log_size to the output payload for the host to get the info.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox
From: Fan Ni
With the change, when setting up memory for type3 memory device, we can
create DC regions
A property 'num-dc-regions' is added to ct3_props to allow users to pass the
number of DC regions to create. To make it easier, other region parameters
like region base, length, and
On Tue, Jul 25, 2023 at 08:18:08AM -0700, Ira Weiny wrote:
> Fan Ni wrote:
> > On Thu, May 11, 2023 at 05:56:40PM +0000, Fan Ni wrote:
> >
> > FYI.
> >
> > I have updated the patch series and sent out again.
> >
> > I suggested anyone who are int
On Thu, May 11, 2023 at 05:56:40PM +, Fan Ni wrote:
FYI.
I have updated the patch series and sent out again.
I suggested anyone who are interested in DCD and using this patch series to
use the new series. Quite a few things has been fixed.
https://lore.kernel.org/linux-cxl
-cxl/20230724162313.34196-1-fan...@samsung.com/T/#t
Thanks,
Fan
> On Sat, 22 Jul 2023 21:52:06 -0700
> Ira Weiny wrote:
>
> > nifan@ wrote:
> > > From: Fan Ni
> > >
> > > The patch series provides dynamic capacity device (DCD) emulation in
> >
From: Fan Ni
Based on CXL spec 3.0 Table 8-94 (Identify Memory Device Output
Payload), dynamic capacity event log size should be part of
output of the Identify command.
Add dc_event_log_size to the output payload for the host to get the info.
Signed-off-by: Fan Ni
---
hw/cxl/cxl-mailbox
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