[PATCH] qemu-options.hx: Fix reversed description of icount sleep behavior

The documentation for the -icount option incorrectly describes the behavior of the sleep suboption. Based on the actual implementation and system behavior, the effects of sleep=on and sleep=off were inadvertently reversed. This commit updates the description to reflect their intended functionality.

Re: [PATCH] accel/tcg: Make round-robin kick period configurable

> On 5/6/25 08:18, Ethan Chen via wrote: > > This change introduces a configurable round-robin kick period, giving users > > the > > flexibility to balance SMP simulation accuracy and performance according to > > their specific needs. > > > > The round-r

[PATCH] accel/tcg: Make round-robin kick period configurable

This change introduces a configurable round-robin kick period, giving users the flexibility to balance SMP simulation accuracy and performance according to their specific needs. The round-robin kick period is the time one vCPU can run before scheduler switches to another vCPU when using a single t

Re: [PATCH v11 8/8] hw/riscv/virt: Add IOPMP support

On Thu, May 22, 2025 at 11:24:28AM +1000, Alistair Francis wrote: > [EXTERNAL MAIL] > > On Wed, Mar 12, 2025 at 7:43 PM Ethan Chen via wrote: > > > > - Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine > > to protect all regions of

[PATCH v11 3/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size

If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be multiple entries within the same page. To obtain the correct result, pass the original address to the IOMMU. Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when there are multiple entries in the same

[PATCH v11 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation

The entire valid transaction must fit within a single IOPMP entry. However, during IOMMU translation, the transaction size is not available. This structure defines the transaction information required by the IOPMP. Signed-off-by: Ethan Chen --- include/hw/misc/riscv_iopmp_txn_info.h | 38 +++

[PATCH v11 0/8] Support RISC-V IOPMP

When IOPMP is enabled, memory access to system memory from devices and the CPU will be checked by the IOPMP. The issue of CPU access to non-CPU address space via IOMMU was previously mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires this patch. You can use a customized

[PATCH v11 2/8] memory: Introduce memory region fetch operation

Allow memory regions to have different behaviors for read and fetch operations. For example, the RISC-V IOPMP could raise an interrupt when the CPU tries to fetch from a non-executable region. If the fetch operation for a memory region is not implemented, the read operation will still be used for

[PATCH v11 8/8] hw/riscv/virt: Add IOPMP support

- Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine to protect all regions of system memory. Signed-off-by: Ethan Chen --- docs/specs/index.rst | 1 + docs/specs/riscv-iopmp.rst | 60 ++ docs/system/riscv/virt.rst | 9 + hw/riscv/

[PATCH v11 6/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

Support IOPMP specification v0.7. The specification url: https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.7 The IOPMP checks whether memory access from a device or CPU is valid. This implementation uses an IOMMU to modify the address space accessed by the device. For device access with

[PATCH v11 4/8] target/riscv: Add support for IOPMP

Signed-off-by: Ethan Chen Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 3 +++ target/riscv/cpu_cfg.h| 2 ++ target/riscv/cpu_helper.c | 18 +++--- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 09de

[PATCH v11 7/8] hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction infomation

This device determines the target IOPMP device for forwarding information based on: * Address: For parallel IOPMP devices * Stage: For cascading IOPMP devices Signed-off-by: Ethan Chen --- hw/misc/meson.build | 1 + hw/misc/riscv_iopmp_dispatcher.c | 139 ++

[PATCH v11 1/8] hw/core: Add config stream

Make other device can use /hw/core/stream.c by select this config. Reviewed-by: Alistair Francis Signed-off-by: Ethan Chen --- hw/Kconfig | 1 + hw/core/Kconfig | 3 +++ hw/core/meson.build | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/Kconfig b/hw/Kconfi

[PATCH v10 8/8] hw/riscv/virt: Add IOPMP support

- Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine to protect all regions of system memory. Signed-off-by: Ethan Chen --- docs/system/riscv/virt.rst | 7 hw/riscv/Kconfig | 1 + hw/riscv/virt.c| 75 ++ in

[PATCH v10 7/8] hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction infomation

This device determines the target IOPMP device for forwarding information based on: * Address: For parallel IOPMP devices * Stage: For cascading IOPMP devices Signed-off-by: Ethan Chen --- hw/misc/meson.build | 1 + hw/misc/riscv_iopmp_dispatcher.c | 136 ++

[PATCH v10 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation

The entire valid transaction must fit within a single IOPMP entry. However, during IOMMU translation, the transaction size is not available. This structure defines the transaction information required by the IOPMP. Signed-off-by: Ethan Chen --- include/hw/misc/riscv_iopmp_txn_info.h | 38 +++

[PATCH v10 6/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

Support IOPMP specification v0.9.2RC3. The specification url: https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.2-RC3 The IOPMP checks whether memory access from a device or CPU is valid. This implementation uses an IOMMU to modify the address space accessed by the device. For device

[PATCH v10 2/8] memory: Introduce memory region fetch operation

Allow memory regions to have different behaviors for read and fetch operations. For example, the RISC-V IOPMP could raise an interrupt when the CPU tries to fetch from a non-executable region. If the fetch operation for a memory region is not implemented, the read operation will still be used for

[PATCH v10 0/8] Support RISC-V IOPMP

When IOPMP is enabled, memory access to system memory from devices and the CPU will be checked by the IOPMP. The issue of CPU access to non-CPU address space via IOMMU was previously mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires this patch. You can use a customized

[PATCH v10 4/8] target/riscv: Add support for IOPMP

Signed-off-by: Ethan Chen Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 3 +++ target/riscv/cpu_cfg.h| 2 ++ target/riscv/cpu_helper.c | 18 +++--- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3d4b

[PATCH v10 1/8] hw/core: Add config stream

Make other device can use /hw/core/stream.c by select this config. Reviewed-by: Alistair Francis Signed-off-by: Ethan Chen --- hw/Kconfig | 1 + hw/core/Kconfig | 3 +++ hw/core/meson.build | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/Kconfig b/hw/Kconfi

[PATCH v10 3/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size

If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be multiple entries within the same page. To obtain the correct result, pass the original address to the IOMMU. Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when there are multiple entries in the same

[PATCH v9 0/8] Support RISC-V IOPMP

When IOPMP is enabled, memory access to system memory from devices and the CPU will be checked by the IOPMP. The issue of CPU access to non-CPU address space via IOMMU was previously mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires this patch. You can use a customized

[PATCH v9 4/8] target/riscv: Add support for IOPMP

Signed-off-by: Ethan Chen Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 3 +++ target/riscv/cpu_cfg.h| 2 ++ target/riscv/cpu_helper.c | 18 +++--- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8d5

[PATCH v9 3/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size

If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be multiple entries within the same page. To obtain the correct result, pass the original address to the IOMMU. Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when there are multiple entries in the same

[PATCH v9 6/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

Support IOPMP specification v0.9.2RC3. The specification url: https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.2-RC3 The IOPMP checks whether memory access from a device or CPU is valid. This implementation uses an IOMMU to modify the address space accessed by the device. For device

[PATCH v9 8/8] hw/riscv/virt: Add IOPMP support

- Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine to protect all regions of system memory. Signed-off-by: Ethan Chen --- docs/system/riscv/virt.rst | 7 hw/riscv/Kconfig | 1 + hw/riscv/virt.c| 75 ++ in

[PATCH v9 7/8] hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction infomation

This device determines the target IOPMP device for forwarding information based on: * Address: For parallel IOPMP devices * Stage: For cascading IOPMP devices Signed-off-by: Ethan Chen --- hw/misc/meson.build | 1 + hw/misc/riscv_iopmp_dispatcher.c | 136 ++

[PATCH v9 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation

The entire valid transaction must fit within a single IOPMP entry. However, during IOMMU translation, the transaction size is not available. This structure defines the transaction information required by the IOPMP. Signed-off-by: Ethan Chen --- include/hw/misc/riscv_iopmp_txn_info.h | 38 +++

[PATCH v9 2/8] memory: Introduce memory region fetch operation

Allow memory regions to have different behaviors for read and fetch operations. For example, the RISC-V IOPMP could raise an interrupt when the CPU tries to fetch from a non-executable region. If the fetch operation for a memory region is not implemented, the read operation will still be used for

[PATCH v9 1/8] hw/core: Add config stream

Make other device can use /hw/core/stream.c by select this config. Reviewed-by: Alistair Francis Signed-off-by: Ethan Chen --- hw/Kconfig | 1 + hw/core/Kconfig | 3 +++ hw/core/meson.build | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/Kconfig b/hw/Kconfi

Re: [PATCH v8 0/8] Support RISC-V IOPMP

On Tue, Nov 05, 2024 at 03:36:07PM -0300, Daniel Henrique Barboza wrote: > [EXTERNAL MAIL] > > Hi Ethan, > > > Do you plan to send a new version of this work? It seems to me that we're > a couple of reviews away from getting it merged. > Hi Daniel, Thanks for checking in! I do plan to send an

Re: [PATCH v8 8/8] hw/riscv/virt: Add IOPMP support

On Mon, Aug 12, 2024 at 10:48:40AM +1000, Alistair Francis wrote: > [EXTERNAL MAIL] > > On Fri, Aug 9, 2024 at 8:14 PM Ethan Chen wrote: > > > > On Thu, Aug 08, 2024 at 02:01:13PM +1000, Alistair Francis wrote: > > > > > > On Mon, Jul 15, 2024

Re: [PATCH v8 5/8] hw/misc/riscv_iopmp: Add API to set up IOPMP protection for system memory

On Mon, Aug 12, 2024 at 10:47:33AM +1000, Alistair Francis wrote: > [EXTERNAL MAIL] > > On Fri, Aug 9, 2024 at 8:11 PM Ethan Chen wrote: > > > > On Thu, Aug 08, 2024 at 02:23:56PM +1000, Alistair Francis wrote: > > > > > > On Mon, Jul 15, 2024

Re: [PATCH v8 8/8] hw/riscv/virt: Add IOPMP support

On Thu, Aug 08, 2024 at 02:01:13PM +1000, Alistair Francis wrote: > > On Mon, Jul 15, 2024 at 8:15 PM Ethan Chen via wrote: > > > > - Add 'iopmp=on' option to enable IOPMP. It adds an iopmp device virt > > machine > > to protect all regions of s

Re: [PATCH v8 5/8] hw/misc/riscv_iopmp: Add API to set up IOPMP protection for system memory

On Thu, Aug 08, 2024 at 02:23:56PM +1000, Alistair Francis wrote: > > On Mon, Jul 15, 2024 at 8:13 PM Ethan Chen via wrote: > > > > To enable system memory transactions through the IOPMP, memory regions must > > be moved to the IOPMP downstream and then replac

Re: [PATCH v8 4/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

On Thu, Aug 08, 2024 at 01:56:35PM +1000, Alistair Francis wrote: > [EXTERNAL MAIL] > > On Mon, Jul 15, 2024 at 7:58 PM Ethan Chen via wrote: > > > > Support basic functions of IOPMP specification v0.9.1 rapid-k model. > > The specification url: > > https://gi

Re: [PATCH v8 6/8] hw/misc/riscv_iopmp: Add API to configure RISCV CPU IOPMP support

On Thu, Aug 08, 2024 at 02:25:04PM +1000, Alistair Francis wrote: > > On Mon, Jul 15, 2024 at 8:15 PM Ethan Chen via wrote: > > > > The iopmp_setup_cpu() function configures the RISCV CPU to support IOPMP and > > specifies the CPU's RRID. > > > > Signed

Re: [PATCH v8 4/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

On Thu, Aug 08, 2024 at 01:56:35PM +1000, Alistair Francis wrote: > [EXTERNAL MAIL] > > On Mon, Jul 15, 2024 at 7:58 PM Ethan Chen via wrote: > > > > Support basic functions of IOPMP specification v0.9.1 rapid-k model. > > The specification url: > > https://gi

[PATCH v8 8/8] hw/riscv/virt: Add IOPMP support

- Add 'iopmp=on' option to enable IOPMP. It adds an iopmp device virt machine to protect all regions of system memory, and configures RRID of CPU. Signed-off-by: Ethan Chen --- docs/system/riscv/virt.rst | 5 +++ hw/riscv/Kconfig | 1 + hw/riscv/virt.c| 63 +

[PATCH v8 7/8] hw/misc/riscv_iopmp: Add DMA operation with IOPMP support API

The iopmp_dma_rw() function performs memory read/write operations to system memory with support for IOPMP. It sends transaction information to the IOPMP for partial hit detection. Signed-off-by: Ethan Chen --- hw/misc/riscv_iopmp.c | 68 +++ include/hw/mis

[PATCH v8 6/8] hw/misc/riscv_iopmp: Add API to configure RISCV CPU IOPMP support

The iopmp_setup_cpu() function configures the RISCV CPU to support IOPMP and specifies the CPU's RRID. Signed-off-by: Ethan Chen --- hw/misc/riscv_iopmp.c | 6 ++ include/hw/misc/riscv_iopmp.h | 1 + 2 files changed, 7 insertions(+) diff --git a/hw/misc/riscv_iopmp.c b/hw/misc/riscv

[PATCH v8 5/8] hw/misc/riscv_iopmp: Add API to set up IOPMP protection for system memory

To enable system memory transactions through the IOPMP, memory regions must be moved to the IOPMP downstream and then replaced with IOMMUs for IOPMP translation. The iopmp_setup_system_memory() function copies subregions of system memory to create the IOPMP downstream and then replaces the specifi

[PATCH v8 1/8] memory: Introduce memory region fetch operation

Allow memory regions to have different behaviors for read and fetch operations. For example, the RISC-V IOPMP could raise an interrupt when the CPU tries to fetch from a non-executable region. If the fetch operation for a memory region is not implemented, the read operation will still be used for

[PATCH v8 2/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size

If the IOMMU granularity is smaller than the TARGET_PAGE size, there may be multiple entries within the same page. To obtain the correct result, pass the original address to the IOMMU. Similar to the RISC-V PMP solution, the TLB_INVALID_MASK will be set when there are multiple entries in the same

[PATCH v8 4/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

Support basic functions of IOPMP specification v0.9.1 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1 The IOPMP checks whether memory access from a device or CPU is valid. This implementation uses an IOMMU to modify the address space accessed b

[PATCH v8 3/8] target/riscv: Add support for IOPMP

Signed-off-by: Ethan Chen --- target/riscv/cpu_cfg.h| 2 ++ target/riscv/cpu_helper.c | 18 +++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fb7eebde52..2946fec20c 100644 --- a/target/riscv/cpu_cfg.h +++

[PATCH v8 0/8] Support RISC-V IOPMP

This series implements basic functions of IOPMP specification v0.9.1 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1 When IOPMP is enabled, memory access to system memory from devices and the CPU will be checked by the IOPMP. The issue of CPU

Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support

; Thanks, > > Ethan > > > > On Fri, Jun 21, 2024 at 03:54:15PM +1000, Alistair Francis wrote: > > > On Wed, Jun 12, 2024 at 1:25 PM Ethan Chen via > > > wrote: > > > > > > > > If a requestor device is connected to the IOPMP

Re: [PATCH v7 2/2] hw/riscv/virt: Add IOPMP support

, Alistair Francis wrote: > On Wed, Jun 12, 2024 at 1:25 PM Ethan Chen via wrote: > > > > If a requestor device is connected to the IOPMP device, its memory access > > will > > be checked by the IOPMP rule. > > > > - Add 'iopmp=on' option to add an i

Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

On Mon, Jun 17, 2024 at 02:09:34PM +0200, Stefan Weil wrote: > [EXTERNAL MAIL] > > Am 12.06.24 um 05:17 schrieb Ethan Chen via: > > Support basic functions of IOPMP specification v0.9.1 rapid-k model. > > The specification url: > > https://github.com/riscv-non-isa/iop

Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

On Mon, Jun 17, 2024 at 07:28:33PM +0800, LIU Zhiwei wrote: > > On 2024/6/12 11:17, Ethan Chen wrote: > > Support basic functions of IOPMP specification v0.9.1 rapid-k model. > > The specification url: > > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1 > > > > IOPMP check memory

Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

On Thu, Jun 13, 2024 at 05:26:03PM +0800, LIU Zhiwei wrote: > > Hi Ethan, > > On 2024/6/12 11:17, Ethan Chen wrote: > > Support basic functions of IOPMP specification v0.9.1 rapid-k model. > > The specification url: > > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1 > > > > IOPM

Re: [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU

On Wed, Jun 12, 2024 at 04:14:02PM +0800, Jim Shu wrote: > [EXTERNAL MAIL] > > It is the preparation patch for upcoming RISC-V wgChecker device. > > Since RISC-V wgChecker could permit access in RO/WO permission, the > IOMMUMemoryRegion could return different section for read & write > access. Th

Re: [RFC PATCH] memory: Introduce memory region fetch operation

On Wed, Jun 12, 2024 at 01:43:41PM +0100, Peter Maydell wrote: > > On Wed, 12 Jun 2024 at 10:02, Ethan Chen via wrote: > > > > Allow the memory region to have different behaviors for read and fetch > > operations. > > > > For example RISCV IOPMP will rai

[RFC PATCH] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size

If the IOMMU granularity is smaller than TARGET_PAGE size, there may have multiple entries in the same page. Pass the origin address to IOMMU to get correct result Similar to the RISCV PMP solution, TLB_INVALID_MASK will be set when there have multiple entries in the same page to check the IOMMU o

[RFC PATCH] memory: Introduce memory region fetch operation

Allow the memory region to have different behaviors for read and fetch operations. For example RISCV IOPMP will raise interrupt when cpu try to fetch a non-excutable region. If fetch operation of a memory region is not implemented, it still uses the read operation for fetch. Signed-off-by: Ethan

[PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

Support basic functions of IOPMP specification v0.9.1 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1 IOPMP check memory access from device is valid or not. This implementation uses IOMMU to change address space that device access. There are th

[PATCH v7 2/2] hw/riscv/virt: Add IOPMP support

If a requestor device is connected to the IOPMP device, its memory access will be checked by the IOPMP rule. - Add 'iopmp=on' option to add an iopmp device and make the Generic PCI Express Bridge connect to IOPMP. Signed-off-by: Ethan Chen --- docs/system/riscv/virt.rst | 6 hw/riscv/Kc

[PATCH v7 0/2] Support RISC-V IOPMP

Due to changing the referenced specification version, this patch has changed a lot in this version. This series implements basic functions of IOPMP specification v0.9.1 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1 When IOPMP is enabled, mem

Re: [PATCH v6 0/3] Support RISC-V IOPMP

Hi Dainel, Sorry for the delayed response. I've been busy over the past two months. I plan to submit the next version of the patch within two weeks. Thanks, Ethan Chen On Mon, May 27, 2024 at 09:09:49AM -0300, Daniel Henrique Barboza wrote: > Hi Ethan, > > > Did you send v7 already and I someh

Re: [PATCH v6 2/3] Add RISC-V IOPMP support

On Wed, Feb 14, 2024 at 11:34:55AM -0300, Daniel Henrique Barboza wrote: > > > On 2/7/24 06:34, Ethan Chen wrote: > > Support specification Version 1.0.0-draft4 rapid-k model. > > The specification url: > > https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf > > >

[PATCH v6 3/3] hw/riscv/virt: Add IOPMP support

If a source device is connected to the IOPMP device, its memory transaction will be checked by the IOPMP rule. When using RISC-V virt machine option "iopmp=on", the generic PCIe host bridge connects to IOPMP. The PCI devices on the bridge will connect to IOPMP with default source id(SID) from PCI

[PATCH v6 1/3] hw/core: Add config stream

Make other device can use /hw/core/stream.c by select this config. Reviewed-by: Alistair Francis Signed-off-by: Ethan Chen --- hw/Kconfig | 1 + hw/core/Kconfig | 3 +++ hw/core/meson.build | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/Kconfig b/hw/Kconfi

[PATCH v6 0/3] Support RISC-V IOPMP

This series implements IOPMP specification v1.0.0-draft4 rapid-k model and add IOPMP device to RISC-V virt machine. Patch 1 add config STREAM make other device can reuse /hw/core/stream.c, IOPMP implementation will use it. Patch 2 implement IOPMP deivce. Patch 3 add IOPMP device to RISC-V virt mac

[PATCH v6 2/3] Add RISC-V IOPMP support

Support specification Version 1.0.0-draft4 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf The memory transaction from source devices connected to IOPMP will be checked by IOPMP rule. The method of connecting the source devi

Re: [PATCH v4 0/4] Support RISC-V IOPMP

On Mon, Jan 22, 2024 at 04:01:12PM +1000, Alistair Francis wrote: > On Thu, Dec 21, 2023 at 4:38 PM Ethan Chen wrote: > > > > On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote: > > > On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via > > > w

[PATCH v5 3/3] hw/riscv/virt: Add IOPMP support

If a source device is connected to the IOPMP device, its memory transaction will be checked by the IOPMP rule. When using RISC-V virt machine option "iopmp=on", the generic PCIe host bridge connects to IOPMP. The PCI devices on the brigde will connets to IOPMP with default source id(SID) from PCI

[PATCH v5 2/3] Add RISC-V IOPMP support

Support specification Version 1.0.0-draft4 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf The memory transaction from source devices connected to IOPMP will be checked by IOPMP rule. The method of connecting the source devi

[PATCH v5 1/3] hw/core: Add config stream

Make other device can use /hw/core/stream.c by select this config. Reviewed-by: Alistair Francis Signed-off-by: Ethan Chen --- hw/Kconfig | 1 + hw/core/Kconfig | 3 +++ hw/core/meson.build | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/Kconfig b/hw/Kconfi

[PATCH v5 0/3] Support RISC-V IOPMP

This series implements IOPMP specification v1.0.0-draft4 rapid-k model and add IOPMP device to RISC-V virt machine. Patch 1 add config STREAM make other device can reuse /hw/core/stream.c, IOPMP implementation will use it. Patch 2 implement IOPMP deivce. Patch 3 add IOPMP device to RISC-V virt mac

Re: [PATCH v4 0/4] Support RISC-V IOPMP

On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote: > On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote: > > > > This series implements IOPMP specification v1.0.0-draft4 rapid-k model. > > The specification url: > > https://github.com/riscv-n

Re: [PATCH v4 2/4] Add RISC-V IOPMP support

On Mon, Dec 18, 2023 at 02:04:06PM +1000, Alistair Francis wrote: > On Wed, Nov 22, 2023 at 3:35 PM Ethan Chen via wrote: > > > > Support specification Version 1.0.0-draft4 rapid-k model. > > The specification url: > > https://github.com/riscv-n

Re: [PATCH v4 0/4] Support RISC-V IOPMP

On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote: > On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote: > > > > This series implements IOPMP specification v1.0.0-draft4 rapid-k model. > > The specification url: > > https://github.com/riscv-n

Re: [PATCH v4 0/4] Support RISC-V IOPMP

Ping again. On Tue, Dec 05, 2023 at 03:48:07PM +0800, Ethan Chen wrote: > Ping. > https://patchew.org/QEMU/20231122053251.440723-1-etha...@andestech.com/ > > On Wed, Nov 22, 2023 at 01:32:47PM +0800, Ethan Chen wrote: > > This series implements IOPMP specification v1.0.0-draft4 rapid-k model. > >

Re: [PATCH v4 0/4] Support RISC-V IOPMP

Ping. https://patchew.org/QEMU/20231122053251.440723-1-etha...@andestech.com/ On Wed, Nov 22, 2023 at 01:32:47PM +0800, Ethan Chen wrote: > This series implements IOPMP specification v1.0.0-draft4 rapid-k model. > The specification url: > https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv

[PATCH v4 4/4] hw/riscv/virt: Add IOPMP support

If a source device is connected to the IOPMP device, its memory access will be checked by the IOPMP rule. - Add 'iopmp=on' option to add an iopmp device and a dma device which is connected to the iopmp to machine. This option is assumed to be "off" - Add 'iopmp_cascade=on' option to add second i

[PATCH v4 1/4] hw/core: Add config stream

Make other device can use /hw/core/stream.c by select this config. Signed-off-by: Ethan Chen --- hw/Kconfig | 1 + hw/core/Kconfig | 3 +++ hw/core/meson.build | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/Kconfig b/hw/Kconfig index 9ca7b38c31..e4d153dce7

[PATCH v4 3/4] hw/dma: Add Andes ATCDMAC300 support

ATCDMAC300 is a direct memory access controller (DMAC) which transfers data efficiently between devices on the AMBA AXI4 bus. ATCDMAC300 supports up to 8 DMA channels. Each DMA channel provides a set of registers to describe the intended data transfers To support RISC-V IOPMP, a memory access dev

[PATCH v4 2/4] Add RISC-V IOPMP support

Support specification Version 1.0.0-draft4 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf IOPMP check memory access from deivce is valid or not. This implementation uses IOMMU to change address space that device access. The

[PATCH v4 0/4] Support RISC-V IOPMP

This series implements IOPMP specification v1.0.0-draft4 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt platform. This DMA device is connected to the IO

Re: [PATCH v3 1/4] hw/core: Add config stream

On Tue, Nov 21, 2023 at 03:28:13PM +1000, Alistair Francis wrote: > On Tue, Nov 21, 2023 at 3:24 PM Alistair Francis wrote: > > > > On Tue, Nov 14, 2023 at 7:49 PM Ethan Chen via > > wrote: > > > > > > Make other device can use /hw/core/stream.c by select

Re: [PATCH v3 4/4] hw/riscv/virt: Add IOPMP support

On Tue, Nov 21, 2023 at 03:22:18PM +1000, Alistair Francis wrote: > On Tue, Nov 14, 2023 at 7:48 PM Ethan Chen via wrote: > > > > - Add 'iopmp=on' option to enable a iopmp device and a dma device > > connect to the iopmp device > > - Add 'iopmp_ca

Re: [PATCH v3 4/4] hw/riscv/virt: Add IOPMP support

On Tue, Nov 14, 2023 at 02:50:21PM -0300, Daniel Henrique Barboza wrote: > > > On 11/14/23 06:47, Ethan Chen wrote: > > - Add 'iopmp=on' option to enable a iopmp device and a dma device > > connect to the iopmp device > > - Add 'iopmp_cascade=on' option to enable iopmp cascading. > > > > Signe

[PATCH v3 2/4] Add RISC-V IOPMP support

Support specification Version 1.0.0-draft4 rapid-k model. Signed-off-by: Ethan Chen --- hw/misc/Kconfig | 4 + hw/misc/meson.build | 1 + hw/misc/riscv_iopmp.c | 967 ++ include/hw/misc/riscv_iopm

[PATCH v3 3/4] hw/dma: Add Andes ATCDMAC300 support

Signed-off-by: Ethan Chen --- hw/dma/Kconfig | 4 + hw/dma/atcdmac300.c | 566 hw/dma/meson.build | 1 + include/hw/dma/atcdmac300.h | 180 4 files changed, 751 insertions(+) create mode 100644 hw/dma/atcdmac300.

[PATCH v3 0/4] Support RISC-V IOPMP

This series implements IOPMP specification v1.0.0-draft4 rapid-k model. When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt platform. This DMA devce is connected to the IOPMP and has the functionalities required by IOPMP, including: - Support specify source-id (SID) - Support as

[PATCH v3 4/4] hw/riscv/virt: Add IOPMP support

- Add 'iopmp=on' option to enable a iopmp device and a dma device connect to the iopmp device - Add 'iopmp_cascade=on' option to enable iopmp cascading. Signed-off-by: Ethan Chen --- hw/riscv/Kconfig| 2 ++ hw/riscv/virt.c | 72 +++-- include

[PATCH v3 1/4] hw/core: Add config stream

Make other device can use /hw/core/stream.c by select this config. Signed-off-by: Ethan Chen --- hw/core/Kconfig | 3 +++ hw/core/meson.build | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/core/Kconfig b/hw/core/Kconfig index 9397503656..628dc3d883 100644 --- a/hw/core/Kconfig +++

Re: [PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs

On Tue, Nov 07, 2023 at 10:53:40AM +, Peter Maydell wrote: > On Tue, 7 Nov 2023 at 03:02, Ethan Chen wrote: > > > > On Mon, Nov 06, 2023 at 10:34:41AM +, Peter Maydell wrote: > > > What AXI bus signals? You already get address and size in the > > > actual memory transaction, they don't nee

Re: [PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs

On Mon, Nov 06, 2023 at 10:34:41AM +, Peter Maydell wrote: > On Mon, 6 Nov 2023 at 01:57, Ethan Chen wrote: > > > > On Fri, Nov 03, 2023 at 10:34:28AM +, Peter Maydell wrote: > > > On Fri, 3 Nov 2023 at 03:29, Ethan Chen wrote: > > > > > > > > On Thu, Nov 02, 2023 at 01:53:05PM +, Pet

Re: [PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs

On Fri, Nov 03, 2023 at 10:34:28AM +, Peter Maydell wrote: > On Fri, 3 Nov 2023 at 03:29, Ethan Chen wrote: > > > > On Thu, Nov 02, 2023 at 01:53:05PM +, Peter Maydell wrote: > > > On Thu, 2 Nov 2023 at 13:49, Peter Xu wrote: > > > > > > > > On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan

Re: [PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs

On Thu, Nov 02, 2023 at 01:53:05PM +, Peter Maydell wrote: > On Thu, 2 Nov 2023 at 13:49, Peter Xu wrote: > > > > On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan Chen wrote: > > > Signed-off-by: Ethan Chen > > > --- > > > include/exec/memattrs.h | 6 ++ > > > 1 file changed, 6 insertions

Re: [PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs

On Thu, Nov 02, 2023 at 09:49:17AM -0400, Peter Xu wrote: > On Thu, Nov 02, 2023 at 05:40:12PM +0800, Ethan Chen wrote: > > Signed-off-by: Ethan Chen > > --- > > include/exec/memattrs.h | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/include/exec/memattrs.h b/include/exec/me

[PATCH v2 1/4] exec/memattrs: Add iopmp source id, start address, end address to MemTxAttrs

Signed-off-by: Ethan Chen --- include/exec/memattrs.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d04170aa27..fc15e5d7d3 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -64,6 +64,12 @@ typedef struct MemTx

[PATCH v2 2/4] Add RISC-V IOPMP support

Support specification Version 1.0.0-draft4 rapid-k model. Signed-off-by: Ethan Chen --- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/riscv_iopmp.c | 902 ++ include/hw/misc/riscv_iopmp.h | 330 + 4 files

[PATCH v2 0/4] Support RISC-V IOPMP

This series implements IOPMP specification v1.0.0-draft4 rapid-k model. When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt platform. This DMA devce is connected to the IOPMP and has the functionalities required by IOPMP, including: - Support specify source-id (SID) - Support as

[PATCH v2 3/4] hw/dma: Add Andes ATCDMAC300 support

Signed-off-by: Ethan Chen --- hw/dma/Kconfig | 3 + hw/dma/atcdmac300.c | 460 hw/dma/meson.build | 1 + include/hw/dma/atcdmac300.h | 171 ++ 4 files changed, 635 insertions(+) create mode 100644 hw/dma/atcdmac30

[PATCH v2 4/4] hw/riscv/virt: Add IOPMP support

- Add 'iopmp=on' option to enable a iopmp device and a dma device connect to the iopmp device - Add 'iopmp_cascade=on' option to enable iopmp cascading. Signed-off-by: Ethan Chen --- hw/riscv/Kconfig| 2 ++ hw/riscv/virt.c | 68 + include

Re: [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented

On Mon, Oct 30, 2023 at 11:02:30AM -0400, Peter Xu wrote: > On Mon, Oct 30, 2023 at 02:00:54PM +0800, Ethan Chen wrote: > > On Fri, Oct 27, 2023 at 12:13:50PM -0400, Peter Xu wrote: > > > Add cc list. > > > > > > On Fri, Oct 27, 2023 at 12:02:24PM -0400, Peter Xu wrote: > > > > On Fri, Oct 27, 202

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