pci_bus_num(bus);
> +AMDVIAddressSpace *amdvi_dev_as;
> +amdvi_as_key *key;
>
> -iommu_as = s->address_spaces[bus_num];
> +amdvi_dev_as = amdvi_as_lookup(s, bus, devfn);
>
> /* allocate memory during the first run */
> -if (!iommu_as) {
> -iommu_as =
orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_COMP_INT);
> +s->evtlog_tail = evtlog_tail_next;
> +amdvi_writeq(s, AMDVI_MMIO_EVENT_TAIL, s->evtlog_tail);
> +
> +amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_EVENT_INT);
> amdvi_generate_msi_interrupt(s
@@ static void amdvi_set_quad(AMDVIState *s, hwaddr addr,
uint64_t val,
uint64_t romask, uint64_t w1cmask)
{
stq_le_p(&s->mmior[addr], val);
-stq_le_p(&s->romask[addr], romask);
+stq_le_p(&s->romask[addr], romask | w1cmask);
stq_le_p(&s->w1cmask[addr], w1cmask);
}
Thanks,
Ethan
> }
> }
>
> --
> 2.34.1
>
>
amp; romask) | (val & ~romask)) & ~(val & w1cmask));
}
This corrects the type of oldval to match the return type of ldq_le_p().
Thanks,
Ethan
On 5/29/25 9:30 PM, Alejandro Jimenez wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email c
Hi,
On 5/21/25 4:49 PM, Alejandro Jimenez wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Hi Ethan,
>
> On 5/20/25 6:18 AM, Ethan MILON wrote:
>>
E could not be retrieved, it is not valid, or it is not
> setup
> + * for paging. In either case, ensure that if paging was previously
> in
> + * use then invalidate all existing mappings and then switch to use
> the
> + * no_dma memory region.
> + */
If the
.
Signed-off-by: Ethan Chen
---
qemu-options.hx | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 7eb8e02b4b..1f862b19a6 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -4936,13 +4936,13 @@ SRST
with actual performance
allow us to access the struct in other
components by including the header and using TCG_STATE(current_accel()).
Would you be open to this direction, or do you have any alternative
suggestions?
Thanks,
Ethan
On Thu, Jun 05, 2025 at 09:21:55AM +0200, Philippe Mathieu-Daudé wrote:
> Hi Ethan,
>
vCPU switching, though it may negatively impact overall
simulation performance.
Signed-off-by: Ethan Chen
---
accel/tcg/tcg-accel-ops-rr.c | 2 +-
accel/tcg/tcg-accel-ops-rr.h | 2 +-
accel/tcg/tcg-all.c | 35 +++
qemu-options.hx | 9
On Thu, May 22, 2025 at 11:24:28AM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Wed, Mar 12, 2025 at 7:43 PM Ethan Chen via wrote:
> >
> > - Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine
> > to protect all regions of
Hi,
On 5/2/25 4:15 AM, Alejandro Jimenez wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
> common operation re
Hi,
On 4/13/25 10:02 PM, Alejandro Jimenez wrote:
> For the specified address range, walk the page table identifying regions
> as mapped or unmapped and invoke registered notifiers with the
> corresponding event type.
>
> Signed-off-by: Alejandro Jimenez
> ---
> hw/i386/amd_iommu.c | 74 +++
same page, ensuring that the IOMMU is
checked on every access.
Signed-off-by: Ethan Chen
Acked-by: Alistair Francis
---
accel/tcg/cputlb.c | 20
system/physmem.c | 4
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
The entire valid transaction must fit within a single IOPMP entry.
However, during IOMMU translation, the transaction size is not
available. This structure defines the transaction information required
by the IOPMP.
Signed-off-by: Ethan Chen
---
include/hw/misc/riscv_iopmp_txn_info.h | 38
ddr' range checks switch case (Daniel)
Ethan Chen (8):
hw/core: Add config stream
memory: Introduce memory region fetch operation
system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
size
target/riscv: Add support for IOPMP
hw/misc/riscv_iopmp_txn_info: Add struct
for fetch operations.
Signed-off-by: Ethan Chen
Acked-by: Alistair Francis
---
accel/tcg/cputlb.c| 9 +++-
include/exec/memory.h | 27 +++
system/memory.c | 104 ++
system/trace-events | 2 +
4 files changed, 140 insertions(+), 2
- Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine
to protect all regions of system memory.
Signed-off-by: Ethan Chen
---
docs/specs/index.rst | 1 +
docs/specs/riscv-iopmp.rst | 60 ++
docs/system/riscv/virt.rst | 9 +
ess)
* err_msiaddrh: 0x0 (high-part 32-bit address)
* msi_rrid: 0
(Range: 0-65535. Specifies the rrid used by the IOPMP to send the MSI.)
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig |4 +
hw/misc/meson.build |1 +
hw/misc/riscv_iopmp.c | 2
Signed-off-by: Ethan Chen
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 +++---
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
This device determines the target IOPMP device for forwarding information
based on:
* Address: For parallel IOPMP devices
* Stage: For cascading IOPMP devices
Signed-off-by: Ethan Chen
---
hw/misc/meson.build | 1 +
hw/misc/riscv_iopmp_dispatcher.c | 139
Make other device can use /hw/core/stream.c by select this config.
Reviewed-by: Alistair Francis
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw
- Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine
to protect all regions of system memory.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 7
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c
This device determines the target IOPMP device for forwarding information
based on:
* Address: For parallel IOPMP devices
* Stage: For cascading IOPMP devices
Signed-off-by: Ethan Chen
---
hw/misc/meson.build | 1 +
hw/misc/riscv_iopmp_dispatcher.c | 136
The entire valid transaction must fit within a single IOPMP entry.
However, during IOMMU translation, the transaction size is not
available. This structure defines the transaction information required
by the IOPMP.
Signed-off-by: Ethan Chen
---
include/hw/misc/riscv_iopmp_txn_info.h | 38
ess)
* err_msiaddrh: 0x0 (high-part 32-bit address)
* msi_rrid: 0
(Range: 0-65535. Specifies the rrid used by the IOPMP to send the MSI.)
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig |4 +
hw/misc/meson.build |1 +
hw/misc/riscv_iopmp.c | 2
for fetch operations.
Signed-off-by: Ethan Chen
---
accel/tcg/cputlb.c| 9 +++-
include/exec/memory.h | 27 +++
system/memory.c | 104 ++
system/trace-events | 2 +
4 files changed, 140 insertions(+), 2 deletions(-)
diff --git a
emove iopmp_cascade option for virt machine
- Refine 'addr' range checks switch case (Daniel)
Ethan Chen (8):
hw/core: Add config stream
memory: Introduce memory region fetch operation
system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
size
target/riscv: Add su
Signed-off-by: Ethan Chen
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 +++---
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
Make other device can use /hw/core/stream.c by select this config.
Reviewed-by: Alistair Francis
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw
same page, ensuring that the IOMMU is
checked on every access.
Signed-off-by: Ethan Chen
Acked-by: Alistair Francis
---
accel/tcg/cputlb.c | 20
system/physmem.c | 4
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
: Store section pointer in CPUTLBEntryFull
https://patchew.org/QEMU/20240612081416.29704-1-jim@sifive.com/20240612081416.29704-2-jim@sifive.com/
[2] https://github.com/zhanyangch/qemu/tree/iopmp_patch_v9_test
[3] https://github.com/zhanyangch/iopmp-test
Ethan Chen (8):
hw/core: Add config
Signed-off-by: Ethan Chen
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 +++---
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
same page, ensuring that the IOMMU is
checked on every access.
Signed-off-by: Ethan Chen
Acked-by: Alistair Francis
---
accel/tcg/cputlb.c | 20
system/physmem.c | 4
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
ess)
* err_msiaddrh: 0x0 (high-part 32-bit address)
* msi_rrid: 0
(Range: 0-65535. Specifies the rrid used by the IOPMP to send the MSI.)
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig |4 +
hw/misc/meson.build |1 +
hw/misc/riscv_iopmp.c | 2
- Add 'iopmp=on' option to enable IOPMP. It adds iopmp devices virt machine
to protect all regions of system memory.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 7
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c
This device determines the target IOPMP device for forwarding information
based on:
* Address: For parallel IOPMP devices
* Stage: For cascading IOPMP devices
Signed-off-by: Ethan Chen
---
hw/misc/meson.build | 1 +
hw/misc/riscv_iopmp_dispatcher.c | 136
The entire valid transaction must fit within a single IOPMP entry.
However, during IOMMU translation, the transaction size is not
available. This structure defines the transaction information required
by the IOPMP.
Signed-off-by: Ethan Chen
---
include/hw/misc/riscv_iopmp_txn_info.h | 38
for fetch operations.
Signed-off-by: Ethan Chen
---
accel/tcg/cputlb.c| 9 +++-
include/exec/memory.h | 27 +++
system/memory.c | 104 ++
system/trace-events | 2 +
4 files changed, 140 insertions(+), 2 deletions(-)
diff --git a
Make other device can use /hw/core/stream.c by select this config.
Reviewed-by: Alistair Francis
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw
On Tue, Nov 05, 2024 at 03:36:07PM -0300, Daniel Henrique Barboza wrote:
> [EXTERNAL MAIL]
>
> Hi Ethan,
>
>
> Do you plan to send a new version of this work? It seems to me that we're
> a couple of reviews away from getting it merged.
>
Hi Daniel,
Thanks for c
On Mon, Aug 12, 2024 at 10:48:40AM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Fri, Aug 9, 2024 at 8:14 PM Ethan Chen wrote:
> >
> > On Thu, Aug 08, 2024 at 02:01:13PM +1000, Alistair Francis wrote:
> > >
> > > On Mon, Jul 15, 2024
On Mon, Aug 12, 2024 at 10:47:33AM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Fri, Aug 9, 2024 at 8:11 PM Ethan Chen wrote:
> >
> > On Thu, Aug 08, 2024 at 02:23:56PM +1000, Alistair Francis wrote:
> > >
> > > On Mon, Jul 15, 2024
On Thu, Aug 08, 2024 at 02:01:13PM +1000, Alistair Francis wrote:
>
> On Mon, Jul 15, 2024 at 8:15 PM Ethan Chen via wrote:
> >
> > - Add 'iopmp=on' option to enable IOPMP. It adds an iopmp device virt
> > machine
> > to protect all regions of s
On Thu, Aug 08, 2024 at 02:23:56PM +1000, Alistair Francis wrote:
>
> On Mon, Jul 15, 2024 at 8:13 PM Ethan Chen via wrote:
> >
> > To enable system memory transactions through the IOPMP, memory regions must
> > be moved to the IOPMP downstream and then replac
On Thu, Aug 08, 2024 at 01:56:35PM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Mon, Jul 15, 2024 at 7:58 PM Ethan Chen via wrote:
> >
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://gi
On Thu, Aug 08, 2024 at 02:25:04PM +1000, Alistair Francis wrote:
>
> On Mon, Jul 15, 2024 at 8:15 PM Ethan Chen via wrote:
> >
> > The iopmp_setup_cpu() function configures the RISCV CPU to support IOPMP and
> > specifies the CPU's RRID.
> >
> > Signed
On Thu, Aug 08, 2024 at 01:56:35PM +1000, Alistair Francis wrote:
> [EXTERNAL MAIL]
>
> On Mon, Jul 15, 2024 at 7:58 PM Ethan Chen via wrote:
> >
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://gi
- Add 'iopmp=on' option to enable IOPMP. It adds an iopmp device virt machine
to protect all regions of system memory, and configures RRID of CPU.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 5 +++
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c
The iopmp_dma_rw() function performs memory read/write operations to system
memory with support for IOPMP. It sends transaction information to the IOPMP
for partial hit detection.
Signed-off-by: Ethan Chen
---
hw/misc/riscv_iopmp.c | 68 +++
include/hw
The iopmp_setup_cpu() function configures the RISCV CPU to support IOPMP and
specifies the CPU's RRID.
Signed-off-by: Ethan Chen
---
hw/misc/riscv_iopmp.c | 6 ++
include/hw/misc/riscv_iopmp.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/misc/riscv_iopmp.c b/hw
specified memory
regions in system memory with the IOMMU regions of the IOPMP. It also
adds entries to a protection map that records the relationship between
physical address regions and the IOPMP, which is used by the IOPMP DMA
API to send transaction information.
Signed-off-by: Ethan Chen
---
hw/misc
for fetch operations.
Signed-off-by: Ethan Chen
---
accel/tcg/cputlb.c| 9 +++-
include/exec/memory.h | 30
system/memory.c | 104 ++
system/trace-events | 2 +
4 files changed, 143 insertions(+), 2 deletions(-)
diff --git a
same page, ensuring that the IOMMU is
checked on every access.
Signed-off-by: Ethan Chen
---
accel/tcg/cputlb.c | 20
system/physmem.c | 4
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index edb3715017
address space is blocked_ followed by
the lacked permissions.
The operation of a blocked region can trigger an IOPMP interrupt, a bus
error, or it can respond with success and fabricated data, depending on
the value of the IOPMP ERR_CFG register.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig
Signed-off-by: Ethan Chen
---
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 +++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fb7eebde52..2946fec20c 100644
--- a/target/riscv/cpu_cfg.h
scade option for virt machine
- Refine 'addr' range checks switch case (Daniel)
Ethan Chen (8):
memory: Introduce memory region fetch operation
system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
size
target/riscv: Add support for IOPMP
hw/misc/riscv_iopmp: A
On Wed, Jun 26, 2024 at 11:22:46AM +1000, Alistair Francis wrote:
>
> On Mon, Jun 24, 2024 at 11:47 AM Ethan Chen wrote:
> >
> > Hi Alistair,
> >
> > IOPMP can applies all device. In this patch series, PCI devices on the
> > bridge
> > can connec
Hi Alistair,
IOPMP can applies all device. In this patch series, PCI devices on the bridge
can connect to IOPMP by pci_setup_iommu(), but other devices need change their
memory access address space from system memory to IOPMP by themself.
Thanks,
Ethan
On Fri, Jun 21, 2024 at 03:54:15PM +1000
On Mon, Jun 17, 2024 at 02:09:34PM +0200, Stefan Weil wrote:
> [EXTERNAL MAIL]
>
> Am 12.06.24 um 05:17 schrieb Ethan Chen via:
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iop
On Mon, Jun 17, 2024 at 07:28:33PM +0800, LIU Zhiwei wrote:
>
> On 2024/6/12 11:17, Ethan Chen wrote:
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
>
On Thu, Jun 13, 2024 at 05:26:03PM +0800, LIU Zhiwei wrote:
>
> Hi Ethan,
>
> On 2024/6/12 11:17, Ethan Chen wrote:
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/
from the access type when creating iotlb? I think the section
might be wrong in this situation.
Thanks,
Ethan
>
>
On Wed, Jun 12, 2024 at 01:43:41PM +0100, Peter Maydell wrote:
>
> On Wed, 12 Jun 2024 at 10:02, Ethan Chen via wrote:
> >
> > Allow the memory region to have different behaviors for read and fetch
> > operations.
> >
> > For example RISCV IOPMP will rai
on every access.
Signed-off-by: Ethan Chen
---
accel/tcg/cputlb.c | 17 -
system/physmem.c | 4
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 117b516739..9c0db4d9e2 100644
--- a/accel/tcg/cputlb.c
+++ b/accel
: Ethan Chen
---
accel/tcg/cputlb.c| 9 +++-
include/exec/memory.h | 30
system/memory.c | 104 ++
3 files changed, 141 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 117b516739..edb3715017
success with fabricated
data depending on IOPMP ERR_CFG register value.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig |3 +
hw/misc/meson.build |1 +
hw/misc/riscv_iopmp.c | 1002 +
hw/misc/trace-events |4 +
include
If a requestor device is connected to the IOPMP device, its memory access will
be checked by the IOPMP rule.
- Add 'iopmp=on' option to add an iopmp device and make the Generic PCI Express
Bridge connect to IOPMP.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 6
stall support, transaction information which need requestor device
support.
- Remove iopmp_cascade option for virt machine
- Refine 'addr' range checks switch case (Daniel)
Ethan Chen (2):
hw/misc/riscv_iopmp: Add RISC-V IOPMP device
hw/riscv/virt: Add IOPMP support
docs/sy
Hi Dainel,
Sorry for the delayed response. I've been busy over the past two months.
I plan to submit the next version of the patch within two weeks.
Thanks,
Ethan Chen
On Mon, May 27, 2024 at 09:09:49AM -0300, Daniel Henrique Barboza wrote:
> Hi Ethan,
>
>
> Did you send
On Wed, Feb 14, 2024 at 11:34:55AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 2/7/24 06:34, Ethan Chen wrote:
> > Support specification Version 1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/blob/main/ri
ce to machine. When iopmp option is "off"
, this option has no effect.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 12
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c| 110 -
include/hw/riscv/virt.h| 8 ++-
4 file
Make other device can use /hw/core/stream.c by select this config.
Reviewed-by: Alistair Francis
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw
style (Daniel Henrique Barboza)
Thanks,
Ethan Chen
Ethan Chen (3):
hw/core: Add config stream
Add RISC-V IOPMP support
hw/riscv/virt: Add IOPMP support
docs/system/riscv/virt.rst| 12 +
hw/Kconfig|1 +
hw/core/Kconfig
stall_io_as. The operation of stall_io_as does
nothing but return a stall result to source device. Source device
should retry the transaction if it gets a stall result.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig |4 +
hw/misc/meson.build
On Mon, Jan 22, 2024 at 04:01:12PM +1000, Alistair Francis wrote:
> On Thu, Dec 21, 2023 at 4:38 PM Ethan Chen wrote:
> >
> > On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote:
> > > On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via
> > > w
ce to machine. When iopmp option is "off"
, this option has no effect.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 12
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c| 110 -
include/hw/riscv/virt.h| 8 ++-
4 file
stall_io_as. The operation of stall_io_as does
nothing but return a stall result to source device. Source device
should retry the transaction if it gets a stall result.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig |4 +
hw/misc/meson.build
Make other device can use /hw/core/stream.c by select this config.
Reviewed-by: Alistair Francis
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw
)
Support PCI device
Drop IOPMP device create helper function (Alistair Francis)
- Remove ATCDMAC300 (Alistair Francis)
- VIRT: Make PCIe bridge connect to IOPMP
Modify document for IOPMP options
Add IOPMP fdt
Thanks,
Ethan Chen
Ethan Chen (3):
hw/core: Add config
On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote:
> On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote:
> >
> > This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-n
On Mon, Dec 18, 2023 at 02:04:06PM +1000, Alistair Francis wrote:
> On Wed, Nov 22, 2023 at 3:35 PM Ethan Chen via wrote:
> >
> > Support specification Version 1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-n
On Mon, Dec 18, 2023 at 02:18:58PM +1000, Alistair Francis wrote:
> On Wed, Nov 22, 2023 at 3:36 PM Ethan Chen via wrote:
> >
> > This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> > The specification url:
> > https://github.com/riscv-n
Ping again.
On Tue, Dec 05, 2023 at 03:48:07PM +0800, Ethan Chen wrote:
> Ping.
> https://patchew.org/QEMU/20231122053251.440723-1-etha...@andestech.com/
>
> On Wed, Nov 22, 2023 at 01:32:47PM +0800, Ethan Chen wrote:
> > This series implements IOPMP specification v1.0.0-dr
Ping.
https://patchew.org/QEMU/20231122053251.440723-1-etha...@andestech.com/
On Wed, Nov 22, 2023 at 01:32:47PM +0800, Ethan Chen wrote:
> This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
> The specification url:
> https://github.com/riscv-non-isa/iopmp-spec/
=on' option to add second iopmp device which is cascaded by
first iopmp device to machine. When iopmp option is "off", this option has no
effect.
Signed-off-by: Ethan Chen
---
docs/system/riscv/virt.rst | 11 +++
hw/riscv/Kconfig
Make other device can use /hw/core/stream.c by select this config.
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw/Kconfig
index 9ca7b38c31..e4d153dce7
iothread property to make the device run on
iothread.
To send transaction information to IOPMP streamsink, function
transaction_info_push is called before memory access.
Signed-off-by: Ethan Chen
---
hw/dma/Kconfig | 4 +
hw/dma/atcdmac300.c | 566
memory access. IOPMP will do
additional partially hit check with transaction info.
If the source device does not support transaction info. IOPMP will not check
partially hit.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig | 4 +
hw/misc/meson.build
- IOPMP: Refine error message and remove unused variable
- VIRT: Document new options
atcdmac300 is only added when iopmp is enabled
serial setting should not be changed
Ethan Chen (4):
hw/core: Add config stream
Add RISC-V IOPMP support
hw/dma: Add Andes
On Tue, Nov 21, 2023 at 03:28:13PM +1000, Alistair Francis wrote:
> On Tue, Nov 21, 2023 at 3:24 PM Alistair Francis wrote:
> >
> > On Tue, Nov 14, 2023 at 7:49 PM Ethan Chen via
> > wrote:
> > >
> > > Make other device can use /hw/core/stream.c by select
On Tue, Nov 21, 2023 at 03:22:18PM +1000, Alistair Francis wrote:
> On Tue, Nov 14, 2023 at 7:48 PM Ethan Chen via wrote:
> >
> > - Add 'iopmp=on' option to enable a iopmp device and a dma device
> > connect to the iopmp device
> > - Add 'iopmp_ca
On Tue, Nov 14, 2023 at 02:50:21PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 11/14/23 06:47, Ethan Chen wrote:
> > - Add 'iopmp=on' option to enable a iopmp device and a dma device
> > connect to the iopmp device
> > - Add 'iopmp_ca
Support specification Version 1.0.0-draft4 rapid-k model.
Signed-off-by: Ethan Chen
---
hw/misc/Kconfig | 4 +
hw/misc/meson.build | 1 +
hw/misc/riscv_iopmp.c | 967 ++
include/hw/misc
Signed-off-by: Ethan Chen
---
hw/dma/Kconfig | 4 +
hw/dma/atcdmac300.c | 566
hw/dma/meson.build | 1 +
include/hw/dma/atcdmac300.h | 180
4 files changed, 751 insertions(+)
create mode 100644 hw/dma/atcdmac300
: Convert ATCDMAC burst to AXI burst
- ATCDMAC300: Send transaction_info to IOPMP StreamSink
Ethan Chen (4):
hw/core: Add config stream
Add RISC-V IOPMP support
hw/dma: Add Andes ATCDMAC300 support
hw/riscv/virt: Add IOPMP support
hw/core/Kconfig | 3 +
hw/core
- Add 'iopmp=on' option to enable a iopmp device and a dma device
connect to the iopmp device
- Add 'iopmp_cascade=on' option to enable iopmp cascading.
Signed-off-by: Ethan Chen
---
hw/riscv/Kconfig| 2 ++
hw/riscv
Make other device can use /hw/core/stream.c by select this config.
Signed-off-by: Ethan Chen
---
hw/core/Kconfig | 3 +++
hw/core/meson.build | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/core/Kconfig b/hw/core/Kconfig
index 9397503656..628dc3d883 100644
--- a/hw/core/Kconfig
On Tue, Nov 07, 2023 at 10:53:40AM +, Peter Maydell wrote:
> On Tue, 7 Nov 2023 at 03:02, Ethan Chen wrote:
> >
> > On Mon, Nov 06, 2023 at 10:34:41AM +, Peter Maydell wrote:
> > > What AXI bus signals? You already get address and size in the
> > > actu
On Mon, Nov 06, 2023 at 10:34:41AM +, Peter Maydell wrote:
> On Mon, 6 Nov 2023 at 01:57, Ethan Chen wrote:
> >
> > On Fri, Nov 03, 2023 at 10:34:28AM +, Peter Maydell wrote:
> > > On Fri, 3 Nov 2023 at 03:29, Ethan Chen wrote:
> > > >
> > &g
On Fri, Nov 03, 2023 at 10:34:28AM +, Peter Maydell wrote:
> On Fri, 3 Nov 2023 at 03:29, Ethan Chen wrote:
> >
> > On Thu, Nov 02, 2023 at 01:53:05PM +, Peter Maydell wrote:
> > > On Thu, 2 Nov 2023 at 13:49, Peter Xu wrote:
> > > >
> > &g
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