Re: Question about RISC-V brom register a1 set value

Hi Zhiwei, thanks for your reply, I make a mistake, t0 is 0x1000 so both lw a1, 32(t0) or ld a1, 32(t0) just read from the brom offset 32byte. Thanks, Eric Chan 刘志伟 於 2022年10月5日 週三 下午5:47寫道： > I think the a1 from QEMU reset vector is the device tree(fdt_laddr) though > I don&

Question about RISC-V brom register a1 set value

have an opportunity to fix this problem. If it is expected, why they must be done? Thanks, Eric Chan qemu/include/hw/riscv/boot_opensbi.h #define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f qemu/hw/riscv/boot.c void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *