Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/translate.c | 26 +-
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 047d97e2c5..5098a1d
On Sun, May 25, 2025 at 05:02:19PM +0100, Richard Henderson wrote:
> Return a constant 0 from reg_for_read, and a new
> temporary from reg_for_write.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/translate.c | 24 ++-
On Sun, May 25, 2025 at 05:02:18PM +0100, Richard Henderson wrote:
> Now that the extended address instructions are handled separately
> from virtual addresses, we can narrow the emulation to 32-bit.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Richard Henderson
> ---
>
On Sun, May 25, 2025 at 05:02:17PM +0100, Richard Henderson wrote:
> Use TARGET_FMT_lx to match the target_ulong type of vaddr.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/mmu.c | 3 ++-
> 1 file changed, 2 inserti
On Sun, May 25, 2025 at 05:02:16PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for extended addresses.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/translate.c | 24
> 1 file chan
On Sun, May 25, 2025 at 05:02:15PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for EAR.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Richard Henderson
> ---
> target/microblaze/cpu.h | 2 +-
> target/microblaze/translate.c | 2 +-
> 2 files
On Sun, May 25, 2025 at 05:02:14PM +0100, Richard Henderson wrote:
> Use helpers and address_space_ld/st instead of inline
> loads and stores. This allows us to perform operations
> on physical addresses wider than virtual addresses.
>
> Signed-off-by: Richard Henderson
Revie
On Sun, May 25, 2025 at 05:02:11PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for the address to store in EAR.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/helper.c | 64 +
On Sun, May 25, 2025 at 05:02:13PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for the address to store in EAR.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/op_helper.c | 70 +-
On Sun, May 25, 2025 at 05:02:12PM +0100, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/helper.h | 12 ++--
> target/microblaze/helper.c | 7 +++
> 2 files changed, 13 insertions(+), 6 deletio
On Mon, May 19, 2025 at 5:26 PM Peter Maydell
wrote:
> On Tue, 13 May 2025 at 16:39, Philippe Mathieu-Daudé
> wrote:
> >
> > On 13/5/25 16:14, Clément Chigot wrote:
> > > From: Frederic Konrad
> > >
> > > This introduces a first-cpu-index property to the arm-gic, as some SOCs
> > > could have t
element
during invalidation and underflow it's entry->lock counter
Signed-off-by: Aleksandr Partanen
Reviewed-by: Stefano Stabellini
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --
From: "Edgar E. Iglesias"
The following changes since commit a9e0c9c0f14e19d23443ac24c8080b4708d2eab8:
Merge tag 'pull-9p-20250505' of https://github.com/cschoenebeck/qemu into
staging (2025-05-05 11:26:59 -0400)
are available in the Git repository at:
https://gitla
From: "Edgar E. Iglesias"
Today, we don't track write-abiliy in the cache, if a user
requests a readable mapping followed by a writeable mapping
on the same page, the second lookup will incorrectly hit
the readable entry.
Split mapcache_grants by ro and rw access. Grants will no
On Sun, May 04, 2025 at 01:57:04PM -0700, Richard Henderson wrote:
> M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are
> all 32-bit targets. AVR is more complicated, but using
> a 32-bit wrap preserves current behaviour.
>
> Cc: Michael Rolnik
> Cc: Laurent Vivier
>
On Wed, Feb 12, 2025 at 02:01:46PM -0800, Richard Henderson wrote:
> Use out-of-line helpers to implement extended address memory ops.
> With this, we can reduce TARGET_LONG_BITS to the more natural 32
> for this 32-bit cpu.
Series looks good to me:
Reviewed-by: Edgar E. Iglesias
On Wed, Apr 30, 2025 at 09:29:20AM +0200, Philippe Mathieu-Daudé wrote:
> On 30/4/25 08:26, Philippe Mathieu-Daudé wrote:
> > Hi,
> >
> > On 13/2/25 13:37, Philippe Mathieu-Daudé wrote:
> > > +AMD folks
> > >
> > > On 12/2/25 23:01, Richard Henderson wrote:
> > > > Use out-of-line helpers to impl
On Wed, Apr 30, 2025 at 08:26:23AM +0200, Philippe Mathieu-Daudé wrote:
> Hi,
>
> On 13/2/25 13:37, Philippe Mathieu-Daudé wrote:
> > +AMD folks
> >
> > On 12/2/25 23:01, Richard Henderson wrote:
> > > Use out-of-line helpers to implement extended address memory ops.
> > > With this, we can reduc
* we must call gdb_init_cpu after CPU properties have been
>set, which is to say somewhere in realize
>
> The function cpu_exec_realizefn() meets both of these requirements,
> as it is called by the architecture-specific CPU realize function
> early in realize, before an
_coprocessor() in realize, after the call to
> cpu_exec_realizefn().
>
> Move the microblaze gdb_register_coprocessor() use, bringing it
> in line with other targets.
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Peter Maydell
> ---
> target/microblaze/cpu.c |
ove the local variable when we make the
> following change.
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Peter Maydell
> ---
> target/microblaze/cpu.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/targe
On Tue, Mar 18, 2025 at 02:07:58PM +0100, Corvin Köhne wrote:
> From: YannickV
>
> It is assumed, that the programmable logic (PL) is always powered
> during emulation. Therefor the PCFG_POR_B bit in the MCTRL register
> is set.
>
> This commit is necessary for the Beckhoff CX7200 board emulatio
On Thu, Apr 24, 2025 at 10:48:17AM +, Corvin Köhne wrote:
> On Tue, 2025-03-18 at 14:07 +0100, Corvin Köhne wrote:
> > CAUTION: External Email!!
> > From: Corvin Köhne
> >
> > Beckhoff has build a board, called CX7200, based on the Xilinx Zynq A9
> > platform. This commit series adds the Beck
lso been toggled
> to 0 before and the UPDATE_CONTROL is not set, the DONE bit in the status
> register is set. If these bits change the DONE bit is reset. Note that the
> option bits are not taken into consideration.
>
> Signed-off-by: Yannick Voßen
LGTM:
Reviewed-by: Edgar E. Ig
On Tue, Mar 18, 2025 at 02:07:57PM +0100, Corvin Köhne wrote:
> From: YannickV
>
> Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT
> should indicate that the reset is finished successfully.
>
> In order to add a MMIO-Device as part of the PL in the Zynq, the
> reset logic must s
On Tue, Mar 18, 2025 at 02:08:00PM +0100, Corvin Köhne wrote:
> From: YannickV
>
> A dummy DDR controller for ZYNQ has been added. While all registers are
> present,
> not all are functional. Read and write access is validated, and the user mode
> can be set. This provides a basic DDR controller
gister with an offset bigger than 0x40 will be
> ignored, because the memory size is set wrong. This effects the
> MCTRL register and makes it useless. This commit restores the
> correct behaviour.
>
> Signed-off-by: Yannick Voßen
Reviewed-by: Edgar E. Iglesias
> ---
>
On Tue, Mar 18, 2025 at 02:07:56PM +0100, Corvin Köhne wrote:
> From: YannickV
>
> When the FPGA_RST_CTRL register in the SLCR (System Level Control
> Register) is written to, the devcfg (Device Configuration) should
> indicate the finished reset.
>
> Problems occure when Loaders trigger a reset
On Tue, Mar 18, 2025 at 02:07:55PM +0100, Corvin Köhne wrote:
> From: YannickV
>
> During the emulation startup, all registers are reset, which triggers the
> `r_unlock_post_write` function with a value of 0. This led to an
> unintended memory access disable, making the devcfg unusable.
>
> To a
t, the DMA transfer proceeds
> as usual. A successful load is indicated but nothing is actually
> done. Guests relying on FPGA functions are still known to fail.
>
> This feature is required for the integration of the Beckhoff
> CX7200 model.
Thanks, LGTM:
Reviewed-by: Edgar E
From: "Edgar E. Iglesias"
Today, we don't track write-abiliy in the cache, if a user
requests a readable mapping followed by a writeable mapping
on the same page, the second lookup will incorrectly hit
the readable entry.
Split mapcache_grants by ro and rw access. Grants will no
From: "Edgar E. Iglesias"
This fixes an issue with grant mappings when a read-only
mapping is requested followed by a read-write mapping for
the same page. Today, we don't track write-ability and
read-write lookups hit on read-only entries.
This series is an attempt to fix th
andr, thanks for the patch, it looks correct to me.
>
> Reviewed-by: Stefano Stabellini
>
>
> Edgar, would you be able to give it a look as well to make sure?
Looks good to me too, thanks!
Reviewed-by: Edgar E. Iglesias
>
>
> > ---
> > hw/xen/xen-mapca
On Wed, Mar 5, 2025 at 5:22 PM Stefano Stabellini
wrote:
> +Edgar
>
> On Wed, 5 Mar 2025, Philippe Mathieu-Daudé wrote:
> > On 16/6/23 01:52, Stefano Stabellini wrote:
> > > From: Vikram Garhwal
> > >
> > > Add a new machine xenpvh which creates a IOREQ server to
> register/connect
> > > with
>
On Tue, Feb 18, 2025 at 6:02 AM Philippe Mathieu-Daudé
wrote:
> Hi Edgar,
>
> On 4/9/24 18:15, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add support for optionally creating a PCIe/GPEX controller.
> >
> > Signed-off-by: Edgar
.c:18:6: error: no previous prototype for
> ‘xen_mr_is_memory’ [-Werror=missing-prototypes]
>18 | bool xen_mr_is_memory(MemoryRegion *mr)
> | ^~~~
>
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw
ines are:
> none empty machine
> xenpvh Xen PVH ARM machine
>
>
Makes sense to me.
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/arm/Kconfig b
hw/xen/xen-hvm-common.c:428: undefined reference to
> `pci_host_config_read_common'
> /usr/bin/ld: hw/xen/xen-hvm-common.c:438: undefined reference to
> `pci_host_config_write_common'
>
> Fixes: f22e598a72c ("hw/xen: pvh-common: Add support for creating
> PCIe/GPEX&quo
On Tue, 4 Feb 2025 at 08:37, Peter Maydell wrote:
> On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias
> wrote:
> > On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell
> wrote:
> >> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan
> wrote:
> >> > -rx_c
From: "Edgar E. Iglesias"
Olaf reported a slowdown in boot time on x86 HVM guests and Stefano
provided a patch that removes the invalidation of the grants mapcache
since not needed, more details here:
https://lore.kernel.org/all/Z5oIvUINVDfrrVla@zapote/T/
Cheers,
Edgar
Stefano Sta
;t do that. So
remove the function call.
Fixes: 9ecdd4bf08 (xen: mapcache: Add support for grant mappings)
Cc: qemu-sta...@nongnu.org
Reported-by: Olaf Hering
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-mapcache.c | 1 -
1
On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell
wrote:
> Edgar or Alistair -- could one of you review this
> cadence GEM patch, please?
>
>
Sorry for the delay!
> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan
> wrote:
> >
> > From: Andrew Yuan
> >
> > As in the Cadence IP for Gigabit Ethernet MAC
te.rx[0]io
> 81001800-81001ffb (prio 0, i/o): xlnx.xps-ethernetlite
> @1800
> 81001ffc-81001fff (prio 0, i/o): ethlite.rx[1]io
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/xilinx_ethlite.c |
; Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now
> unused. Not a concern, this array will soon disappear.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/xilinx_ethlite.c | 15 +++
> 1 file changed, 7 ins
On Tue, Nov 12, 2024 at 07:10:27PM +0100, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> hw/net/xilinx_ethlite.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/hw/net/xilinx_ethlite.c b/hw/ne
On Tue, Nov 12, 2024 at 07:10:44PM +0100, Philippe Mathieu-Daudé wrote:
> Having all its address range mapped by subregions,
> s->mmio MemoryRegion effectively became a container.
> Rename it as 'container' for clarity.
Reviewed-by: Edgar E. Iglesias
>
> Signed-of
001800-81001ff3 (prio 0, ram): ethlite.rx[1]buf
> 81001ffc-81001fff (prio 0, i/o): ethlite.rx[1]io
>
> Mention the device datasheet in the file header.
Nice!
Reviewed-by: Edgar E. Iglesias
>
> Reported-by: Paolo Bonzini
> Signed-
On Tue, Nov 12, 2024 at 07:10:24PM +0100, Philippe Mathieu-Daudé wrote:
> This is the result of a long discussion with Edgar (started few
> years ago!) and Paolo:
> https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f681...@redhat.com/
> After clarification from Richard on MMIO/RAM acc
On Tue, Nov 12, 2024 at 07:10:42PM +0100, Philippe Mathieu-Daudé wrote:
> Add TX_CTRL to the TX registers MMIO region.
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/xilinx_ethlite.c | 56 +++--
&g
On Tue, Nov 12, 2024 at 07:10:41PM +0100, Philippe Mathieu-Daudé wrote:
> Add TX_GIE to the TX registers MMIO region.
>
> Before TX_GIE1 was accessed as RAM, with no effect.
> Now it is accessed as MMIO, also without any effect.
>
> Signed-off-by: Philippe Mathieu-Daudé
Re
On Tue, Nov 12, 2024 at 07:10:40PM +0100, Philippe Mathieu-Daudé wrote:
> Declare TX registers as MMIO region, split it out
> of the current mixed RAM/MMIO region.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> hw/net/xil
; Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now
> unused. Not a concern, this array will soon disappear.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/xilinx_ethlite.c | 12 ++--
> 1 file changed, 10 insertio
; Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now
> unused. Not a concern, this array will soon disappear.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/xilinx_ethlite.c | 8 ++--
> 1 file changed, 6 insertions(+
; Previous s->regs[R_RX_CTRL0] and s->regs[R_RX_CTRL1] are now
> unused. Not a concern, this array will soon disappear.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/xilinx_ethlite.c | 31 +--
> 1 fi
On Tue, Nov 12, 2024 at 07:10:34PM +0100, Philippe Mathieu-Daudé wrote:
> rxbuf_ptr() points to the beginning of a (RAM) RX buffer
> within the device state.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> hw/net/xilinx_ethlite.c | 9 +
On Tue, Nov 12, 2024 at 07:10:33PM +0100, Philippe Mathieu-Daudé wrote:
> txbuf_ptr() points to the beginning of a (RAM) TX buffer
> within the device state.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> hw/net/xilinx_ethlite.c | 13
On Tue, Nov 12, 2024 at 07:10:32PM +0100, Philippe Mathieu-Daudé wrote:
> For a particular physical address within the EthLite MMIO range,
> addr_to_port_index() returns which port is accessed.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/net/xilinx_ethlite.c | 10 +-
> 1 file ch
pong;
> uint32_t c_rx_pingpong;
> -unsigned int txbuf;
> -unsigned int rxbuf;
> +unsigned int port_index;
May want to add a comment that you're refering to the dual port RAM
index and not some other port...
Either way:
Reviewed-by: Edgar E. Iglesias
>
>
ot memory region: system
> 8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
> 810007e4-810007f3 (prio 0, i/o): ethlite.mdio
> 810007f4-81001fff (prio 0, i/o): xlnx.xps-ethernetlite
> @07f4
>
> Signed-off-by: Phil
On Tue, Nov 12, 2024 at 07:10:29PM +0100, Philippe Mathieu-Daudé wrote:
> The current max RX bufsize is set to 0x800. This is
> invalid, since it contains the MMIO registers region.
> Add the correct definition and use it.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Ed
On Tue, Nov 12, 2024 at 07:10:28PM +0100, Philippe Mathieu-Daudé wrote:
> Use XlnxXpsEthLite typedef, OBJECT_DECLARE_SIMPLE_TYPE macro;
> convert type_init() to DEFINE_TYPES().
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> hw/net/xil
On Tue, Nov 12, 2024 at 07:10:26PM +0100, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> hw/net/xilinx_ethlite.c | 5 +++--
> hw/net/trace-events | 4
> 2 files changed, 7 insertions(+), 2 deletions(-)
&g
On Fri, Nov 08, 2024 at 04:26:20PM +, Ho, Nelson via wrote:
> Hi Edgar,
>
> I am working on bringing up the Wind River Helix hypervisor on the
> xlnx-versal-virt machine, which expects to find MMU-500 SMMU where it lives
> on the Versal SoC. I understand the -virt machine is not intended to
On Tue, Nov 05, 2024 at 11:18:31PM +, Philippe Mathieu-Daudé wrote:
> On 5/11/24 23:01, Philippe Mathieu-Daudé wrote:
> > Hi Edgar,
> >
> > On 5/11/24 23:54, Edgar E. Iglesias wrote:
> > > On Tue, Nov 05, 2024 at 02:04:13PM +0100, Philippe Mathieu-Daudé wro
t; sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
> diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
> index ede7c172748..44ef11ebf89 100644
> --- a/hw/net/xilinx_ethlite.c
> +++ b/hw/net/xilinx_ethlite.c
> @@ -3,6 +3,9 @@
> *
> * Copyri
On Tue, Nov 05, 2024 at 02:04:20PM +0100, Philippe Mathieu-Daudé wrote:
> Pass vCPU endianness as argument so we can load kernels
> with different endianness (different from the qemu-system-binary
> builtin one).
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philipp
(2 bytes)
> • Word (4 bytes)"
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/timer/xilinx_timer.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
>
mer/xilinx_timer.c
> index 28ac95edea1..3e272c8bb39 100644
> --- a/hw/timer/xilinx_timer.c
> +++ b/hw/timer/xilinx_timer.c
> @@ -3,6 +3,9 @@
> *
> * Copyright (c) 2009 Edgar E. Iglesias.
> *
> + * DS573: https://docs.amd.com/v/u/en-US/xps_timer
> + * LogiCORE IP XPS Ti
ion(-)
>
> diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
> index 1762b34564e..71f743a1f14 100644
> --- a/hw/intc/xilinx_intc.c
> +++ b/hw/intc/xilinx_intc.c
> @@ -3,6 +3,9 @@
> *
> * Copyright (c) 2009 Edgar E. Iglesias.
> *
> +
On Tue, Nov 05, 2024 at 02:04:18PM +0100, Philippe Mathieu-Daudé wrote:
> Fix few MemoryRegionOps style before adding new fields
> in the following commits.
Wasn't aware of this style rule :-)
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
On Tue, Nov 05, 2024 at 02:04:17PM +0100, Philippe Mathieu-Daudé wrote:
> Replace DEFINE_MACHINE() by DEFINE_TYPES(), converting the
> class_init() handler.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/microblaze/petalogix_s3a
1a ("microblaze: Allow targeting
> little-endian mb") added little-endian support, forgetting
> to set the CPU endianness to little-endian. Not an issue
> since this property was never used, but we will use it soon,
> so explicit the endianness to get the expected behavior.
On Tue, Nov 05, 2024 at 02:04:16PM +0100, Philippe Mathieu-Daudé wrote:
> The machine datasheet mentions the GPIO device as 'xps_gpio'.
> Rename it accordingly to easily find its documentation.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
g-endian system binary, while their
> CPU is working in little-endian. Unlikely to work as it. Deprecate now
> as broken config so we can remove soon.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> docs/about/deprecated.rst
On Tue, Nov 05, 2024 at 02:04:13PM +0100, Philippe Mathieu-Daudé wrote:
> Rename the 'endian' property as 'little-endian' because the 'ENDI'
> bit is set when the endianness is in little order, and unset in
> big order.
Hi Phil,
Unfortunately, these properties are not only QEMU internal these got
From: "Edgar E. Iglesias"
The following changes since commit f1dd640896ee2b50cb34328f2568aad324702954:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-10-18 10:42:56 +0100)
are available in the Git repository at:
https://gitlab.com/edg
From: "Edgar E. Iglesias"
Avoid use of uninitialized bufioreq_evtchn. It should only
be used if buffered IOREQs are enabled.
Resolves: Coverity CID 1563383
Reported-by: Peter Maydell
Acked-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-hvm-common.c | 7
On Mon, Oct 07, 2024 at 04:42:49PM +0100, Peter Maydell wrote:
> On Thu, 3 Oct 2024 at 19:57, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > Expose handle_bufioreq in xen_register_ioreq().
> > This is to allow machines to
From: "Edgar E. Iglesias"
This has a fix for Coverity CID 1563383 reported by Peter.
Avoid use of uninitialized bufioreq_evtchn. It should only
be used if buffered IOREQs are enabled.
Cheers,
Edgar
Edgar E. Iglesias (1):
hw/xen: Avoid use of uninitialized bufioreq_evtchn
hw/x
From: "Edgar E. Iglesias"
Avoid use of uninitialized bufioreq_evtchn. It should only
be used if buffered IOREQs are enabled.
Resolves: Coverity CID 1563383
Reported-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-hvm-common.c | 7 ---
1 file changed, 4 insert
From: "Edgar E. Iglesias"
Enable PCI support for the ARM Xen PVH machine.
Reviewed-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xen-pvh.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 28af3910ea..
From: "Edgar E. Iglesias"
Add a way to enable/disable buffered IOREQs for PVH machines
and disable them for ARM. ARM does not support buffered
IOREQ's nor the legacy way to map IOREQ info pages.
See the following for more details:
https://xenbits.xen.org/gitweb/?p=xen.git
hem.
Signed-off-by: Dr. David Alan Gilbert
Acked-by: Anthony PERARD
Reviewed-by: Thomas Huth
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-legacy-backend.c | 18 --
hw/xen/xen_devconfig.c | 8
include/hw/xen/xe
From: "Edgar E. Iglesias"
Acked-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-pvh-common.c | 36
1 file changed, 36 insertions(+)
diff --git a/hw/xen/xen-pvh-common.c b/hw/xen/xen-pvh-common.c
index 76a9b2b945..218ac85
From: "Edgar E. Iglesias"
Expose handle_bufioreq in xen_register_ioreq().
This is to allow machines to enable or disable buffered ioreqs.
No functional change since all callers still set it to
HVM_IOREQSRV_BUFIOREQ_ATOMIC.
Reviewed-by: Stefano Stabellini
Signed-off-by: Edgar E
From: "Edgar E. Iglesias"
The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6:
Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging (2024-10-03 10:32:54 +0100)
are available in the Git repository at:
On Thu, Oct 03, 2024 at 06:07:00PM +0100, Peter Maydell wrote:
> On Thu, 3 Oct 2024 at 15:31, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6:
> >
From: "Edgar E. Iglesias"
Add a way to enable/disable buffered IOREQs for PVH machines
and disable them for ARM. ARM does not support buffered
IOREQ's nor the legacy way to map IOREQ info pages.
See the following for more details:
https://xenbits.xen.org/gitweb/?p=xen.git
From: "Edgar E. Iglesias"
Enable PCI support for the ARM Xen PVH machine.
Reviewed-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xen-pvh.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 28af3910ea..
From: "Edgar E. Iglesias"
The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6:
Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging (2024-10-03 10:32:54 +0100)
are available in the Git repository at:
From: "Edgar E. Iglesias"
Expose handle_bufioreq in xen_register_ioreq().
This is to allow machines to enable or disable buffered ioreqs.
No functional change since all callers still set it to
HVM_IOREQSRV_BUFIOREQ_ATOMIC.
Reviewed-by: Stefano Stabellini
Signed-off-by: Edgar E
From: "Edgar E. Iglesias"
Acked-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-pvh-common.c | 36
1 file changed, 36 insertions(+)
diff --git a/hw/xen/xen-pvh-common.c b/hw/xen/xen-pvh-common.c
index 76a9b2b945..218ac85
hem.
Signed-off-by: Dr. David Alan Gilbert
Acked-by: Anthony PERARD
Reviewed-by: Thomas Huth
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-legacy-backend.c | 18 --
hw/xen/xen_devconfig.c | 8
include/hw/xen/xe
On Sun, Sep 22, 2024 at 09:24:33PM +0800, Chao Liu wrote:
> Signed-off-by: Chao Liu
Reviewed-by: Edgar E. Iglesias
> ---
> hw/dma/xlnx-zynq-devcfg.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zyn
Ping!
On Wed, Aug 14, 2024 at 01:15:55PM -0500, Eric Blake wrote:
> On Mon, Aug 12, 2024 at 04:43:23PM GMT, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Avoid a maybe-uninitialized warning in raw_refresh_zoned_limits()
> > by initial
"xen: remove the legacy 'xen_disk' backend")
> >
> > xen_config_dev_console is unused since 2018's
> > 6d7c06c213 ("Remove broken Xen PV domain builder")
> >
> > Remove them.
> >
> > Signed-off-by: Dr. David Alan Gilbert
>
> Acked-by: Anthony PERARD
>
> Thanks,
Reviewed-by: Edgar E. Iglesias
Cheers,
Edgar
From: "Edgar E. Iglesias"
Acked-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-pvh-common.c | 36
1 file changed, 36 insertions(+)
diff --git a/hw/xen/xen-pvh-common.c b/hw/xen/xen-pvh-common.c
index 76a9b2b945..218ac85
From: "Edgar E. Iglesias"
Add a way to enable/disable buffered IOREQs for PVH machines
and disable them for ARM. ARM does not support buffered
IOREQ's nor the legacy way to map IOREQ info pages.
See the following for more details:
https://xenbits.xen.org/gitweb/?p=xen.git
From: "Edgar E. Iglesias"
Enable PCI support for the ARM Xen PVH machine.
Reviewed-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xen-pvh.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 28af3910ea..
From: "Edgar E. Iglesias"
Enable PCI on the ARM PVH machine. First we add a way to control the use
of buffered IOREQ's since those are not supported on Xen/ARM.
Finally we enable the PCI support.
I've published some instructions on how to try this including the work in
prog
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