On Tue, Jul 15, 2025 at 08:19:04AM +0200, Cédric Le Goater wrote:
> commit ad8e0e8a0088 removed the "==" underlining the file title
> which broke documentation rendering. Add it back.
>
> Fixes: ad8e0e8a0088 ("docs: add support for gb200-bmc")
> Cc: Ed T
On Thu, Jul 03, 2025 at 05:18:56PM +0200, Cédric Le Goater wrote:
> On 7/3/25 16:42, Ed Tanous wrote:
> > This patch series adds support for gb200-bmc, a baseboard management
> > controller
> > module based on an Aspeed 2600 SOC.
> >
> > v2:
> > - Rebase on
On Thu, Jul 03, 2025 at 05:17:31PM +0200, Cédric Le Goater wrote:
> On 7/3/25 16:42, Ed Tanous wrote:
> > To support the newly added gb200 machine, add appropriate tests.
> >
> > Signed-off-by: Ed Tanous
> > ---
> > tests/functional/aspeed.py
This patch updates the docs for support of gb200-bmc.
Signed-off-by: Ed Tanous
---
docs/system/arm/aspeed.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 43d27d83cb..bec0a1dfa8 100644
--- a/docs/system/arm
To support the newly added gb200 machine, add appropriate tests.
Signed-off-by: Ed Tanous
---
tests/functional/aspeed.py| 9 +--
tests/functional/meson.build | 2 ++
.../test_arm_aspeed_gb200nvl_bmc.py | 26 +++
3 files
This patch series adds support for gb200-bmc, a baseboard management controller
module based on an Aspeed 2600 SOC.
v2:
- Rebase on master
- Drop duplicated patch for enabling PCA954X
- Updated commit message with source information
- Added functional tests and example openbmc image
Ed Tanous (4
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous
---
hw/arm/aspeed.c | 2 ++
include/hw/arm/aspeed.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index d0b333646e..3ef7f6c5b2 100644
--- a
Signed-off-by: Ed Tanous
---
hw/arm/aspeed.c| 79 ++
hw/arm/aspeed_eeprom.c | 21 +++
hw/arm/aspeed_eeprom.h | 3 ++
3 files changed, 103 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 3ef7f6c5b2..98144ced86 100644
--- a/hw
On Wed, Jul 02, 2025 at 11:38:53PM +0200, Cédric Le Goater wrote:
> On 7/1/25 22:34, Ed Tanous wrote:
> > GB200nvl72 is a system for for accelerated compute. This is a model for
> > the BMC target within the system.
>
> Could you please add a comment saying it is based on D
GB200nvl72 is a system for for accelerated compute. This is a model for
the BMC target within the system.
Signed-off-by: Ed Tanous
---
hw/arm/aspeed.c| 79 ++
hw/arm/aspeed_eeprom.c | 21 +++
hw/arm/aspeed_eeprom.h | 3 ++
3 files
This patch updates the docs for support of gb200-bmc.
Signed-off-by: Ed Tanous
---
docs/system/arm/aspeed.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 43d27d83cb..bec0a1dfa8 100644
--- a/docs/system/arm
This patch series adds support for gb200-bmc, a baseboard management controller
module based on an Aspeed 2600 SOC.
Ed Tanous (4):
hw/arm: Add PCA9554 to ARM target
hw/arm/aspeed: Add second SPI chip to Aspeed model
docs: add support for gb200-bmc
hw/arm/aspeed: Add GB200 BMC target
From: Ed Tanous
There are arm targets that are connected to this io expander,
specifically some varieties of Aspeed 2600 BMCs. Add it to Kconfig to
allow use.
Signed-off-by: Ed Tanous
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous
---
hw/arm/aspeed.c | 2 ++
include/hw/arm/aspeed.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index d0b333646e..3ef7f6c5b2 100644
--- a
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