[PATCH] hw/riscv: boot: Support 64bit fdt address.

modified Signed-off-by: Dylan Jhong --- hw/riscv/boot.c | 12 +++- include/hw/riscv/boot.h | 4 ++-- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 519fa455a1..852aa92bbe 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c

Re: [PATCH] hw/char/serial: Support serial_mm_init() with wakeup event.

On Wed, Mar 23, 2022 at 05:37:10PM +0800, Peter Maydell wrote: > On Wed, 23 Mar 2022 at 09:20, Dylan Jhong wrote: > > > > Although the "wakeup" parameter is declared in SerialState, > > but there is no function actually setting it up. > > Support &q

[PATCH] hw/char/serial: Support serial_mm_init() with wakeup event.

Although the "wakeup" parameter is declared in SerialState, but there is no function actually setting it up. Support "wakeup" as parameter in serial_mm_init(). We also add a new parameter "wakeup_reason" to let users specify their own wakeup event id. Signed-of

[PATCH V5] target/riscv: Align the data type of reset vector address

Use target_ulong to instead of uint64_t on reset vector address to adapt on both 32/64 machine. Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

[PATCH V4] target/riscv: Align the data type of reset vector address

Use target_ulong to instead of uint64_t on reset vector address to adapt on both 32/64 machine. Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu.h | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target

Re: [PATCH V3] target/riscv: Align the data type of reset vector address

On Fri, Mar 26, 2021 at 04:19:09AM +0800, Alistair Francis wrote: > On Thu, Mar 25, 2021 at 5:43 AM Dylan Jhong wrote: > > > > Signed-off-by: Dylan Jhong > > Signed-off-by: Ruinland ChuanTzu Tsai > > --- > > target/riscv/cpu.c | 6 +- > > target/ris

[PATCH V3] target/riscv: Align the data type of reset vector address

Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b..8a5f18bcb0 100644 --- a/target/riscv/cpu.c

Re: [PATCH V2] target/riscv: Align the data type of reset vector address

machine. I'll send patch v3 to fix this issue. Sorry for my mistake. Regards, Dylan On Thu, Mar 25, 2021 at 01:52:13PM +0800, Dylan Dai-Rong Jhong(鍾岱融) wrote: > Signed-off-by: Dylan Jhong > Signed-off-by: Ruinland ChuanTzu Tsai > --- > target/riscv/cpu.c | 2 +- > target/

[PATCH V2] target/riscv: Align the data type of reset vector address

Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b..4ac901245a 100644 --- a/target/riscv/cpu.c +++ b

Re: [PATCH] target/riscv: Align the data type of reset vector address

On Wed, Mar 24, 2021 at 10:59:55PM +0800, Alistair Francis wrote: > On Tue, Mar 23, 2021 at 5:15 AM Dylan Jhong wrote: > > > > Although the AE350 has not been upstream (preparing for v2), > > the reset vector of the AE350 is known to be at the 2G position, > > so

[PATCH] target/riscv: Align the data type of reset vector address

Although the AE350 has not been upstream (preparing for v2), the reset vector of the AE350 is known to be at the 2G position, so this patch is corrected in advance. Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1

Re: [PATCH 3/3] Andes AE350 RISC-V Machine

On Wed, Mar 10, 2021 at 02:15:25PM +0800, Bin Meng wrote: > On Wed, Mar 10, 2021 at 11:36 AM Dylan Jhong wrote: > > > > This provides a RISC-V Board based on Andes's AE350 specification. > > The following machine is implemented: > > > > - 'andes_ae35

Re: [PATCH 1/3] Andes RISC-V PLIC

On Wed, Mar 10, 2021 at 02:05:51PM +0800, Bin Meng wrote: > On Wed, Mar 10, 2021 at 11:34 AM Dylan Jhong wrote: > > > > Andes PLIC (Platform-Level Interrupt Controller) device provides an > > interrupt controller functionality based on Andes's PLIC specification. > &g

[PATCH 3/3] Andes AE350 RISC-V Machine

This provides a RISC-V Board based on Andes's AE350 specification. The following machine is implemented: - 'andes_ae350'; PLIC, PLICSW, PLMT, 16550a UART, VirtIO MMIO, device-tree Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- default-configs/devices/risc

[PATCH 2/3] Andes RISC-V PLMT

Andes PLMT (Platform-Level Machine Timer) device provides an timer functionality and issues timer interrupts. The Andes PLMT is implemented based on Andes's PLMT specification. Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- hw/timer/Kconfig | 3 + hw/

[PATCH 1/3] Andes RISC-V PLIC

t and interrupt preemption, we leave them as future items for now. Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- hw/intc/Kconfig | 3 + hw/intc/andes_plic.c | 505 +++ hw/intc/meson.build | 1 + include/hw

[PATCH 0/3] Support Andes AE350 Platform

4. UART(16550a), 5. Virtio MMIO, 6. Device tree Dylan Jhong (3): Andes RISC-V PLIC Andes RISC-V PLMT Andes AE350 RISC-V Machine default-configs/devices/riscv32-softmmu.mak | 1 + default-configs/devices/riscv64-softmmu.mak | 1 + hw/intc/Kconfig |