Reviewed-by: Dongxue Zhang
On Thu, Nov 9, 2023 at 10:22 AM Leo Hou wrote:
>
> From: Leo Hou
>
> cpu_by_arch_id() uses hartid-base as the index to obtain the corresponding
> CPUState structure variable.
> qemu_get_cpu() uses cpu_index as the index to obtain the corresp
>On Thu, Dec 29, 2022 at 12:34 AM ~elta wrote:
>>
>> From: Dongxue Zhang
>>
>> Should be cpu->cfg.elen in range [8, 64].
>>
>> Signed-off-by: Dongxue Zhang
>
>When sending a new version can you please add any previous reviewed tags.
>
>Alist
CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'.
Signed-off-by: Dongxue Zhang
---
target-mips/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 89c01f7..17817c3 100644
--- a/target-mips/cpu.h
+++
CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'.
Signed-off-by: Dongxue Zhang
---
target-mips/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 89c01f7..17817c3 100644
--- a/target-mips/cpu.h
+++
Compare the real msb and lsb, when lsb <= msb, tranlate the code. When
lsb > msb, just fall through and don't raise RI exception.
Signed-off-by: Dongxue Zhang
---
target-mips/translate.c | 43 ---
1 file changed, 24 insertions(+), 19 deletio
Ok, I got you. I will re-build a new patch for all the bitops.
2014-07-29 22:08 GMT+08:00 Aurelien Jarno :
> On Tue, Jul 29, 2014 at 08:41:08PM +0800, Elta wrote:
> > I think, debug mode shouldn't crash the qemu with an unpredictable
> > operation,
> > so i want to fix it. And you say there shou
Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved
in the same TB of the store instruction.
Signed-off-by: Dongxue Zhang
---
target-mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips
Save code with sw and raise synci. The saved code should be raise.
If the code raised, log 'test passed'.
If the code not raised, log 'test failed, the copied instruction not run'.
Other cases, log 'unhandled'.
The test should log 'test passed'.
Signed-of
Free t0 and t1 in opcode OPC_DINSV.
Signed-off-by: Dongxue Zhang
---
target-mips/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d7b8c4d..c381366 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
Use 'if' to make sure the real msb greater than the lsb. As the compiler may
not do this.
Signed-off-by: Dongxue Zhang
---
target-mips/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c381366..e2cce31 10
Make target-openrisc running OK by add typename in openrisc_cpu_class_by_name().
Signed-off-by: Dongxue Zhang
---
target-openrisc/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index fd90d37..d38c28b 100644
--- a/target
Hello everybody, i want to use mips target with smp support. When use
command without smp, then the log stopped at "kernel panic", when -smp 2
added, it stoppted at "NR_IRQS:256".
I use the git qemu at 576156ffed72ab4feb0b752979db86ff8759a2a1
qemu configed with "./configure --target-list=mips64el
Thanks for your review, now I know this problem but don't have gcc can
compile repl_ph instruction. I will build a gcc and resend this patch later.
2012/12/12 Andreas Färber
> Am 11.12.2012 16:13, schrieb Markus Armbruster:
> > Please-separate-words-with-spaces-in-your-subject-line-thank-you-:)
, and check_dsp. If arch is
microMIPS32DSP, then a bug case. So I changed gen_HILO function for furture add
other arch with dsp.
MFHI MTHI MFLO MTLO of mipsdsp have been tested, they worked fun.
Signed-off-by: Dongxue Zhang
---
target-mips/translate.c |
The immediate value is 9bits, should sign-extend to 16bits. The return value to
register should sign-extend to target_long, as Richard says, removing an
unnecessary cast works fun.
Signed-off-by: Dongxue Zhang
---
target-mips/translate.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion
Fix my email address, last time it's wrong.
Signed-off-by: Dongxue Zhang
---
target-mips/dsp_helper.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 14daf91..536032b 100644
--- a/target-mips/dsp_helper.c
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