introduced.
Additionally, writes to the SMI_STS register are enabled for the
corresponding two bits using a write mask to make future work easier.
Signed-off-by: Dominic Prinz
---
Changes from v2 to v3 (this):
- Updated compat properties to reflect new minor release (9.1)
Changes from v1 to
Second ping
https://patchew.org/QEMU/1e4d59a49e7f2e02cf522e799a7bf5f3fa3fba1f.1722414006.git@dprinz.de/
https://lore.kernel.org/qemu-devel/1e4d59a49e7f2e02cf522e799a7bf5f3fa3fba1f.1722414006.git@dprinz.de/
On Wed Aug 21, 2024 at 3:00 PM CEST, Dominic Prinz wrote:
> Ping
>
&
Ping
https://patchew.org/QEMU/1e4d59a49e7f2e02cf522e799a7bf5f3fa3fba1f.1722414006.git@dprinz.de/
https://lore.kernel.org/qemu-devel/1e4d59a49e7f2e02cf522e799a7bf5f3fa3fba1f.1722414006.git@dprinz.de/
On Wed Jul 31, 2024 at 10:28 AM CEST, Dominic Prinz wrote:
> This patch implements
introduced.
Additionally, writes to the SMI_STS register are enabled for the
corresponding two bits.
Signed-off-by: Dominic Prinz
---
Changes since previous version:
- Ensured backwards compatablity by introducing two compat properties
- Introduced write mask for SMI_STS register to make future wor
Ping for my patch from last Friday.
https://patchew.org/QEMU/20240719102053.316744-1-...@dprinz.de/
https://lore.kernel.org/qemu-devel/20240719102053.316744-1-...@dprinz.de/
On 19.07.24 12:20, Dominic Prinz wrote:
This patch implements the periodic and the swsmi ICH9 chipset timer. They are
This patch implements the periodic and the swsmi ICH9 chipset timer. They are
especially useful when prototyping UEFI firmware (e.g. with EDK2's OVMF)
with QEMU.
This includes that writes to the SMI_STS register are enabled for the
corresponding two bits.
Signed-off-by: Dominic Prinz
--
