[Qemu-devel] Arm CMP instruction not setting CPSR values as expected

2018-11-15 Thread Darrell Leinwand
=600d10ad R04=0008 R05=0080 R06=2f2f2eff R07=00087f90 R08=01010101 R09= R10=0002 R11=0020 R12=fffdf910 R13=00087f90 R14=0001b4b1 R15=0001c90c PSR=0033 T NS svc32 Darrell Leinwand | Engineering Performance Software: Seeing Things Differently. O: 623-337-8060 C: 480-309

Re: [Qemu-devel] Bad icount read when running qemu-system-ppc64 and mfspr atbu guest instruction

2018-04-11 Thread Darrell Leinwand
? Thanks for the help. Darrell On 4/11/18, 4:39 PM, "Richard Henderson" wrote: On 04/12/2018 04:18 AM, Darrell Leinwand wrote: > Hi, > > When I enable icount using an e5500 core I get an exit with “Bad icount > read” when the guest software execut

[Qemu-devel] Bad icount read when running qemu-system-ppc64 and mfspr atbu guest instruction

2018-04-11 Thread Darrell Leinwand
Hi, When I enable icount using an e5500 core I get an exit with “Bad icount read” when the guest software executes a load atbu command. It looks like in qemu/accel/tcg/cpu_exec.c:166 sets can_do_io false when using icount. cpu->can_do_io = !use_icount; ret = tcg_qemu_tb_exec(env, tb_ptr