Hello virtio folks,
I noticed a mismatch between the way the specification defines
device-specific virtqueue indexes and the way device and driver
implementers have interpreted the specification. As a practical example,
consider the traditional memory balloon device [1]. The first two queues
(inde
Hi Shimi,
On Sun, Aug 26, 2018 at 2:50 PM Gersner wrote:
>
> Hi Daniel,
> Thanks for taking a look. Comments are inline.
>
> Gersner.
>
> On Sun, Jul 15, 2018 at 9:21 AM Daniel Verkamp wrote:
>>
>> On Fri, Jun 22, 2018 at 4:22 AM, Shimi Gersner wrote:
>&g
On Fri, Jun 22, 2018 at 4:22 AM, Shimi Gersner wrote:
> PCI/e configuration currently does not meets specifications.
>
> Patch includes various configuration changes to support specifications
> - BAR2 to return zero when read and CMD.IOSE is not set.
> - Expose NVME configuration through IO space
As in the SATA and AHCI specifications, a FIS is 5 Dwords of 4 bytes
each, which comes to 20 bytes (decimal), not 0x20.
Signed-off-by: Daniel Verkamp
---
hw/ide/ahci.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index a883a92
(Sorry for the slow response, was on vacation)
On Thu, Sep 1, 2011 at 7:58 AM, Alexander Graf wrote:
> On 08/30/2011 05:07 AM, Daniel Verkamp wrote:
>>
>> On Sun, Aug 28, 2011 at 11:48 AM, Alexander Graf wrote:
>>>
>>> On 27.08.2011, at 04:12, Daniel Verkamp
On Sun, Aug 28, 2011 at 11:48 AM, Alexander Graf wrote:
>
> On 27.08.2011, at 04:12, Daniel Verkamp wrote:
>
>> Implement an I/O space index-data register pair as defined by the AHCI
>> spec, including the corresponding SATA PCI capability and BAR.
>>
>> This al
.
Signed-off-by: Daniel Verkamp
---
hw/ide/ahci.c | 42 +-
hw/ide/ahci.h |9 -
hw/ide/ich.c | 27 ++-
hw/pci_regs.h |1 +
4 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
