Re: [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree

2022-11-30 Thread Conor.Dooley
On 30/11/2022 08:13, Atish Kumar Patra wrote: > In Linux DT binding or dt schema repo ? I am a bit confused now as we > talked about both above :). I asked about a dt-binding and not a schema change, so the former ;)

Re: [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree

2022-11-29 Thread Conor.Dooley
+CC Rob, which I probably should've done earlier, so context all preserved On 29/11/2022 09:42, Conor Dooley wrote: > On 29/11/2022 09:27, Atish Kumar Patra wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the >> content is safe >> >> On Mon, Nov 28, 2022 at 11:32

Re: [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree

2022-11-29 Thread Conor.Dooley
On 29/11/2022 09:27, Atish Kumar Patra wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Mon, Nov 28, 2022 at 11:32 PM wrote: >> >> On 29/11/2022 07:08, Andrew Jones wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unles

Re: [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree

2022-11-28 Thread Conor.Dooley
On 29/11/2022 07:08, Andrew Jones wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Mon, Nov 28, 2022 at 09:10:03PM +, conor.doo...@microchip.com wrote: >> On 28/11/2022 20:41, Atish Kumar Patra wrote: >>> EXTERNAL EMAIL: Do not click

Re: [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree

2022-11-28 Thread Conor.Dooley
On 28/11/2022 20:41, Atish Kumar Patra wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Mon, Nov 28, 2022 at 12:38 PM wrote: >> >> On 28/11/2022 20:16, Atish Kumar Patra wrote: >>> On Thu, Nov 24, 2022 at 5:17 AM Conor Dooley >>> wrot

Re: [PATCH v14 4/5] hw/riscv: virt: Add PMU DT node to the device tree

2022-11-28 Thread Conor.Dooley
On 28/11/2022 20:16, Atish Kumar Patra wrote: > On Thu, Nov 24, 2022 at 5:17 AM Conor Dooley > wrote: >> >> On Wed, Aug 24, 2022 at 03:17:00PM -0700, Atish Patra wrote: >>> Qemu virt machine can support few cache events and cycle/instret counters. >>> It also supports counter overflow for these e

Re: [PATCH] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals

2022-08-16 Thread Conor.Dooley
On 16/08/2022 01:40, Philippe Mathieu-Daudé wrote: > [You don't often get email from f4...@amsat.org. Learn why this is important > at https://aka.ms/LearnAboutSenderIdentification ] > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi Conor, >

Re: [PATCH] hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals

2022-08-14 Thread Conor.Dooley
On 14/08/2022 23:08, Alistair Francis wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Sat, Aug 13, 2022 at 11:51 PM Conor Dooley wrote: >> QEMU support for PolarFire SoC seems to be fairly out of date at this >> point. Running with a r

Re: [PATCH v2 3/4] hw/riscv: virt: fix syscon subnode paths

2022-08-08 Thread Conor.Dooley
On 09/08/2022 00:10, Rob Herring wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Mon, Aug 8, 2022 at 4:10 PM wrote: >> >> On 08/08/2022 22:28, Jessica Clarke wrote: >>> Moreover, what is the point of regmap in this >>> case? Its existe

Re: [PATCH v2 3/4] hw/riscv: virt: fix syscon subnode paths

2022-08-08 Thread Conor.Dooley
On 08/08/2022 22:28, Jessica Clarke wrote: > On 8 Aug 2022, at 22:06, Conor Dooley wrote: >> >> From: Conor Dooley >> >> The subnodes of the syscon have been added to the incorrect paths. >> Rather than add them as subnodes, they were originally added to "/foo" >> and a later patch moved them to

Re: [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings

2022-08-08 Thread Conor.Dooley
On 08/08/2022 21:51, Alistair Francis wrote: > On Tue, Aug 9, 2022 at 2:14 AM wrote: >> I guess this patch can then be safely ignored :) >> Glad to have cleared this up as I was rather confused by what I saw. > > Great! Do you mind resending the series then with this patch dropped? > It just make

Re: [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings

2022-08-08 Thread Conor.Dooley
On 08/08/2022 16:03, Tsukasa OI wrote: > I agree with Alistair. **I** removed 'S' and 'U' from the ISA string > and it should be working in the latest development branch (I tested). Yeah, I saw what you as I looked at the commit log while trying to understand why there were invalid strings appear

Re: [PATCH 1/5] target/riscv: Ignore the S and U letters when formatting ISA strings

2022-08-08 Thread Conor.Dooley
On 07/08/2022 23:53, Alistair Francis wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Sat, Aug 6, 2022 at 2:08 AM Conor Dooley wrote: >> >> From: Palmer Dabbelt >> >> The ISA strings we're providing from QEMU aren't actually legal RIS