From 5de17d5aacb9cf21de4c9736b227b0498c607709 Mon Sep 17 00:00:00 2001
From: CHRIS HOWARD
Date: Thu, 12 May 2022 11:35:17 +0200
Subject: [PATCH] Fix aarch64 debug register names.
Signed-off-by: CHRIS HOWARD
---
target/arm/helper.c | 16
1 file changed, 12 insertions(+), 4
On 8. May 2022, at 14:08, Peter Maydell wrote:
>
> On Sat, 7 May 2022 at 14:44, Chris Howard wrote:
>>
>> Hi, I’m writing a simple debugger in assembly code for the Raspberry Pi 3B
>> (in aarch64).
>>
>> I’m using QEMU 7.0.0. Everything is running in
On 8. May 2022, at 14:18, Peter Maydell wrote:
> On Sat, 7 May 2022 at 15:18, Chris Howard wrote:
>> PS. In plain gdb (ie. no nice user interface) a large number (but not all)
>> of the system registers gets displayed after each step. It would be nice if
>> these were s
On 7. May 2022, at 15:42, Chris Howard wrote:
>
> Hi, I’m writing a simple debugger in assembly code for the Raspberry Pi 3B
> (in aarch64).
>
> I’m using QEMU 7.0.0. Everything is running in EL1. (I have MDE and KDE set
> in MDSCR_EL1).
>
> I’m coming across U
Hi, I’m writing a simple debugger in assembly code for the Raspberry Pi 3B (in
aarch64).
I’m using QEMU 7.0.0. Everything is running in EL1. (I have MDE and KDE set in
MDSCR_EL1).
I’m coming across Unexpected Behaviour when playing with single-stepping:
It appears that single-stepping is enabl
and the exception won’t be triggered.**
(if I *attempt* to set the MASK to 0b1, but it actually gets set to
0b0, then I get the behaviour quoted below).
> On 24. Apr 2022, at 13:40, Chris Howard wrote:
>
> Hi, I’m new to qemu (and even bug-reporting) so apologies in advance…
>
Hi, I’m new to qemu (and even bug-reporting) so apologies in advance…
The MASK field in DBGWCRx_EL1 is **5** bits wide [28:24].
In target/arm/kvm64.c I found the line:
wp.wcr = deposit32(wp.wcr, 24, 4, bits); // ie **4** bits
instead of **5**
If it’s not copying (or calculating
