esponder to get the data
object of SPDM/secured SPDM.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
hw/mem/cxl_type3.c | 31 +++-
hw/pci/Kconfig | 4 +
hw/pci/SpdmEmuCommand.c | 319
hw/pci/meson.build
This patch series provides an implementation of the the Data Object Exchange
(DOE) for Component Measurement and Authentication (CMA) of the Security
Protocol and Data Model (SPDM).
This patch is based on
[1] [PATCH v1 openspdm on QEMU CXL/PCIe Device 0/2] Testing PCIe DOE in QEMU
CXL/PCIe Devi
From: hchkuo
The requester should be used as a PCIe app to access the SPDM object in
the PCEe device.
Signed-off-by: Chris Browy
---
Include/IndustryStandard/PciDoeBinding.h| 27 +++
SpdmEmu/SpdmEmuCommon/SpdmEmu.c | 85 ++
SpdmEmu/SpdmEmuCommon
From: hchkuo
Modified gcc to CC in GNUMakefile, so that we can specify the gcc version
Signed-off-by: Chris Browy
---
GNUmakefile.Flags | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/GNUmakefile.Flags b/GNUmakefile.Flags
index 3586284..33baceb 100644
--- a
This patch series provides an implementation of the the Data Object Exchange
(DOE) for Component Measurement and Authentication (CMA) of the Security
Protocol and Data Model (SPDM).
This patch is based on
[1] Openspdm: https://github.com/jyao1/openspdm.git
Openspdm is an emulator composed of an
ned-off-by: Chris Browy
---
hw/mem/cxl_type3.c | 147
include/hw/cxl/cxl_compliance.h | 293
include/hw/cxl/cxl_component.h | 3 +
include/hw/cxl/cxl_device.h | 3 +
include/hw/cxl/cxl_pci.h| 1 +
5 files ch
From: hchkuo
Pre-built CDAT table for testing, contains one CDAT header and six
CDAT entries: DSMAS, DSLBIS, DSMSCIS, DSIS, DSEMTS, and SSLBIS
respectively.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
tests/data/cdat/cdat.dat | Bin 0 -> 148 bytes
1 file changed, 0 insertions(+)
n will be early returned if not within the related DOE range.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
MAINTAINERS | 7 +
hw/pci/meson.build| 1 +
hw/pci/pcie_doe.c | 374 ++
include/hw/pci/pcie.h | 1 +
From: hchkuo
Macros for the vender ID of PCI-SIG mentioned in "PCIe Data Object
Exchange ECN, March 12, 2020" and the size of PCIe Data Object
Exchange.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
include/hw/pci/pci_ids.h | 3 +++
include/hw/pci/pcie_regs.h | 4 +++
y of CDAT is added to hw/mem/cxl_type3.c with capability
offset 0x190. The config read/write to this capability range can be
generated in the OS to request the CDAT data.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
hw/cxl/cxl-cdat.c | 139 ++
h
From: hchkuo
Linux standard header for the registers of PCI Data Object Exchange
(DOE). This header might be generated via script. The DOE feature
should be added in the future Linux release so this patch can be
removed then.
Signed-off-by: hchkuo
Signed-off-by: Chris Browy
---
include
This patch implements the PCIe Data Object Exchange (DOE) for PCIe 4.0/5.0
and later and CXL 2.0 "type-3" memory devices supporting the following
protocols:
1: PCIe DOE Discovery protocol
2: CXL DOE Compliance Mode protocol
3: CXL DOE CDAT protocol
Implementation is based on QEMU version which
From: hchkuo
Pre-built CDAT table for testing, contains one CDAT header and six
CDAT entries: DSMAS, DSLBIS, DSMSCIS, DSIS, DSEMTS, and SSLBIS
respectively.
Signed-off-by: Chris Browy
---
tests/data/cdat/cdat.dat | Bin 0 -> 148 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
cre
y of CDAT is added to hw/mem/cxl_type3.c with capability
offset 0x190. The config read/write to this capability range can be
generated in the OS to request the CDAT data.
Signed-off-by: Chris Browy
---
hw/cxl/cxl-cdat.c | 228 +
hw/cxl/meson.
ost of the compliance
response is limited to returning corresponding length.
A DOE capability of CXL Compliance is added to hw/mem/cxl_type3.c with
capability offset 0x160. The config read/write to this capability range
can be generated in the OS to request the Compliance info.
Signed-off-by: Chris Brow
n will be early returned if not within the related DOE range.
Signed-off-by: Chris Browy
---
MAINTAINERS | 7 +
hw/pci/meson.build| 1 +
hw/pci/pcie_doe.c | 374 ++
include/hw/pci/pcie.h | 1 +
include/hw/pci/p
From: hchkuo
Macros for the vender ID of PCI-SIG and the size of PCIe Data Object
Exchange.
Signed-off-by: Chris Browy
---
include/hw/pci/pci_ids.h | 2 ++
include/hw/pci/pcie_regs.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
From: hchkuo
Linux standard header for the registers of PCI Data Object Exchange
(DOE). This header might be generated via script. The DOE feature
should be added in the future Linux release so this patch can be
removed then.
Signed-off-by: Chris Browy
---
include/standard-headers/linux
This patch implements the PCIe Data Object Exchange (DOE) for PCIe 4.0/5.0
and later and CXL 2.0 "type-3" memory devices supporting the following
protocols:
1: PCIe DOE Discovery protocol
2: CXL DOE Compliance Mode protocol
3: CXL DOE CDAT protocol
Implementation is based on QEMU version which
From: hchkuo
Signed-off-by: hchkuo
---
include/hw/pci/pci_ids.h | 2 ++
include/hw/pci/pcie_regs.h| 3 +++
include/standard-headers/linux/pci_regs.h | 3 ++-
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/
From: hchkuo
Signed-off-by: hchkuo
---
hw/cxl/cxl-cdat.c | 220 +
hw/cxl/meson.build | 1 +
hw/mem/cxl_type3.c | 200 +++
include/hw/cxl/cxl_cdat.h | 149
include/hw/cxl/cxl_
DOE
+M: Huai-Cheng Kuo
+M: Chris Browy
+S: Supported
+F: include/hw/pci/pcie_doe.h
+F: hw/pci/pcie_doe.c
+
ACPI/SMBIOS
M: Michael S. Tsirkin
M: Igor Mammedov
diff --git a/hw/pci/meson.build b/hw/pci/meson.build
index 5c4bbac..115e502 100644
--- a/hw/pci/meson.build
+++ b/hw/pci/meson.build
Version 4 patch series for PCIe DOE for PCIe and CXL 2.0 completes
all planned functionality.
Based on QEMU version:
https://gitlab.com/bwidawsk/qemu/-/tree/cxl-2.0v4
Summary of changes:
1: PCIe DOE support for Discovery
- Fix the alignment error in DOE config write
- Fix the interr
---
hw/cxl/cxl-component-utils.c | 93
hw/mem/cxl_type3.c | 184
include/hw/cxl/cxl_cdat.h | 127 +
include/hw/cxl/cxl_compl.h | 252 +
include/hw/cxl/cxl_component.h | 74 ++
inc
-configs/pci.mak
+PCIE DOE
+M: Huai-Cheng Kuo
+M: Chris Browy
+S: Supported
+F: include/hw/pci/pcie_doe.h
+F: hw/pci/pcie_doe.c
+
ACPI/SMBIOS
M: Michael S. Tsirkin
M: Igor Mammedov
@@ -1764,7 +1752,6 @@ F: hw/ssi/xilinx_*
SD (Secure Card)
M: Philippe Mathieu-Daudé
-M: Bin Meng
L
es/resources/Coherent%20Device%20Attribute%20Table_1.02.pdf
---
Chris Browy (2):
Basic PCIe DOE support
CXL DOE support for CDAT and Compliance Mode
MAINTAINERS | 49 +--
hw/cxl/cxl-component-utils.c | 93 +
hw/mem/cxl_type3.c
> On Mar 4, 2021, at 2:21 PM, Jonathan Cameron
> wrote:
>
> On Tue, 9 Feb 2021 15:35:49 -0500
> Chris Browy wrote:
>
> Hi Chris,
>
> One more thing hit whilst debugging linux side of this.
>
>> +static void pcie_doe_irq_assert(DOECap *doe_cap)
>>
> On Feb 18, 2021, at 2:15 PM, Jonathan Cameron
> wrote:
>
> On Fri, 12 Feb 2021 17:26:50 -0500
> Chris Browy wrote:
>
>>> On Feb 12, 2021, at 12:23 PM, Jonathan Cameron
>>> wrote:
>>>
>>> On Tue, 9 Feb 2021 15:36:03 -0500
>>&g
> On Feb 18, 2021, at 2:11 PM, Jonathan Cameron
> wrote:
>
> On Fri, 12 Feb 2021 16:58:21 -0500
> Chris Browy wrote:
>
>>> On Feb 12, 2021, at 11:24 AM, Jonathan Cameron
>>> wrote:
>>>
>>> On Tue, 9 Feb 2021 15:35:49 -0500
>&g
> On Feb 12, 2021, at 12:23 PM, Jonathan Cameron
> wrote:
>
> On Tue, 9 Feb 2021 15:36:03 -0500
> Chris Browy wrote:
>
> Split this into two patches for v3. CDAT in one, compliance mode in the
> other.
>
Compliance mode is an optional feature. We’ll split i
> On Feb 12, 2021, at 11:24 AM, Jonathan Cameron
> wrote:
>
> On Tue, 9 Feb 2021 15:35:49 -0500
> Chris Browy wrote:
>
> Run ./scripts/checkpatch.pl over the patches and fix all the warnings before
> posting. It will save time by clearing out most of the minor fo
ption rom to ct3d so
UEFI could
access CDAT through a EFI_ADAPTER_INFORMATION_PROTOCOL (CDAT type) entry.
>
> Thanks.
> Ben
>
> On 21-02-09 15:36:03, Chris Browy wrote:
>> ---
>> hw/cxl/cxl-component-utils.c | 132 +++
>> hw/mem/cxl_type
it compared to
other
areas ;)
Review comments will be folded into next patch.
> On Feb 9, 2021, at 4:42 PM, Ben Widawsky wrote:
>
> Have you/Jonathan come to consensus about which implementation is going
> forward?
> I'd rather not have to review two :D
>
> On 21-0
create mode 100644 include/hw/pci/pcie_doe.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 981dc92..4fb865e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1655,6 +1655,13 @@ F: docs/pci*
F: docs/specs/*pci*
F: default-configs/pci.mak
+PCIE DOE
+M: Huai-Cheng Kuo
+M: Chris Browy
+S: Supported
+F
---
hw/cxl/cxl-component-utils.c | 132 +++
hw/mem/cxl_type3.c | 172
include/hw/cxl/cxl_cdat.h | 120 +
include/hw/cxl/cxl_compl.h | 289 +
include/hw/cxl/cxl_component.h | 126
Attribute Table CDAT 1.02
https://uefi.org/sites/default/files/resources/Coherent%20Device%20Attribute%20Table_1.02.pdf
---
Chris Browy (2):
Basic PCIe DOE support
Basic CXL DOE for CDAT and Compliance Mode
MAINTAINERS | 7 +
hw/cxl/cxl-component-utils.c
> On Feb 5, 2021, at 1:49 PM, Jonathan Cameron
> wrote:
>
> On Fri, 5 Feb 2021 09:19:36 -0800
> Ben Widawsky wrote:
>
>> On 21-02-05 16:09:54, Jonathan Cameron wrote:
>>> On Wed, 3 Feb 2021 23:53:53 -0500
>>> Chris Browy wrote:
>>>
be a --in-replies-to issue. I’ve restored that here in this email reply.
Best Regards,
Chris
On 2/3/21, 12:19 PM, "Jonathan Cameron" wrote:
On Tue, 2 Feb 2021 15:43:28 -0500
Chris Browy wrote:
Hi Chris,
Whilst I appreciate that this is very much an RFC and so
PCIe Data Object Exchange (DOE) protocol for PCIe and CXL is available
https://gitlab.com/avery-qemu/cxl2.0-v3-doe/
based on Ben Widawsky's CXL QEMU cxl2.0-v3 gitlab branch
https://lore.kernel.org/qemu-devel/20210202005948.241655-1-ben.widaw...@intel.com
which is located at
https://gitlab.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 981dc92e25..4fb865e0b3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1655,6 +1655,13 @@ F: docs/pci*
F: docs/specs/*pci*
F: default-configs/pci.mak
+PCIE DOE
+M: Huai-Cheng Kuo
+M: Chris Browy
+S: Supported
+F: include/hw/pci/pcie_doe.h
+F: hw
PCIe Data Object Exchange (DOE) protocol for PCIe and CXL is available
https://gitlab.com/avery-qemu/cxl2.0-v3-doe/
based on Ben Widawsky's CXL QEMU cxl2.0-v3 gitlab branch
https://lore.kernel.org/qemu-devel/20210202005948.241655-1-ben.widaw...@intel.com
which is located at
https://gitlab.com
at are the userspace system APIs for targeting CXL HDM address domain?
Usually you can mmap a SPA if you know how to look it up.
Best Regards,
Chris Browy
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