Sapphire Rapids missing from "Preferred CPU models for Intel x86 hosts" ?

s Is this intentional, or an oversight? Thanks, Chris

[PATCH v2] tests/qtest: Fix npcm7xx_timer-test.c flaky test

npcm7xx_timer-test occasionally fails due to the state of the timers from the previous test iteration. Advancing the clock step after the reset resolves this issue. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1897 Signed-off-by: Chris Rauer --- tests/qtest/npcm7xx_timer-test.c | 1

Re: [PATCH] tests/qtest: Fix npcm7xx_timer-test.c flaky test

Ack. will send out v2. On Wed, Sep 27, 2023 at 9:44 PM Thomas Huth wrote: > On 28/09/2023 05.45, Chris Rauer wrote: > > Could you please add a proper patch description how this is fixing the > issue? > > Thanks, >Thomas > > > > Fixes: https://gitlab.co

[PATCH] tests/qtest: Fix npcm7xx_timer-test.c flaky test

Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1897 Signed-off-by: Chris Rauer --- tests/qtest/npcm7xx_timer-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/npcm7xx_timer-test.c b/tests/qtest/npcm7xx_timer-test.c index 43711049ca..58f58c2f71 100644 --- a/tests/qtest

Re: [PATCH] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero

No. This patch does not address that issue and is not related. I was able to reproduce it about 2/1000 iterations with and without this patch. I will look into that issue separately. -Chris On Fri, Sep 22, 2023 at 11:24 AM Hao Wu wrote: > Is this related to this error? > &

[PATCH] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero

The counter register is only 24-bits and counts down. If the timer is running but the qtimer to reset it hasn't fired off yet, there is a chance the regster read can return an invalid result. Signed-off-by: Chris Rauer --- hw/timer/npcm7xx_timer.c | 3 +++ 1 file changed, 3 insertions(+)

[PATCH v3 4/6] qtest: bail from irq_intercept_in if name is specified

Named interception of in-GPIOs is not supported yet. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell --- softmmu/qtest.c | 8 1 file changed, 8 insertions(+) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 0f1d478bda..66757ba261 100644 --- a/softmmu/qtest.c +++ b

[PATCH v3 3/6] qtest: implement named interception of out-GPIO

Adds qtest_irq_intercept_out_named method, which utilizes a new optional name parameter to the irq_intercept_out qtest command. Signed-off-by: Chris Laplante --- softmmu/qtest.c| 18 ++ tests/qtest/libqtest.c | 6 ++ tests/qtest/libqtest.h | 11 +++ 3 files

[PATCH v3 5/6] qtest: irq_intercept_[out/in]: return FAIL if no intercepts are installed

This is much better than just silently failing with OK. Signed-off-by: Chris Laplante --- softmmu/qtest.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 66757ba261..35b643a274 100644 --- a/softmmu/qtest.c +++ b/softmmu

[PATCH v3 2/6] qtest: factor out qtest_install_gpio_out_intercept

Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell --- softmmu/qtest.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index f8d764b719..1b86489162 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -365,6 +365,15

[PATCH v3 0/6] Add nRF51 DETECT signal with test

le named out-GPIOs, not just one (Peter) Chris Laplante (6): hw/gpio/nrf51: implement DETECT signal qtest: factor out qtest_install_gpio_out_intercept qtest: implement named interception of out-GPIO qtest: bail from irq_intercept_in if name is specified qtest: irq_intercept_[out/in]: retu

[PATCH v3 6/6] qtest: microbit-test: add tests for nRF51 DETECT

Exercise the DETECT mechanism of the GPIO peripheral. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell --- tests/qtest/microbit-test.c | 42 + 1 file changed, 42 insertions(+) diff --git a/tests/qtest/microbit-test.c b/tests/qtest/microbit-test.c

[PATCH v3 1/6] hw/gpio/nrf51: implement DETECT signal

see a reason to model these. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell --- hw/gpio/nrf51_gpio.c | 14 +- include/hw/gpio/nrf51_gpio.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c index b47fd

Re: [PATCH 0/6] Add nRF51 DETECT signal with test

led the delay for the external xtal, but just wondering if its worth the extra code. Thanks, Chris

Re: [PATCH v2 3/6] qtest: implement named interception of out-GPIO

hould we bother factoring out qtest_install_gpio_out_intercept still? It is only used in one place now, as before. Thanks, Chris

[PATCH v2 5/6] qtest: irq_intercept_[out/in]: return FAIL if no intercepts are installed

This is much better than just silently failing with OK. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell --- softmmu/qtest.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 1719bbddc3..c9751f527f 100644 --- a

[PATCH v2 4/6] qtest: bail from irq_intercept_in if name is specified

Named interception of in-GPIOs is not supported yet. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell --- softmmu/qtest.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 7fd8546ed2..1719bbddc3 100644 --- a/softmmu

[PATCH v2 1/6] hw/gpio/nrf51: implement DETECT signal

see a reason to model these. Signed-off-by: Chris Laplante --- hw/gpio/nrf51_gpio.c | 14 +- include/hw/gpio/nrf51_gpio.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c index b47fddf4ed..08396c69a4 100644 ---

[PATCH v2 6/6] qtest: microbit-test: add tests for nRF51 DETECT

Exercise the DETECT mechanism of the GPIO peripheral. Signed-off-by: Chris Laplante Reviewed-by: Peter Maydell --- tests/qtest/microbit-test.c | 42 + 1 file changed, 42 insertions(+) diff --git a/tests/qtest/microbit-test.c b/tests/qtest/microbit-test.c

[PATCH v2 0/6] Add nRF51 DETECT signal with test

= v2: factor out qtest_install_gpio_out_intercept before usage (Peter) renamed qtest_install_gpio_out_intercepts => qtest_install_gpio_out_intercept don't pass DETECT to soc level (Peter) change qtest to use DETECT at GPIO level (Peter) Chris Laplante (6): hw/gpio/nrf51: imp

[PATCH v2 2/6] qtest: factor out qtest_install_gpio_out_intercept

Signed-off-by: Chris Laplante --- softmmu/qtest.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index f8d764b719..1c92e5a6a3 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -365,6 +365,15 @@ void qtest_set_command_cb

[PATCH v2 3/6] qtest: implement named interception of out-GPIO

Adds qtest_irq_intercept_out_named method, which utilizes a new optional name parameter to the irq_intercept_out qtest command. Signed-off-by: Chris Laplante --- softmmu/qtest.c| 24 tests/qtest/libqtest.c | 6 ++ tests/qtest/libqtest.h | 11 +++ 3

Re: [PATCH 0/6] Add nRF51 DETECT signal with test

first. I'm just going to send the POWER/DETECT bits first. There is quite a lot to emulate in CLOCK, POWER, and MPU, and I'd like to do a good job on it. Thanks. Chris

Re: [PATCH 5/6] qtest: irq_intercept_[out/in]: return FAIL if no intercepts are installed

I just did a 'make check' and got: Ok: 737 Expected Fail: 0 Fail: 0 Unexpected Pass:0 Skipped:71 Timeout:0 Thanks, Chris

Re: [PATCH 0/6] Add nRF51 DETECT signal with test

reasonable naming-wise? 2. I also have some implementations for pieces of CLOCK, namely the HFCLKSTART/HFCLKSTOP events and HFCLKSTARTED event. Should I include that in this patch series, or would you prefer it in a separate series? It is unrelated to DETECT and POWER. Thanks, Chris

Thoughts on implementing SEGGER RTT

de a TCP/IP endpoint that a real RTT Viewer could connect to (https://www.segger.com/products/debug-probes/j-link/tools/rtt-viewer/). I'm not sure how feasible this is, though. If anyone has any thoughts or guidance I'd appreciate it. Thanks, Chris

[PATCH 2/6] qtest: implement named interception of out-GPIO

Adds qtest_irq_intercept_out_named method, which utilizes a new optional name parameter to the irq_intercept_out qtest command. Signed-off-by: Chris Laplante --- softmmu/qtest.c| 39 ++- tests/qtest/libqtest.c | 6 ++ tests/qtest/libqtest.h | 11

[PATCH 5/6] qtest: irq_intercept_[out/in]: return FAIL if no intercepts are installed

This is much better than just silently failing with OK. Signed-off-by: Chris Laplante --- softmmu/qtest.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 051bbf4177..e888acb319 100644 --- a/softmmu/qtest.c +++ b/softmmu

[PATCH 6/6] qtest: microbit-test: add tests for nRF51 DETECT

Exercise the DETECT mechanism of the GPIO peripheral. Signed-off-by: Chris Laplante --- tests/qtest/microbit-test.c | 42 + 1 file changed, 42 insertions(+) diff --git a/tests/qtest/microbit-test.c b/tests/qtest/microbit-test.c index 6022a92b6a..3c85adba37

[PATCH 4/6] qtest: factor out qtest_install_gpio_out_intercepts

Simplify the code a bit. Signed-off-by: Chris Laplante --- softmmu/qtest.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 74482ce3cd..051bbf4177 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -365,6

[PATCH 3/6] qtest: bail from irq_intercept_in if name is specified

Named interception of in-GPIOs is not supported yet. Signed-off-by: Chris Laplante --- softmmu/qtest.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 7c3dea5760..74482ce3cd 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c

[PATCH 0/6] Add nRF51 DETECT signal with test

;FAIL' responses when interception fails. Otherwise, it is frustrating to troubleshoot why calls to qtest_irq_intercept_out and friends appears to do nothing. Chris Laplante (6): hw/gpio/nrf51: implement DETECT signal qtest: implement named interception of out-GPIO qtest: bail from irq_inter

[PATCH 1/6] hw/gpio/nrf51: implement DETECT signal

see a reason to model these. Signed-off-by: Chris Laplante --- hw/arm/nrf51_soc.c | 1 + hw/gpio/nrf51_gpio.c | 14 +- include/hw/gpio/nrf51_gpio.h | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c

Re: Addition of qtest_irq_intercept_out_named, or modify qtest_irq_interrupt_out?

esolve_path, but (as I understand it) a named IRQ is not an object, it's a property. So I either need to find a flavor of object_resolve_path that can also handle properties, or I need to add a parameter to qtest_irq_intercept_out for specifying the name. Does that sound right? Thanks, Chris

Re: Emulation of 'System OFF' mode in ARM nRF51 SoCs

IO peripheral to support the DETECT mechanism, and so far it seems to work. I have also locally implemented a version of qtest_irq_intercept_out which supports named GPIO out interrupts, and I have a qtest that confirms that basic functionality of DETECT is working. Hoping to have patches to send in the next couple weeks. Thanks, Chris

Addition of qtest_irq_intercept_out_named, or modify qtest_irq_interrupt_out?

named), vs add the functionality to qtest_irq_intercept_out in the form of an optional additional parameter? Thanks, Chris

Re: Emulation of 'System OFF' mode in ARM nRF51 SoCs

ement in nrf51 directly, or will I need to do it in machine context? I guess what I'm asking is, if the CPU is off, can it still wake itself up? Thanks, Chris

Re: Emulation of 'System OFF' mode in ARM nRF51 SoCs

use the qtest API to test your code, > see some tests in tests/qtest/ using: > - qtest_set_irq_in() > - qtest_qom_set_bool() for GPIO Thanks for the tips - I am working on implementing this now! Chris

Emulation of 'System OFF' mode in ARM nRF51 SoCs

be good enough for my use. I don't really care about masking out other interrupt sources, for example. Thanks, Chris

[PATCH] hw/ssi: Fix Linux driver init issue with xilinx_spi

Register section: https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf Signed-off-by: Chris Rauer --- hw/ssi/xilinx_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 552927622f

Resizable BAR in Kernel 6.1

Hi, I was wondering if Resizable BAR support is planned to come to QEMU soon as it does now have a sysfs interface (commit 041bc24d867a2a577a06534d6d25e500b24a01ef) meaning that a protocol could be implemented for virtualizing it to the VM. I am wondering if this is a feature being developed or p

[PATCH v4 2/3] hw: misc: edu: rename local vars in edu_check_range

This serves to make the local variables a bit less ambiguous. The latter two arguments are named to match DMA_START, and DMA_SIZE. Signed-off-by: Chris Friedt --- hw/misc/edu.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/misc/edu.c b/hw/misc/edu.c

[PATCH v4 1/3] hw: misc: edu: fix 2 off-by-one errors

opposite end, in the case that size1 was 4096, within() would fail because of the non-inclusive check 'end1 < end2', which should have been 'end1 <= end2'. The error message would previously say EDU: DMA range 0x4-0x40fff out of bounds (0x4-0x40fff)!

[PATCH v4 3/3] hw: misc: edu: use qemu_log_mask instead of hw_error

Log a guest error instead of a hardware error when the guest tries to DMA to / from an invalid address. Signed-off-by: Chris Friedt --- hw/misc/edu.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/misc/edu.c b/hw/misc/edu.c index 52afbd792a..a18f803815 100644

Re: [v2] hw: misc: edu: fix 2 off-by-one errors

> On Oct 17, 2022, at 1:22 PM, Alex Bennée wrote: > > > > > Peter Maydell writes: > >>> On Mon, 17 Oct 2022 at 14:50, Alexander Bulekov wrote: >>> >>> On 221015 1710, Chris Friedt wrote: >>>> From: Christopher Friedt >&

[PATCH v3 2/2] hw: misc: edu: rename local vars in edu_check_range

This serves to make the local variables a bit less ambiguous. The latter two arguments are named to match DMA_START, and DMA_SIZE. Signed-off-by: Chris Friedt --- hw/misc/edu.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/misc/edu.c b/hw/misc/edu.c

[PATCH v3 1/2] hw: misc: edu: fix 2 off-by-one errors

//gitlab.com/qemu-project/qemu/-/issues/1254 Signed-off-by: Chris Friedt --- hw/misc/edu.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/misc/edu.c b/hw/misc/edu.c index e935c418d4..b3de8d206a 100644 --- a/hw/misc/edu.c +++ b/hw/misc/edu.c @@ -103,1

[v2] hw: misc: edu: fix 2 off-by-one errors

From: Christopher Friedt In the case that size1 was zero, because of the explicit 'end1 > addr' check, the range check would fail and the error message would read as shown below. The correct comparison is 'end1 >= addr' (or 'addr <= end1'). EDU: DMA range 0x4-0x3 out of bounds (0x4-0

[PATCH] hw: misc: edu: fix 2 off-by-one errors

(0x4-0x40fff)! Note: the original change (and error message) was when parameters were uint32_t. Signed-off-by: Chris Friedt Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1254 --- hw/misc/edu.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/misc/e

Re: driver type raw-xz supports discard=unmap?

On Mon, Jul 25, 2022, at 9:53 AM, Daniel P. Berrangé wrote: > On Mon, Jul 25, 2022 at 08:51:42AM -0400, Chris Murphy wrote: >> Huh, interesting. I have no idea then. I just happened to notice it in the >> (libvirt) XML config that's used by oz. >> https://kojipkgs.f

Re: driver type raw-xz supports discard=unmap?

On Mon, Jul 25, 2022, at 5:13 AM, Daniel P. Berrangé wrote: > On Fri, Jul 22, 2022 at 04:03:52PM -0400, Chris Murphy wrote: >> Is this valid? >> >> ` >> >> >> ` >> `/> >> ` >> >> I know type="raw" works fine,

driver type raw-xz supports discard=unmap?

Is this valid? ` ` `/> ` I know type="raw" works fine, I'm wondering if there'd be any problem with type "raw-xz" combined with discards? Thanks, Chris Murphy

[PATCH] Fix aarch64 debug register names.

From 5de17d5aacb9cf21de4c9736b227b0498c607709 Mon Sep 17 00:00:00 2001 From: CHRIS HOWARD Date: Thu, 12 May 2022 11:35:17 +0200 Subject: [PATCH] Fix aarch64 debug register names. Signed-off-by: CHRIS HOWARD --- target/arm/helper.c | 16 1 file changed, 12 insertions(+), 4

Re: Possible bug in Aarch64 single-stepping

On 8. May 2022, at 14:08, Peter Maydell wrote: > > On Sat, 7 May 2022 at 14:44, Chris Howard wrote: >> >> Hi, I’m writing a simple debugger in assembly code for the Raspberry Pi 3B >> (in aarch64). >> >> I’m using QEMU 7.0.0. Everything is running in

Re: Possible bug in Aarch64 single-stepping [PATCH]

On 8. May 2022, at 14:18, Peter Maydell wrote: > On Sat, 7 May 2022 at 15:18, Chris Howard wrote: >> PS. In plain gdb (ie. no nice user interface) a large number (but not all) >> of the system registers gets displayed after each step. It would be nice if >> these were s

Re: Possible bug in Aarch64 single-stepping

On 7. May 2022, at 15:42, Chris Howard wrote: > > Hi, I’m writing a simple debugger in assembly code for the Raspberry Pi 3B > (in aarch64). > > I’m using QEMU 7.0.0. Everything is running in EL1. (I have MDE and KDE set > in MDSCR_EL1). > > I’m coming across U

Possible bug in Aarch64 single-stepping

single-stepping to occur (and that it gets cleared whenever an exception is taken and needs to be reset if one wants to single-step again). Have I misunderstood / misconfigured something, or is this a bug? Attached is a minimal(ish) example: Regards, chris

Re: Possible bug when setting aarch64 watchpoints

and the exception won’t be triggered.** (if I *attempt* to set the MASK to 0b1, but it actually gets set to 0b0, then I get the behaviour quoted below). > On 24. Apr 2022, at 13:40, Chris Howard wrote: > > Hi, I’m new to qemu (and even bug-reporting) so apologies in advance… >

Possible bug when setting aarch64 watchpoints

rtunately, changing the 4 to a 5 and recompiling had no effect :-( I may well have misunderstood something. :-/ —Chris

Re: [PATCH 0/2] Adds designware i2c module and adds it to virt arm

an hold back the designware stuff until another SoC platform is interested in using this controller (since it seems like it is a common one). Hopefully someone will find another use for the controller patches someday. Thanks again for looking at our patches. -Chris On Wed, Jan 26, 2022 at 3:4

Re: [PATCH 0/2] Adds designware i2c module and adds it to virt arm

ndalone PCI I2C controllers. I’ve seen I2C controllers on PCI devices with other things but I don’t think those could be used for IPMI SSIF or other general I2C use cases. Do you know of a particular device I should take a look at? -Chris On Wed, Jan 26, 2022 at 10:03 AM Peter Maydell wrote: &

Re: [PATCH 0/2] Adds designware i2c module and adds it to virt arm

rm quirks, and we don't need all the things in that IO hub. -Chris

Re: dozens of qemu/kvm VMs getting into stuck states since kernel ~5.13

On Tue, Dec 7, 2021 at 5:25 PM Sean Christopherson wrote: > > On Tue, Dec 07, 2021, Chris Murphy wrote: > > cc: qemu-devel > > > > Hi, > > > > I'm trying to help progress a very troublesome and so far elusive bug > > we're seeing in Fedora inf

dozens of qemu/kvm VMs getting into stuck states since kernel ~5.13

can take a glance at those kernel messages, and/or give hints how we can extract more information for debugging, it'd be appreciated. Maybe all of that is normal and the actual problem isn't in any of these traces. Thanks, -- Chris Murphy

Re: [Bug 1914117] Short files returned via FTP on Qemu with various architectures and OSes

I tested Qemu 6.1 (MacOS using brew to install) with guest OS NetBSD/i386. The bind distribution file downloaded fine by FTP. Libslurp has a workaround for MacOS and it looks like its gone in. I think this one can be closed. Sorry for the delay Kind regards Chris > On 25 Aug 2021, at 08

[PATCH v2] hw/arm: Add support for kudo-bmc board.

kudo-bmc is a board supported by OpenBMC. https://github.com/openbmc/openbmc/tree/master/meta-fii/meta-kudo Since v1: - hyphenated Cortex-A9 Tested: Booted kudo firmware. Signed-off-by: Chris Rauer --- docs/system/arm/nuvoton.rst | 1 + hw/arm/npcm7xx_boards.c | 34

[PATCH] hw/arm: Add support for kudo-bmc board.

kudo-bmc is a board supported by OpenBMC. https://github.com/openbmc/openbmc/tree/master/meta-fii/meta-kudo Tested: Booted kudo firmware. Signed-off-by: Chris Rauer --- docs/system/arm/nuvoton.rst | 1 + hw/arm/npcm7xx_boards.c | 34 ++ 2 files changed, 35

[PATCH v1 QEMU CXL modifications for openspdm 1/1] pcie/spdm: PCIe CMA implementation

esponder to get the data object of SPDM/secured SPDM. Signed-off-by: hchkuo Signed-off-by: Chris Browy --- hw/mem/cxl_type3.c | 31 +++- hw/pci/Kconfig | 4 + hw/pci/SpdmEmuCommand.c | 319 hw/pci/meson.build

[PATCH v1 QEMU CXL modifications for openspdm 0/1] Testing PCIe DOE in QEMU CXL/PCIe Device using openspdm

This patch series provides an implementation of the the Data Object Exchange (DOE) for Component Measurement and Authentication (CMA) of the Security Protocol and Data Model (SPDM). This patch is based on [1] [PATCH v1 openspdm on QEMU CXL/PCIe Device 0/2] Testing PCIe DOE in QEMU CXL/PCIe Devi

[PATCH v1 openspdm on QEMU CXL/PCIe Device 2/2] requester: Modified for QEMU emulation

From: hchkuo The requester should be used as a PCIe app to access the SPDM object in the PCEe device. Signed-off-by: Chris Browy --- Include/IndustryStandard/PciDoeBinding.h| 27 +++ SpdmEmu/SpdmEmuCommon/SpdmEmu.c | 85 ++ SpdmEmu/SpdmEmuCommon

[PATCH v1 openspdm on QEMU CXL/PCIe Device 1/2] build: gcc to CC in GNUMakefile

From: hchkuo Modified gcc to CC in GNUMakefile, so that we can specify the gcc version Signed-off-by: Chris Browy --- GNUmakefile.Flags | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/GNUmakefile.Flags b/GNUmakefile.Flags index 3586284..33baceb 100644 --- a

[PATCH v1 openspdm on QEMU CXL/PCIe Device 0/2] Testing PCIe DOE in QEMU CXL/PCIe Device using openspdm

This patch series provides an implementation of the the Data Object Exchange (DOE) for Component Measurement and Authentication (CMA) of the Security Protocol and Data Model (SPDM). This patch is based on [1] Openspdm: https://github.com/jyao1/openspdm.git Openspdm is an emulator composed of an

[PATCH v6 cxl2.0-v6-doe 4/6] cxl/compliance: CXL Compliance Data Object Exchange implementation

ned-off-by: Chris Browy --- hw/mem/cxl_type3.c | 147 include/hw/cxl/cxl_compliance.h | 293 include/hw/cxl/cxl_component.h | 3 + include/hw/cxl/cxl_device.h | 3 + include/hw/cxl/cxl_pci.h| 1 + 5 files ch

[PATCH v6 cxl2.0-v6-doe 6/6] test/cdat: CXL CDAT test data

From: hchkuo Pre-built CDAT table for testing, contains one CDAT header and six CDAT entries: DSMAS, DSLBIS, DSMSCIS, DSIS, DSEMTS, and SSLBIS respectively. Signed-off-by: hchkuo Signed-off-by: Chris Browy --- tests/data/cdat/cdat.dat | Bin 0 -> 148 bytes 1 file changed, 0 insertions(+)

[PATCH v6 cxl2.0-v6-doe 3/6] hw/pci: PCIe Data Object Exchange implementation

n will be early returned if not within the related DOE range. Signed-off-by: hchkuo Signed-off-by: Chris Browy --- MAINTAINERS | 7 + hw/pci/meson.build| 1 + hw/pci/pcie_doe.c | 374 ++ include/hw/pci/pcie.h | 1 +

[PATCH v6 cxl2.0-v6-doe 2/6] include/hw/pci: headers for PCIe DOE

From: hchkuo Macros for the vender ID of PCI-SIG mentioned in "PCIe Data Object Exchange ECN, March 12, 2020" and the size of PCIe Data Object Exchange. Signed-off-by: hchkuo Signed-off-by: Chris Browy --- include/hw/pci/pci_ids.h | 3 +++ include/hw/pci/pcie_regs.h | 4 +++

[PATCH v6 cxl2.0-v6-doe 5/6] cxl/cdat: CXL CDAT Data Object Exchange implementation

y of CDAT is added to hw/mem/cxl_type3.c with capability offset 0x190. The config read/write to this capability range can be generated in the OS to request the CDAT data. Signed-off-by: hchkuo Signed-off-by: Chris Browy --- hw/cxl/cxl-cdat.c | 139 ++ h

[PATCH v6 cxl2.0-v6-doe 1/6] standard-headers/linux/pci_regs: PCI header from Linux kernel

From: hchkuo Linux standard header for the registers of PCI Data Object Exchange (DOE). This header might be generated via script. The DOE feature should be added in the future Linux release so this patch can be removed then. Signed-off-by: hchkuo Signed-off-by: Chris Browy --- include

[PATCH v6 cxl2.0-v6-doe 0/6] QEMU PCIe DOE for PCIe 4.0/5.0 and CXL 2.0

This patch implements the PCIe Data Object Exchange (DOE) for PCIe 4.0/5.0 and later and CXL 2.0 "type-3" memory devices supporting the following protocols: 1: PCIe DOE Discovery protocol 2: CXL DOE Compliance Mode protocol 3: CXL DOE CDAT protocol Implementation is based on QEMU version which

Re: [Bug 1914117] Re: Short files returned via FTP on Qemu with various architectures and OSes

If it’s included in qemu when one downloads the sources I’m happy. Sent from my iPhone > On 15 May 2021, at 11:55, Thomas Huth <1914...@bugs.launchpad.net> wrote: > > Could we close this ticket now if there is a workaround in libslirp now? > > ** Changed in: qemu > Status: New => Incompl

[PATCH v5 cxl2.0-v3-doe 6/6] test/cdat: CXL CDAT test data

From: hchkuo Pre-built CDAT table for testing, contains one CDAT header and six CDAT entries: DSMAS, DSLBIS, DSMSCIS, DSIS, DSEMTS, and SSLBIS respectively. Signed-off-by: Chris Browy --- tests/data/cdat/cdat.dat | Bin 0 -> 148 bytes 1 file changed, 0 insertions(+), 0 deletions(-) cre

[PATCH v5 cxl2.0-v3-doe 5/6] cxl/cdat: CXL CDAT Data Object Exchange implementation

y of CDAT is added to hw/mem/cxl_type3.c with capability offset 0x190. The config read/write to this capability range can be generated in the OS to request the CDAT data. Signed-off-by: Chris Browy --- hw/cxl/cxl-cdat.c | 228 + hw/cxl/meson.

[PATCH v5 cxl2.0-v3-doe 4/6] cxl/compliance: CXL Compliance Data Object Exchange implementation

ost of the compliance response is limited to returning corresponding length. A DOE capability of CXL Compliance is added to hw/mem/cxl_type3.c with capability offset 0x160. The config read/write to this capability range can be generated in the OS to request the Compliance info. Signed-off-by: Chris Brow

[PATCH v5 cxl2.0-v3-doe 3/6] hw/pci: PCIe Data Object Exchange implementation

n will be early returned if not within the related DOE range. Signed-off-by: Chris Browy --- MAINTAINERS | 7 + hw/pci/meson.build| 1 + hw/pci/pcie_doe.c | 374 ++ include/hw/pci/pcie.h | 1 + include/hw/pci/p

[PATCH v5 cxl2.0-v3-doe 2/6] include/hw/pci: headers for PCIe DOE

From: hchkuo Macros for the vender ID of PCI-SIG and the size of PCIe Data Object Exchange. Signed-off-by: Chris Browy --- include/hw/pci/pci_ids.h | 2 ++ include/hw/pci/pcie_regs.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h

[PATCH v5 cxl2.0-v3-doe 1/6] standard-headers/linux/pci_regs: PCI header from Linux kernel

From: hchkuo Linux standard header for the registers of PCI Data Object Exchange (DOE). This header might be generated via script. The DOE feature should be added in the future Linux release so this patch can be removed then. Signed-off-by: Chris Browy --- include/standard-headers/linux

[PATCH v5 cxl2.0-v3-doe 0/6] QEMU PCIe DOE for PCIe 4.0/5.0 and CXL 2.0

This patch implements the PCIe Data Object Exchange (DOE) for PCIe 4.0/5.0 and later and CXL 2.0 "type-3" memory devices supporting the following protocols: 1: PCIe DOE Discovery protocol 2: CXL DOE Compliance Mode protocol 3: CXL DOE CDAT protocol Implementation is based on QEMU version which

[Bug 1580459] Re: Windows (10?) guest freezes entire host on shutdown if using PCI passthrough

I am no longer having any issues at all. I am using the NVidia Sound Card as well. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1580459 Title: Windows (10?) guest freezes entire host on shutdown

[PATCH v4 cxl-2.0-doe 3/3] PCIe standard header for DOE

From: hchkuo Signed-off-by: hchkuo --- include/hw/pci/pci_ids.h | 2 ++ include/hw/pci/pcie_regs.h| 3 +++ include/standard-headers/linux/pci_regs.h | 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/

[PATCH v4 cxl-2.0-doe 2/3] CXL Data Object Exchange implementation

From: hchkuo Signed-off-by: hchkuo --- hw/cxl/cxl-cdat.c | 220 + hw/cxl/meson.build | 1 + hw/mem/cxl_type3.c | 200 +++ include/hw/cxl/cxl_cdat.h | 149 include/hw/cxl/cxl_

[PATCH v4 cxl-2.0-doe 1/3] PCIe Data Object Exchange implementation

DOE +M: Huai-Cheng Kuo +M: Chris Browy +S: Supported +F: include/hw/pci/pcie_doe.h +F: hw/pci/pcie_doe.c + ACPI/SMBIOS M: Michael S. Tsirkin M: Igor Mammedov diff --git a/hw/pci/meson.build b/hw/pci/meson.build index 5c4bbac..115e502 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build

[PATCH v4 cxl-2.0-doe 0/3] QEMU PCIe DOE for PCIe and CXL2.0

Version 4 patch series for PCIe DOE for PCIe and CXL 2.0 completes all planned functionality. Based on QEMU version: https://gitlab.com/bwidawsk/qemu/-/tree/cxl-2.0v4 Summary of changes: 1: PCIe DOE support for Discovery - Fix the alignment error in DOE config write - Fix the interr

[RFC PATCH v3 cxl-2.0-doe 2/2] CXL DOE support for CDAT and Compliance Mode

--- hw/cxl/cxl-component-utils.c | 93 hw/mem/cxl_type3.c | 184 include/hw/cxl/cxl_cdat.h | 127 + include/hw/cxl/cxl_compl.h | 252 + include/hw/cxl/cxl_component.h | 74 ++ inc

[RFC PATCH v3 cxl-2.0-doe 1/2] Basic PCIe DOE support

: docs/system/cpu-models-mips.rst.inc F: hw/intc/mips_gic.c @@ -263,7 +254,7 @@ S: Maintained F: target/moxie/ F: disas/moxie.c F: hw/moxie/ -F: default-configs/*/moxie-softmmu.mak +F: default-configs/moxie-softmmu.mak NiosII TCG CPUs M: Chris Wulff @@ -272,7 +263,7 @@ S: Maintained F

[RFC PATCH v3 cxl-2.0-doe 0/2] Version 3 patch series for PCIe DOE for PCIe and CXL 2.0

es/resources/Coherent%20Device%20Attribute%20Table_1.02.pdf --- Chris Browy (2): Basic PCIe DOE support CXL DOE support for CDAT and Compliance Mode MAINTAINERS | 49 +-- hw/cxl/cxl-component-utils.c | 93 + hw/mem/cxl_type3.c

Re: [RFC PATCH v2 1/2] Basic PCIe DOE support

> On Mar 4, 2021, at 2:21 PM, Jonathan Cameron > wrote: > > On Tue, 9 Feb 2021 15:35:49 -0500 > Chris Browy wrote: > > Hi Chris, > > One more thing hit whilst debugging linux side of this. > >> +static void pcie_doe_irq_assert(DOECap *doe_cap) >>

[Bug 1914117] Re: Short files returned via FTP on Qemu with various architectures and OSes

libslirp now has a workaround for this in slirp.c. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1914117 Title: Short files returned via FTP on Qemu with various architectures and OSes Status in

Re: [RFC v2 2/2] Basic CXL DOE for CDAT and Compliance Mode

> On Feb 18, 2021, at 2:15 PM, Jonathan Cameron > wrote: > > On Fri, 12 Feb 2021 17:26:50 -0500 > Chris Browy wrote: > >>> On Feb 12, 2021, at 12:23 PM, Jonathan Cameron >>> wrote: >>> >>> On Tue, 9 Feb 2021 15:36:03 -0500 >>&g

Re: [RFC PATCH v2 1/2] Basic PCIe DOE support

> On Feb 18, 2021, at 2:11 PM, Jonathan Cameron > wrote: > > On Fri, 12 Feb 2021 16:58:21 -0500 > Chris Browy wrote: > >>> On Feb 12, 2021, at 11:24 AM, Jonathan Cameron >>> wrote: >>> >>> On Tue, 9 Feb 2021 15:35:49 -0500 >&g

Re: [RFC v2 2/2] Basic CXL DOE for CDAT and Compliance Mode

> On Feb 12, 2021, at 12:23 PM, Jonathan Cameron > wrote: > > On Tue, 9 Feb 2021 15:36:03 -0500 > Chris Browy wrote: > > Split this into two patches for v3. CDAT in one, compliance mode in the > other. > Compliance mode is an optional feature. We’ll split i

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