Re: [PATCH v3 2/2] target/riscv: Restrict midelegh access to S-mode harts

I intended to separate the S-mode and M-mode handling. Do you think this change could improve performance? Thanks, Jay Chang On Tue, Jul 1, 2025 at 11:46 AM Nutty Liu wrote: > On 7/1/2025 11:00 AM, Jay Chang wrote: > > RISC-V AIA Spec states: > > "For a machine-level en

[PATCH v3 0/2] Add S-mode checks for delegation-related CSRs

updated predicate in aia_smode32. Change log: V3: * Add cover letter Jay Chang (2): target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts target/riscv: Restrict midelegh access to S-mode harts target/riscv/csr.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.48.1

[PATCH v3 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

deleg registers should not exist." Add smode predicate to ensure these CSRs are only accessible when S-mode is supported. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jay Chang --- target/riscv/csr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --gi

[PATCH v3 2/2] target/riscv: Restrict midelegh access to S-mode harts

me as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jay Chang --- ta

Re: [PATCH v2 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

Hi, Gentle ping on this patch. Thanks, Jay Chang On Tue, Apr 1, 2025 at 6:34 PM Jay Chang wrote: > RISC-V Privileged Spec states: > "In harts with S-mode, the medeleg and mideleg registers must exist, and > setting a bit in medeleg or mideleg will delegate the corresponding

[PATCH v5 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Signed-off-by: Jay Chang Reviewed-by: Frank Chang --- target/riscv/cpu.c| 48

[PATCH v5 0/2] Extend and configure PMP region count

uld set its own default if they want. (based on feedback from Daniel) Jay Chang (2): target/riscv: Extend PMP region up to 64 target/riscv: Make PMP region count configurable target/riscv/cpu.c| 48 ++- target/riscv/cpu.h| 3 +- target/ri

[PATCH v5 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Signed-off-by: Jay Chang Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/ri

Re: [PATCH v4 2/2] target/riscv: Make PMP region count configurable

*Hi Daniel,* You're absolutely right — thanks for pointing it out and providing the fix! Would you like me to send out a v5 patch incorporating your changes? Best Regards Jay Chang On Thu, Jun 5, 2025 at 2:20 AM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: >

[PATCH v3 0/2] Extend and configure PMP region count

Jay Chang (2): target/riscv: Extend PMP region up to 64 target/riscv: Make PMP region count configurable target/riscv/cpu.c| 54 - target/riscv/cpu.h| 3 +- target/riscv/cpu_bits.h | 60 ++ target/riscv/cpu_cfg_fields.h.inc |

[PATCH v4 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Signed-off-by: Jay Chang Reviewed-by: Frank Chang --- target/riscv/cpu.c| 54

[PATCH v4 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Signed-off-by: Jay Chang Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/ri

[PATCH v4 0/2] Extend and configure PMP region count

Jay Chang (2): target/riscv: Extend PMP region up to 64 target/riscv: Make PMP region count configurable target/riscv/cpu.c| 54 - target/riscv/cpu.h| 3 +- target/riscv/cpu_bits.h | 60 ++ target/riscv/cpu_cfg_fields.h.inc |

[PATCH v3 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Signed-off-by: Jay Chang Reviewed-by: Frank Chang --- target/riscv/cpu.c| 54

[PATCH v3 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Signed-off-by: Jay Chang Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/ri

[PATCH 2/2] target/riscv: Add standard B extension implied rule

From: Frank Chang Add the missing implied rule for standard B extension. Standard B extension implies Zba, Zbb, Zbs extensions. RISC-V B spec: https://github.com/riscv/riscv-b Signed-off-by: Frank Chang Reviewed-by: Jerry Zhang Jian Reviewed-by: Jim Shu --- target/riscv/cpu.c | 14

[PATCH 1/2] target/riscv: Add the implied rule for G extension

From: Jim Shu Add the missing implied rule from G to imafd_zicsr_zifencei. Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- target/riscv/cpu.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d92874baa0

[PATCH v2 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/cpu_bits.h | 60 +++ target/riscv/csr.c |

[PATCH v2 0/2] Extend and configure PMP region count

pmp-regions`. This allows platforms to adjust the number of PMP regions without relying on a fixed default value. If unspecified, the default remains 16 to preserve compatibility. change log: V2: * Rebase on riscv-to-apply.next Jay Chang (2): target/riscv: Extend PMP region up to 64 target/ri

[PATCH v2 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/cpu.c| 54

Re: [PATCH 2/2] target/riscv: Make PMP region count configurable

I will send v2 patch Jay Chang On Thu, Apr 24, 2025 at 6:55 PM Alistair Francis wrote: > On Mon, Apr 21, 2025 at 7:48 PM Jay Chang wrote: > > > > Previously, the number of PMP regions was hardcoded to 16 in QEMU. > > This patch replaces the fixed value with a ne

[PATCH 1/2] target/riscv: Extend PMP region up to 64

According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0–pmpcfg15) to configure 64 PMP regions (pmpaddr0–pmpaddr63). Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/cpu_bits.h | 60 +++ target/riscv/csr.c |

[PATCH 2/2] target/riscv: Make PMP region count configurable

behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=true, c=true, pmp=true, num-pmp-regions=8 Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/cpu.c | 46

[PATCH 0/2] Extend and configure PMP region count

pmp-regions`. This allows platforms to adjust the number of PMP regions without relying on a fixed default value. If unspecified, the default remains 16 to preserve compatibility. Jay Chang (2): target/riscv: Extend PMP region up to 64 target/riscv: Make PMP region count configurable target/ri

[PATCH 2/2] target/riscv: Restrict midelegh access to S-mode harts

me as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/csr.c | 7 +-- 1 fi

[PATCH v2 2/2] target/riscv: Restrict midelegh access to S-mode harts

me as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/csr.c | 7 +-- 1 fi

[PATCH v2 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

deleg registers should not exist." Add smode predicate to ensure these CSRs are only accessible when S-mode is supported. Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/csr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/ta

Re: [PATCH for-10.1] hw/riscv: do not mark any machine as default

Reviewed-by: Frank Chang Daniel Henrique Barboza 於 2025年3月27日 週四 下午9:04寫道： > > Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and > made it default for qemu-system-riscv32/64. It was the first RISC-V > machine added in QEMU so setting it as default w

Re: [PATCH 2/2] target/riscv: Restrict midelegh access to S-mode harts

enrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 3/18/25 4:01 AM, Jay Chang wrote: > > RISC-V AIA Spec states: > > "For a machine-level environment, extension Smaia encompasses all added > > CSRs and all modifications to interrupt response behavior that

[PATCH 1/2] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

deleg registers should not exist." Add smode predicate to ensure these CSRs are only accessible when S-mode is supported. Reviewed-by: Frank Chang Signed-off-by: Jay Chang --- target/riscv/csr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/ta

Re: [PATCH v11 3/6] target/riscv: Handle Smrnmi interrupt and exception

and 'rnmi-exception-vector' as the > property > > of the harts. It’s very easy for users to set the address based on their > > expectation. This patch also adds the functionality to handle the RNMI > signals. > > > > Signed-off-by: Frank Chang > > Signed-of

[PATCH v12 3/6] target/riscv: Handle Smrnmi interrupt and exception

the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza --- hw/riscv/riscv_hart.c | 41 include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c| 11 + target/riscv/c

Re: [PATCH v11 5/6] target/riscv: Add Smrnmi cpu extension

> > mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all > > interrupts will be disabled. Since our current OpenSBI does not > > support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for > > now. We can re-enable it once OpenSBI include

[PATCH v12 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/c

[PATCH v12 6/6] target/riscv: Add Zicfilp support for Smrnmi

From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of

[PATCH v12 4/6] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang

[PATCH v12 0/6] Add Smrnmi support

From: Frank Chang This patchset added support for Smrnmi Extension in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x740) * mnepc (0x741

[PATCH v12 2/6] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h

[PATCH v12 5/6] target/riscv: Add Smrnmi cpu extension

x27;s disable Smrnmi for the 'max' type CPU for now. We can re-enable it once OpenSBI includes proper support for it. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Signed-off-by: Daniel Henrique Barboza Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 ++ targe

[PATCH v11 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/c

[PATCH v11 5/6] target/riscv: Add Smrnmi cpu extension

x27;s disable Smrnmi for the 'max' type CPU for now. We can re-enable it once OpenSBI includes proper support for it. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Signed-off-by: Daniel Henrique Barboza Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 ++ targe

[PATCH v11 6/6] target/riscv: Add Zicfilp support for Smrnmi

From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of

[PATCH v11 2/6] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h

[PATCH v11 3/6] target/riscv: Handle Smrnmi interrupt and exception

the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza --- hw/riscv/riscv_hart.c | 42 - include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c| 11 + target/riscv/c

[PATCH v11 4/6] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang

[PATCH v11 0/6] Add Smrnmi support

From: Frank Chang This patchset added support for Smrnmi Extension in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x740) * mnepc (0x741

Re: [PATCH v10 3/7] target/riscv: Handle Smrnmi interrupt and exception

gt; We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the > property > > of the harts. It’s very easy for users to set the address based on their > > expectation. This patch also adds the functionality to handle the RNMI > signals. > &g

[PATCH v10 3/7] target/riscv: Handle Smrnmi interrupt and exception

the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 40 + include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c| 11 + target/riscv/cpu.h| 3 ++ target/riscv/c

[PATCH v10 0/7] Add Smrnmi support

From: Frank Chang This patchset added support for Smrnmi Extension in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x740) * mnepc (0x741

[PATCH v10 4/7] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang

[PATCH v10 7/7] target/riscv: Disable Smrnmi for the 'max' type CPU

From: Frank Chang When Smrnmi is present, the firmware (e.g., OpenSBI) must set mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all interrupts will be disabled. Since our current OpenSBI does not support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for

[PATCH v10 2/7] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h

[PATCH v10 5/7] target/riscv: Add Smrnmi cpu extension

From: Tommy Wu This adds the properties for ISA extension Smrnmi. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e6988f44c6..7a4aa235ce 100644 --- a/target/riscv

[PATCH v10 1/7] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/c

[PATCH v10 6/7] target/riscv: Add Zicfilp support for Smrnmi

From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of

Re: [PATCH v9 0/6] Add Smrnmi support

pdate_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); > } > + > +/* > + * ext_smrnmi requires OpenSBI changes that our current > + * image does not have. Disable it for now. > + */ > +isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); > } > > This will make

Re: [PATCH v9 0/6] Add Smrnmi support

Hi, A gentle ping on this. Regards, Frank Chang 於 2024年11月22日 週五 上午11:23寫道： > > From: Frank Chang > > This patchset added support for Smrnmi Extension in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable

[PATCH v9 4/6] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang

[PATCH v9 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/c

Re: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

On Wed, Nov 20, 2024 at 11:29 AM Frank Chang wrote: > On Mon, Nov 18, 2024 at 11:13 AM Alistair Francis > wrote: > >> On Mon, Oct 21, 2024 at 1:06 PM wrote: >> > >> > From: Tommy Wu >> > >> > Because the RNMI interrupt trap handler address

[PATCH v9 5/6] target/riscv: Add Smrnmi cpu extension

From: Tommy Wu This adds the properties for ISA extension Smrnmi. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b402d8545b..6c91464a00 100644 --- a/target/riscv

[PATCH v9 6/6] target/riscv: Add Zicfilp support for Smrnmi

From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of

[PATCH v9 0/6] Add Smrnmi support

From: Frank Chang This patchset added support for Smrnmi Extension in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x740) * mnepc (0x741

[PATCH v9 3/6] target/riscv: Handle Smrnmi interrupt and exception

the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 40 + include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c| 11 + target/riscv/cpu.h| 3 ++ target/riscv/c

[PATCH v9 2/6] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h

Re: [PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

and 'rnmi-exception-vector' as the > property > > of the harts. It’s very easy for users to set the address based on their > > expectation. This patch also adds the functionality to handle the RNMI > signals. > > > > Signed-off-by: Frank Chang > > Signe

[PATCH v8 0/5] Add Smrnmi support

From: Frank Chang This patchset added support for Smrnmi Extension in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x740) * mnepc (0x741

[PATCH v8 4/5] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang

[PATCH v8 3/5] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ tar

[PATCH v8 2/5] target/riscv: Handle Smrnmi interrupt and exception

the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 18 include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c| 11 + target/riscv/cpu.h| 6 +++ target/riscv/cpu_bits.h

[PATCH v8 5/5] target/riscv: Add Smrnmi cpu extension

From: Tommy Wu This adds the properties for ISA extension Smrnmi. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b3195da512..fed64741d1 100644 --- a/target/riscv

[PATCH v8 1/5] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/c

Re: [PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

On Thu, Oct 17, 2024 at 7:18 PM Rajnesh Kanwal wrote: > On Tue, Aug 27, 2024 at 10:28 AM Frank Chang > wrote: > > > > Rajnesh Kanwal 於 2024年6月19日 週三 下午11:27寫道： > > > > > > This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and > > > sctrd

Re: [PATCH v7 2/5] target/riscv: Handle Smrnmi interrupt and exception

ode. Otherwise, we may hit the assertion in: riscv_pmu_cycle_update_priv(), and riscv_pmu_icount_update_priv() The TLB will also not be flushed properly on the virt mode changed. I will fix it in the next patchset. Thanks, Frank Chang > > Thanks, > > Clément > > > > + return; > > + } > >

[PATCH v7 1/5] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig

From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/c

[PATCH v7 5/5] target/riscv: Add Smrnmi cpu extension

From: Tommy Wu This adds the properties for ISA extension Smrnmi. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b3195da512..fed64741d1 100644 --- a/target/riscv

[PATCH v7 3/5] target/riscv: Add Smrnmi CSRs

From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ tar

[PATCH v7 4/5] target/riscv: Add Smrnmi mnret instruction

From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang

[PATCH v7 2/5] target/riscv: Handle Smrnmi interrupt and exception

the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- hw/riscv/riscv_hart.c | 18 include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c| 11 + target/riscv/cpu.h| 6 +++ target/riscv/cpu_bits.h

[PATCH v7 0/5] Add Smrnmi support

From: Frank Chang This patchset added support for Smrnmi Extension in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x740) * mnepc (0x741

Re: [PATCH v6 0/5] target/riscv: Add Smrnmi support.

nt Hi Clément, Sorry for keeping you waiting. I've reviewed the comments from you and Alistair. The comments should be straightforward to fix. I will fix them and send out the patchset later today. Hope that it makes things easier. Regards, Frank Chang > > > Alistair so > &

Re: [PATCH v6 0/5] target/riscv: Add Smrnmi support.

Hi Daniel, Thanks for the reminder. I'll take over Tommy's work to send out the v7 patchset later this week. Regards, Frank Chang On Fri, Oct 11, 2024 at 7:38 PM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > Hi Tommy, > > > Do you plan to send a n

Re: [PATCH v2 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

gt; bool ext_smaia; > bool ext_ssaia; > +bool ext_smctr; > +bool ext_ssctr; Base on: https://github.com/riscv/riscv-control-transfer-records/pull/29 Smctr and Ssctr depend on both S-mode and Sscsrind. We should add the implied rules for Smctr and Ssctr. Regards, Frank Chang

[PATCH v4 0/2] RISC-V: Add preliminary textra trigger CSR functions

condition between textra.MHVALUE and mcontext CSR is also implemented. Changes from v3: - Simplify the comparison between mcontext and textra.MHVALUE Changes from v2: - Remove redundant log Changes from v1: - Log that mhselect only supports 0 or 4 for now - Simplify writing of tdata3 Alvin Chang (2

[PATCH v4 1/2] target/riscv: Preliminary textra trigger CSR writting support

. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang Reviewed-by: Alistair

[PATCH v4 2/2] target/riscv: Add textra matching condition for the triggers

textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 45 +++- target/riscv

[PATCH] RISC-V: Remove riscv_cpu_claim_interrupts()

ask. It seems the function of riscv_cpu_claim_interrupts() is no longer used. Therefore, we remove it in this commit. Signed-off-by: Alvin Chang --- hw/intc/riscv_aclint.c| 20 hw/intc/riscv_aplic.c | 11 --- hw/intc/riscv_imsic.c | 8 hw/intc/sifive_plic.c

Re: [PATCH] target/riscv: Add a property to set vl to ceil(AVL/2)

Reviewed-by: Frank Chang Jason Chien 於 2024年7月23日 週二 上午1:51寫道： > > RVV spec allows implementations to set vl with values within > [ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a > property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). Th

[PATCH v3 1/2] target/riscv: Preliminary textra trigger CSR writting support

. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang Reviewed-by: Alistair

[PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR functions

condition between textra.MHVALUE and mcontext CSR is also implemented. Changes from v2: - Remove redundant log Changes from v1: - Log that mhselect only supports 0 or 4 for now - Simplify writing of tdata3 Alvin Chang (2): target/riscv: Preliminary textra trigger CSR writting support target

[PATCH v3 2/2] target/riscv: Add textra matching condition for the triggers

textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- target/riscv/debug.c | 63

[PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

attendant side effects. So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies a register holding a zero value, an illegal instruction exception should be raised. Signed-off-by: Yu-Ming Chang Signed-off-by: Alvin Chang --- Hi Alistair, This fixed the issue of riscv_csrrw_debug

[PATCH v2 0/2] RISC-V: Add preliminary textra trigger CSR functions

condition between textra.MHVALUE and mcontext CSR is also implemented. Changes from v1: - Log that mhselect only supports 0 or 4 for now - Simplify writing of tdata3 Alvin Chang (2): target/riscv: Preliminary textra trigger CSR writting support target/riscv: Add textra matching condition for the

[PATCH v2 1/2] target/riscv: Preliminary textra trigger CSR writting support

. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang --- target/riscv

[PATCH v2 2/2] target/riscv: Add textra matching condition for the triggers

textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis --- target/riscv/debug.c | 63

[PATCH 2/2] target/riscv: Add textra matching condition for the triggers

textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang --- target/riscv/debug.c | 63 +++- target/riscv

[PATCH 1/2] target/riscv: Preliminary textra trigger CSR writting support

. For textra.MHSELECT field, the only legal values are 0 (ignore) and 4 (mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is aligned to RISC-V SPIKE simulator. Signed-off-by: Alvin Chang --- target/riscv

[PATCH 0/2] RISC-V: Add preliminary textra trigger CSR functions

condition between textra.MHVALUE and mcontext CSR is also implemented. Alvin Chang (2): target/riscv: Preliminary textra trigger CSR writting support target/riscv: Add textra matching condition for the triggers target/riscv/cpu_bits.h | 10 +++ target/riscv/debug.c| 144

Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

static RISCVException write_menvcfg(CPURISCVState > *env, int csrno, > (cfg->ext_sstc ? MENVCFG_STCE : 0) | > (cfg->ext_svadu ? MENVCFG_ADUE : 0); > } > +/* Update PMM field only if the value is valid according to Zjpm v0.8 */ > +if (((val &

Re: [PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

9b6 100644 > --- a/target/riscv/pmp.h > +++ b/target/riscv/pmp.h > @@ -40,11 +40,12 @@ typedef enum { > } pmp_am_t; > > typedef enum { > -MSECCFG_MML = 1 << 0, > -MSECCFG_MMWP = 1 << 1, > -MSECCFG_RLB = 1 << 2, > -MSECCFG_USEED = 1 << 8, > -MSECCFG_SSEED = 1 << 9 > +MSECCFG_MML = 1 << 0, > +MSECCFG_MMWP = 1 << 1, > +MSECCFG_RLB = 1 << 2, > +MSECCFG_USEED = 1 << 8, > +MSECCFG_SSEED = 1 << 9, > +MSECCFG_PMM = 3UL << 32, Should use '3ULL' to left shift bits more than 31 bits. Otherwise, it would generate the error: "error: left shift count >= width of type [-Werror=shift-count-overflow]" Regards, Frank Chang > } mseccfg_field_t; > > typedef struct { > -- > 2.34.1 > >

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