Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

2025-07-15 Thread CLEMENT MATHIEU--DRIF
On 15/07/2025 2:35 pm, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 2025/7/15 14:11, CLEMENT MATHIEU--DRIF wrote: >> >> >> On 14/07/2

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

2025-07-15 Thread CLEMENT MATHIEU--DRIF
On 15/07/2025 10:27 am, David Woodhouse wrote: > On Tue, 2025-07-15 at 06:11 +0000, CLEMENT MATHIEU--DRIF wrote: >> >> >> On 14/07/2025 11:22 pm, Konstantin Belousov wrote: >>> Caution: External email. Do not open attachments or click links, >>> unless t

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

2025-07-14 Thread CLEMENT MATHIEU--DRIF
On 14/07/2025 11:22 pm, Konstantin Belousov wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Mon, Jul 14, 2025 at 05:41:22PM +0100, David Woodhouse wrote: >> On 14 July 2025 15:28:

[PATCH 04/10] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry

2025-06-28 Thread CLEMENT MATHIEU--DRIF
PASID value must be used by devices as a key (or part of a key) when populating their ATC with the IOTLB entries returned by the IOMMU. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386

[PATCH v5 00/10] intel_iommu: Add ATS support

2025-06-28 Thread CLEMENT MATHIEU--DRIF
ew by Michael: - Split long lines in memory.h - Change patch encoding (no UTF-8) - Changes after review by Zhenzhong: - Rework "Fill the PASID field when creating an IOMMUTLBEntry" Clement Mathieu--Drif (10): pci: Add a memory attribute for pre-translated DMA ope

[PATCH 10/10] intel_iommu: Add support for ATS

2025-06-28 Thread CLEMENT MATHIEU--DRIF
Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 63 +++ 1 file changed, 63 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1b1b0b5632..fe9a5f2872 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386

[PATCH 05/10] intel_iommu: Declare supported PASID size

2025-06-28 Thread CLEMENT MATHIEU--DRIF
the PSS field of the extended capabilities stores the supported PASID size minus 1. This commit adds support for 8bits PASIDs (limited by MemTxAttrs::pid). Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2

[PATCH 06/10] intel_iommu: Implement vtd_get_iotlb_info from PCIIOMMUOps

2025-06-28 Thread CLEMENT MATHIEU--DRIF
Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 71497f1936..affa7768e6 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4733,10 +4733,20 @@ static

[PATCH 08/10] intel_iommu: Return page walk level even when the translation fails

2025-06-28 Thread CLEMENT MATHIEU--DRIF
We will use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage is not present. Signed-off-by: Clement Mathieu--Drif --- hw/i386

[PATCH 02/10] memory: Add permissions in IOMMUAccessFlags

2025-06-28 Thread CLEMENT MATHIEU--DRIF
) : - Execute Requested - Privileged Mode Requested - Global - Untranslated Only IOMMU_ACCESS_FLAG sets the additional flags to 0 Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 23 +-- 1 file changed, 21 insertions(+), 2 deletions(-) diff

[PATCH 07/10] intel_iommu: Implement the PCIIOMMUOps callbacks related to invalidations of device-IOTLB

2025-06-28 Thread CLEMENT MATHIEU--DRIF
Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index affa7768e6..234c452849 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c

[PATCH 01/10] pci: Add a memory attribute for pre-translated DMA operations

2025-06-28 Thread CLEMENT MATHIEU--DRIF
The address_type bit will be set to PCI_AT_TRANSLATED by devices that use cached addresses obtained via ATS. Signed-off-by: Clement Mathieu--Drif --- include/exec/memattrs.h | 3 +++ include/hw/pci/pci.h| 9 + 2 files changed, 12 insertions(+) diff --git a/include/exec/memattrs.h b

[PATCH 09/10] intel_iommu: Set address mask when a translation fails and adjust W permission

2025-06-28 Thread CLEMENT MATHIEU--DRIF
Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386

[PATCH 03/10] memory: Allow to store the PASID in IOMMUTLBEntry

2025-06-28 Thread CLEMENT MATHIEU--DRIF
This will be useful for devices that support ATS and need to store entries in an ATC (device IOTLB). Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/system/memory.h b/include/system/memory.h index 1672622d70

Re: [PATCH 0/2] Memory and PCI definitions for emulated ATS

2025-06-25 Thread CLEMENT MATHIEU--DRIF
On 23/06/2025 3:15 pm, Peter Xu wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Mon, Jun 23, 2025 at 05:43:06AM +, CLEMENT MATHIEU--DRIF wrote: >> Hi

Re: [PATCH 0/2] Memory and PCI definitions for emulated ATS

2025-06-23 Thread CLEMENT MATHIEU--DRIF
Hi Peter On 20/06/2025 4:35 pm, Peter Xu wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Fri, Jun 20, 2025 at 05:56:49AM +, CLEMENT MATHIEU--DRIF wrote: >&

[PATCH 0/2] Memory and PCI definitions for emulated ATS

2025-06-19 Thread CLEMENT MATHIEU--DRIF
- Global - Untranslated Only (cannot be used with 'Address type = translated') Clement Mathieu--Drif (2): pci: Add a memory attribute for pre-translated DMA operations memory: Add permissions in IOMMUAccessFlags include/exec/memattrs.h | 3 +++ include/hw/pci/pci.h| 9 +

[PATCH 2/2] memory: Add permissions in IOMMUAccessFlags

2025-06-19 Thread CLEMENT MATHIEU--DRIF
) : - Execute Requested - Privileged Mode Requested - Global - Untranslated Only IOMMU_ACCESS_FLAG sets the additional flags to 0 Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 23 +-- 1 file changed, 21 insertions(+), 2 deletions(-) diff

[PATCH 1/2] pci: Add a memory attribute for pre-translated DMA operations

2025-06-19 Thread CLEMENT MATHIEU--DRIF
The address_type bit will be set to PCI_AT_TRANSLATED by devices that use cached addresses obtained via ATS. Signed-off-by: Clement Mathieu--Drif --- include/exec/memattrs.h | 3 +++ include/hw/pci/pci.h| 9 + 2 files changed, 12 insertions(+) diff --git a/include/exec/memattrs.h b

Re: [PATCH v1 04/15] intel_iommu: Introduce a new structure VTDHostIOMMUDevice

2025-06-12 Thread CLEMENT MATHIEU--DRIF
Hi, On 06/06/2025 12:04 pm, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Introduce a new structure VTDHostIOMMUDevice which replaces > HostIOMMUDevice to be stored i

Re: [PATCH 00/11] SVM API declaration for emulated devices

2025-06-04 Thread CLEMENT MATHIEU--DRIF
Just cc'ing riscv team Thanks >cmd On 20/05/2025 9:18 am, CLEMENT MATHIEU--DRIF wrote: > This patch set belongs to a list of series that add SVM support in VT-d. > > Here we focus on introducing a common PCI-level API for ATS and PRI to be > used by virtual devices. >

[PATCH 08/11] memory: Store user data pointer in the IOMMU notifiers

2025-05-20 Thread CLEMENT MATHIEU--DRIF
This will help developers of ATS-capable devices to track a state. Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/system/memory.h b/include/system/memory.h index fbbf4cf911..fc35a0dcad 100644 --- a/include/system

[PATCH 09/11] pci: Add a pci-level initialization function for IOMMU notifiers

2025-05-20 Thread CLEMENT MATHIEU--DRIF
This is meant to be used by ATS-capable devices. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c | 17 + include/hw/pci/pci.h | 33 + 2 files changed, 50 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index fc4954ac81

[PATCH 01/11] pcie: Add helper to declare PASID capability for a pcie device

2025-05-20 Thread CLEMENT MATHIEU--DRIF
Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 25 + include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h | 5 + 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 1b12db6fa2

[PATCH 00/11] SVM API declaration for emulated devices

2025-05-20 Thread CLEMENT MATHIEU--DRIF
- PRI - Device IOTLB invalidations - Requests with already pre-translated addresses - A demo device - A simple driver for the demo device - A userspace program (for testing and demonstration purposes) https://github.com/BullSequana/Qemu-in-guest-SVM-demo Clement Mathi

[PATCH 04/11] pcie: Add a helper to declare the PRI capability for a pcie device

2025-05-20 Thread CLEMENT MATHIEU--DRIF
Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 26 ++ include/hw/pci/pcie.h | 5 - include/hw/pci/pcie_regs.h | 3 +++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 36de709801

[PATCH 10/11] pci: Add a pci-level API for ATS

2025-05-20 Thread CLEMENT MATHIEU--DRIF
Devices implementing ATS can send translation requests using pci_ats_request_translation. The invalidation events are sent back to the device using the iommu notifier managed with pci_iommu_register_iotlb_notifier / pci_iommu_unregister_iotlb_notifier. Signed-off-by: Clement Mathieu--Drif Co

[PATCH 02/11] pcie: Helper functions to check if PASID is enabled

2025-05-20 Thread CLEMENT MATHIEU--DRIF
pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 2 ++ 2 files changed, 11 insertions

[PATCH 06/11] pci: Cache the bus mastering status in the device

2025-05-20 Thread CLEMENT MATHIEU--DRIF
The cached is_master value is necessary to know if a device is allowed to issue ATS/PRI requests or not as these operations do not go through the master_enable memory region. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c| 23 +-- include/hw/pci

[PATCH 07/11] pci: Add an API to get IOMMU's min page size and virtual address width

2025-05-20 Thread CLEMENT MATHIEU--DRIF
This kind of information is needed by devices implementing ATS in order to initialize their translation cache. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c | 17 + include/hw/pci/pci.h | 26 ++ 2 files changed, 43 insertions(+) diff

[PATCH 11/11] pci: Add a PCI-level API for PRI

2025-05-20 Thread CLEMENT MATHIEU--DRIF
A device can send a PRI request to the IOMMU using pci_pri_request_page. The PRI response is sent back using the notifier managed with pci_pri_register_notifier and pci_pri_unregister_notifier. Signed-off-by: Clement Mathieu--Drif Co-authored-by: Ethan Milon --- hw/pci/pci.c | 66

[PATCH 05/11] pcie: Helper functions to check to check if PRI is enabled

2025-05-20 Thread CLEMENT MATHIEU--DRIF
pri_enabled can be used to check whether the capability is present and enabled on a PCIe device Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files changed, 10 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index

[PATCH 03/11] pcie: Helper function to check if ATS is enabled

2025-05-20 Thread CLEMENT MATHIEU--DRIF
ats_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files changed, 10 insertions

Re: [PATCH v4 14/19] atc: Add unit tests

2025-05-14 Thread CLEMENT MATHIEU--DRIF
On 14/05/2025 9:36 am, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Thu, Feb 27, 2025 at 10:54:47AM +, CLEMENT MATHIEU--DRIF wrote: &

Re: [PATCH v5 2/2] intel_iommu: Take locks when looking for and creating address spaces

2025-05-14 Thread CLEMENT MATHIEU--DRIF
On 14/05/2025 1:48 pm, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Wed, Apr 30, 2025 at 12:48:06PM +, CLEMENT MATHIEU--DRIF wrote: >

Re: [PATCH v5 0/2] intel_iommu: Fix locking issues

2025-05-05 Thread CLEMENT MATHIEU--DRIF
Cc'ing Paolo On 30/04/2025 2:48 pm, CLEMENT MATHIEU--DRIF wrote: > This series introduces 2 fixes and improves locking style > consistency in the VT-d device. > > Changes since v4: > - Re-check if the address space is present once both bql and > iommu lock ar

Re: [PATCH v4 3/3] intel_iommu: Take the VTD lock when looking for and creating address spaces

2025-04-30 Thread CLEMENT MATHIEU--DRIF
On 29/04/2025 8:01 am, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >&

[PATCH v5 2/2] intel_iommu: Take locks when looking for and creating address spaces

2025-04-30 Thread CLEMENT MATHIEU--DRIF
-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 25 - 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index dad1d9f300..144e25622a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4205,9

[PATCH v5 1/2] intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automatically

2025-04-30 Thread CLEMENT MATHIEU--DRIF
vtd_switch_address_space needs to take the BQL if not already held. Use BQL_LOCK_GUARD to make the iommu implementation more consistent. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/i386

[PATCH v5 0/2] intel_iommu: Fix locking issues

2025-04-30 Thread CLEMENT MATHIEU--DRIF
This series introduces 2 fixes and improves locking style consistency in the VT-d device. Changes since v4: - Re-check if the address space is present once both bql and iommu lock are held. Clement Mathieu--Drif (2): intel_iommu: Use BQL_LOCK_GUARD to manage cleanup

Re: [PATCH v4 3/3] intel_iommu: Take the VTD lock when looking for and creating address spaces

2025-04-28 Thread CLEMENT MATHIEU--DRIF
Hi Zhenzhong, On 28/04/2025 10:55 am, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Hi Clement, > >> -Original Message- >&g

[PATCH v4 1/3] intel_iommu: Take the bql before registering a new address space

2025-04-27 Thread CLEMENT MATHIEU--DRIF
Address space creation might end up being called without holding the bql as it is exposed through the IOMMU ops. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

[PATCH v4 2/3] intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automatically

2025-04-27 Thread CLEMENT MATHIEU--DRIF
vtd_switch_address_space needs to take the BQL if not already held. Use BQL_LOCK_GUARD to make the iommu implementation more consistent. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/i386

[PATCH v4 3/3] intel_iommu: Take the VTD lock when looking for and creating address spaces

2025-04-27 Thread CLEMENT MATHIEU--DRIF
vtd_find_add_as can be called by multiple threads which leads to a race condition on address space creation. The IOMMU lock must be taken to avoid such a race. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 28 ++-- 1 file changed, 26 insertions(+), 2

[PATCH v4 0/3] intel_iommu: Fix locking issues

2025-04-27 Thread CLEMENT MATHIEU--DRIF
This series introduces 2 fixes and improves locking style consistency in the VT-d device. Clement Mathieu--Drif (3): intel_iommu: Take the bql before registering a new address space intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automatically intel_iommu: Take the VTD lock when looking

Re: [PATCH v3 1/2] intel_iommu: Take the bql before registering a new address space

2025-04-23 Thread CLEMENT MATHIEU--DRIF
On 23/04/2025 12:06 pm, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Wed, Apr 23, 2025 at 09:15:36AM +, CLEMENT MATHIEU--DRIF wrote: &g

Re: [PATCH v3 1/2] intel_iommu: Take the bql before registering a new address space

2025-04-23 Thread CLEMENT MATHIEU--DRIF
On 23/04/2025 8:00 am, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Wed, Apr 23, 2025 at 05:38:20AM +, CLEMENT MATHIEU--DRIF wrote: &

[PATCH v3 2/2] intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automatically

2025-04-22 Thread CLEMENT MATHIEU--DRIF
vtd_switch_address_space needs to take the BQL if not already held. Use BQL_LOCK_GUARD to make the iommu implementation more consistent. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/i386

[PATCH v3 1/2] intel_iommu: Take the bql before registering a new address space

2025-04-22 Thread CLEMENT MATHIEU--DRIF
Address space creation might end up being called without holding the bql as it is exposed through the IOMMU ops. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

Re: [PATCH 09/18] amd_iommu: Add helpers to walk AMD v1 Page Table format

2025-04-17 Thread CLEMENT MATHIEU--DRIF
On 17/04/2025 5:27 pm, Alejandro Jimenez wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 4/17/25 8:40 AM, CLEMENT MATHIEU--DRIF wrote: >> >> >>

Re: [PATCH 09/18] amd_iommu: Add helpers to walk AMD v1 Page Table format

2025-04-17 Thread CLEMENT MATHIEU--DRIF
On 14/04/2025 4:02 am, Alejandro Jimenez wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > The current amdvi_page_walk() is designed to be called by the replay() > method. Rather than

Re: [PATCH] intel_iommu: Take the bql before registering a new address space

2025-04-15 Thread CLEMENT MATHIEU--DRIF
On 15/04/2025 8:53 am, Philippe Mathieu-Daudé wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 15/4/25 08:18, CLEMENT MATHIEU--DRIF wrote: >> Address space

[PATCH v2] intel_iommu: Take the bql before registering a new address space

2025-04-15 Thread CLEMENT MATHIEU--DRIF
Address space creation might end up being called without holding the bql as it is exposed through the IOMMU ops. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

Re: [PATCH] intel_iommu: Take the bql before registering a new address space

2025-04-15 Thread CLEMENT MATHIEU--DRIF
Bonzini wrote: >>> On Tue, Apr 15, 2025 at 1:51 PM CLEMENT MATHIEU--DRIF >>> wrote: >>>> On 15/04/2025 11:30 am, Paolo Bonzini wrote: >>>>> Caution: External email. Do not open attachments or click links, >>>>> unless >>>>&g

Re: [PATCH] intel_iommu: Take the bql before registering a new address space

2025-04-15 Thread CLEMENT MATHIEU--DRIF
On 15/04/2025 2:33 pm, Stefan Hajnoczi wrote: > On Tue, Apr 15, 2025 at 03:11:00AM -0400, Michael S. Tsirkin wrote: >> On Tue, Apr 15, 2025 at 06:18:08AM +, CLEMENT MATHIEU--DRIF wrote: >>> Address space creation might end up being called without holding the >>> b

Re: [PATCH] intel_iommu: Take the bql before registering a new address space

2025-04-15 Thread CLEMENT MATHIEU--DRIF
On 15/04/2025 11:30 am, Paolo Bonzini wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 4/15/25 08:18, CLEMENT MATHIEU--DRIF wrote: >> Address space creati

[PATCH] intel_iommu: Take the bql before registering a new address space

2025-04-14 Thread CLEMENT MATHIEU--DRIF
Address space creation might end up being called without holding the bql as it is exposed through the IOMMU ops. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

Re: [PATCH v3 02/16] hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET with PCH_PIC_xxx

2025-04-10 Thread CLEMENT MATHIEU--DRIF
Reviewed-by: Clement Mathieu--Drif On 09/04/2025 4:36 am, Bibo Mao wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_

Re: [PATCH v3 01/16] hw/intc/loongarch_pch: Modify name of some registers

2025-04-10 Thread CLEMENT MATHIEU--DRIF
Reviewed-by: Clement Mathieu--Drif On 09/04/2025 4:36 am, Bibo Mao wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > For some registers with width 8 bytes, its name is

Re: Giving your own patches your Reviewed-by

2025-03-12 Thread CLEMENT MATHIEU--DRIF
On 12/03/2025 13:54, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 2025/3/12 18:03, Philippe Mathieu-Daudé wrote: >> Hi Markus, >> >> (Cc'ing Yi, Clément and Zhenzhong fo

[PATCH v4 14/19] atc: Add unit tests

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests

[PATCH v4 06/19] pcie: Helper functions to check if PASID is enabled

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 2 ++ 2

[PATCH v4 03/19] memory: Allow to store the PASID in IOMMUTLBEntry

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif This will be useful for devices that support ATS and need to store entries in an ATC (device IOTLB). Signed-off-by: Clement Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h

[PATCH v4 10/19] intel_iommu: Implement the get_memory_region_pasid iommu operation

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 17 - include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a360119fbe

[PATCH v4 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw

[PATCH v4 00/19] intel_iommu: Add ATS support

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif This patch set belongs to a list of series that add SVM support for VT-d. Here we focus on implementing ATS support in the IOMMU and adding a PCI-level API to be used by virtual devices. This work is based on the VT-d specification version 4.1 (March 2023). Here is

[PATCH v4 02/19] intel_iommu: Declare supported PASID size

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif PSS field of the ecap register stores the supported PASID size minus 1. Thus, this commit adds support for 20bits PASIDs. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2

[PATCH v4 08/19] pci: Cache the bus mastering status in the device

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif The cached is_master value is necessary to know if a device is allowed to issue ATS requests or not. This behavior is implemented in an upcoming patch. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c| 25 +++-- include/hw

[PATCH v4 09/19] pci: Add IOMMU operations to get memory regions with PASID

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif The region returned by this operation will be used as the input region for ATS. Signed-off-by: Clement Mathieu--Drif --- include/hw/pci/pci.h | 16 1 file changed, 16 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index

[PATCH v4 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif PASID value must be used by devices as a key (or part of a key) when populating their ATC with the IOTLB entries returned by the IOMMU. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386

[PATCH v4 13/19] atc: Generic ATC that can be used by PCIe devices that support SVM

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clement Mathieu--Drif

[PATCH v4 16/19] pci: Add a pci-level API for ATS

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier

[PATCH v4 11/19] memory: Store user data pointer in the IOMMU notifiers

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif This will help developers of svm devices to track a state Signed-off-by: Clement Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index eee625a9c6..4d240cad1c 100644 --- a

[PATCH v4 18/19] intel_iommu: Return page walk level even when the translation fails

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed

[PATCH v4 15/19] memory: Add an API for ATS support

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. We decided not to use the existing translation operation for 2 reasons. First, ATS is

[PATCH v4 19/19] intel_iommu: Add support for ATS

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 74 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 72 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c

[PATCH v4 05/19] pcie: Add helper to declare PASID capability for a pcie device

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 24 include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h | 5 + 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci

[PATCH v4 07/19] pcie: Helper function to check if ATS is enabled

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif ats_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files

[PATCH v4 12/19] pci: Add a pci-level initialization function for iommu notifiers

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed

[PATCH v4 01/19] memory: Add permissions in IOMMUAccessFlags

2025-02-27 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added

Re: [PATCH v3 00/19] intel_iommu: Add ATS support

2025-02-21 Thread CLEMENT MATHIEU--DRIF
On 21/02/2025 11:57, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Fri, Feb 21, 2025 at 08:07:25AM +, CLEMENT MATHIEU--DRIF wrote: &

[PATCH v3 16/19] pci: Add a pci-level API for ATS

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier

[PATCH v3 07/19] pcie: Helper function to check if ATS is enabled

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif ats_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files

[PATCH v3 09/19] pci: Add IOMMU operations to get memory regions with PASID

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif The region returned by this operation will be used as the input region for ATS. Signed-off-by: Clement Mathieu--Drif --- include/hw/pci/pci.h | 16 1 file changed, 16 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index

[PATCH v3 11/19] memory: Store user data pointer in the IOMMU notifiers

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif This will help developers of svm devices to track a state Signed-off-by: Clement Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index eee625a9c6..4d240cad1c 100644 --- a

[PATCH v3 02/19] intel_iommu: Declare supported PASID size

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif PSS field of the ecap register stores the supported PASID size minus 1. Thus, this commit adds support for 20bits PASIDs. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2

[PATCH v3 15/19] memory: Add an API for ATS support

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. We decided not to use the existing translation operation for 2 reasons. First, ATS is

[PATCH v3 06/19] pcie: Helper functions to check if PASID is enabled

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 2 ++ 2

[PATCH v3 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw

[PATCH v3 18/19] intel_iommu: Return page walk level even when the translation fails

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed

[PATCH v3 08/19] pci: Cache the bus mastering status in the device

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif The cached is_master value is necessary to know if a device is allowed to issue ATS requests or not. This behavior is implemented in an upcoming patch. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c| 25 +++-- include/hw

[PATCH v3 05/19] pcie: Add helper to declare PASID capability for a pcie device

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 24 include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h | 5 + 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci

[PATCH v3 10/19] intel_iommu: Implement the get_memory_region_pasid iommu operation

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 17 - include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a360119fbe

[PATCH v3 00/19] intel_iommu: Add ATS support

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif This patch set belongs to a list of series that add SVM support for VT-d. Here we focus on implementing ATS support in the IOMMU and adding a PCI-level API to be used by virtual devices. This work is based on the VT-d specification version 4.1 (March 2023). Here is

[PATCH v3 14/19] atc: Add unit tests

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests

[PATCH v3 12/19] pci: Add a pci-level initialization function for iommu notifiers

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed

[PATCH v3 13/19] atc: Generic ATC that can be used by PCIe devices that support SVM

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clement Mathieu--Drif

[PATCH v3 19/19] intel_iommu: Add support for ATS

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 74 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 72 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c

[PATCH v3 01/19] memory: Add permissions in IOMMUAccessFlags

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added

[PATCH v3 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry

2025-02-21 Thread CLEMENT MATHIEU--DRIF
From: Clement Mathieu--Drif PASID value must be used by devices as a key (or part of a key) when populating their ATC with the IOTLB entries returned by the IOMMU. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386

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