Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Michael Kowal
>
> When the END Event Queue wraps the END EQ Generation bit is flipped and the
> Generation Flipped bit is set to one. On a END cache Watch read operation,
> the Generat
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Report access size in XIVE TM operation error logs.
>
> Signed-off-by: Nicholas Piggin
> ---
> hw/intc/xive.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
&
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Glenn Miles
>
> According to the XIVE spec, updating the CPPR should also update the
> PIPR. The final value of the PIPR depends on other factors, but it
> should never be set to a valu
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Have xive_tctx_accept clear NSR in one shot rather than masking out bits
> as they are tested, which makes it clear it's reset to 0, and does not
> have a partial NSR value in the register.
>
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Michael Kowal
>
> Writes to the Flush Control registers were logged as invalid
> when they are allowed. Clearing the unsupported want_cache_disable
> feature is supported, so don't log a
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Group interrupts should not be taken from the backlog and presented
> if they are precluded by CPPR.
>
> Fixes: 855434b3b8 ("ppc/xive2: Process group backlog when pushing an OS
> conte
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Glenn Miles
>
> The queue size of an Event Notification Descriptor (END)
> is determined by the 'cl' and QsZ fields of the END.
> If the cl field is 1, then the queue size
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Glenn Miles
>
> The current xive algorithm for finding a matching group vCPU
> target always uses the first vCPU found. And, since it always
> starts the search with thread 0 of a co
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Glenn Miles
>
> A problem was seen where uart interrupts would be lost resulting in the
> console hanging. Traces showed that a lower priority interrupt was
> preempting a higher pri
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC
> register, so don't clear it on read.
>
> Don't bother clearing the reads-as-zero CONFLICT bit because it'
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Typo, IBP should be IPB.
>
> Signed-off-by: Nicholas Piggin
> ---
> hw/intc/trace-events | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/intc/trac
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> The group interrupt delivery flow selects the group backlog scan if
> LSMFB < IPB, but that scan may find an interrupt with a priority >=
> IPB. In that case, the VP-direct interrupt should
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Rather than functions to return masks to test NSR bits, have functions
> to test those bits directly. This should be no functional change, it
> just makes the code more readable.
>
> Signed-off-by:
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> If CPPR is lowered to preclude the pending interrupt, NSR should be
> cleared and the qemu_irq should be lowered. This avoids some cases
> of supurious interrupts.
>
> Signed-off-by:
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Glenn Miles
>
> Add support for XIVE ESB Interrupt Escalation.
>
> Suggested-by: Michael Kowal
> [This change was taken from a patch provided by Michael Kowal.]
> Signed-off-by: Glenn Mi
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Michael Kowal
>
> In a multi chip environment there will be remote/forwarded VSDs. The check
> to find a matching INT controller (XIVE) of the remote block number was
> checking the I
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Test that the NSR exception bit field is equal to the pool ring value,
> rather than any common bits set, which is more correct (although there
> is no practical bug because the LSI NSR ty
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> This improves the implementation of pulling pool and phys contexts in
> XIVE1, by following closer the OS pulling code.
>
> In particular, the old ring data is returned rather than the modified,
> and
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> From: Michael Kowal
>
> This can make it easier to see what the target system is trying to
> do.
>
> [npiggin: split from larger patch]
> Signed-off-by: Michael Kowal
> ---
>
Looks good.
Reviewed-by: Caleb Schlossin
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Pushing a context and loading IPB from NVP is defined to merge ('or')
> that IPB into the TIMA IPB register. PIPR should therefore be calculated
> based on the final IPB value, not
> In this commit Write a qtest pnv-spi-seeprom-test to check the
> SPI transactions between spi controller and seeprom device.
>
> Signed-off-by: Chalapathi V
> Acked-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
Thanks,
Caleb Schlossin
Fro
> An existing QEMU SSI framework is used and SSI_BUS is created.
>
> Signed-off-by: Chalapathi V
Reviewed-by: Caleb Schlossin
Thanks,
Caleb Schlossin
From: Chalapathi V
Sent: Wednesday, June 26, 2024 4:05 AM
To: qemu-devel@nongnu.org
Cc: qemu-...@n
On 6/26/24 11:05 AM, Chalapathi V wrote:
> In this commit target specific dependency from include/hw/ppc/pnv_xscom.h
> has been removed so that pnv_xscom.h can be included outside hw/ppc.
>
> Signed-off-by: Chalapathi V
Reviewed-by: Caleb Schlossin
Thanks,
Cal
Big (SMT8) cores have a complicated function to map the core, thread ID
to pervasive topology (PIR). Fix this for power8, power9, and power10.
Signed-off-by: Caleb Schlossin
---
Version 2 fixes the PIR calculation for core, thread ID
for power10 big cores (SMT8).
include/hw/ppc/pnv_chip.h
Cedric,
I'll resend both patches, so this new patch shows up properly as [PATCH 2/2].
Thanks,
Caleb
On 2/27/24 10:15 AM, Cédric Le Goater wrote:
> Hello Caleb,
>
> On 2/27/24 15:48, Caleb Schlossin wrote:
>> Pervasive topology(PIR) calculation for core, thread ID was
&g
Pervasive topology(PIR) calculation for core, thread ID was
wrong for big cores (SMT8). Fixing for P10.
Based on: <20240123195005.8965-1-cal...@linux.vnet.ibm.com>
Signed-off-by: Caleb Schlossin
---
hw/ppc/pnv.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff
Big (SMT8) cores have a complicated function to map the core, thread ID
to pervasive topology (PIR). Fix this for power8, power9, and power10.
Signed-off-by: Caleb Schlossin
---
include/hw/ppc/pnv_chip.h | 2 +-
include/hw/ppc/pnv_core.h | 1 +
hw/ppc/pnv.c | 60
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