On 4/24/2025 4:46 AM, Philippe Mathieu-Daudé wrote:
Since the macros.h headers call GETPC(), they need to
include "accel/tcg/getpc.h", which defines it.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Brian Cain
target/hexagon/macros.h | 1 +
target/hex
fe to base the table on the
complete opcodes table.
Signed-off-by: Taylor Simpson
---
Reviewed-by: Brian Cain
Tested-by: Brian Cain
target/hexagon/genptr.c | 6 ++-
target/hexagon/README| 1 -
target/hexagon/gen_tcg_func_table.py
On 4/17/2025 11:33 AM, Matheus Tavares Bernardino wrote:
This is the new email I'll be using from now on.
Signed-off-by: Matheus Tavares Bernardino
---
Reviewed-by: Brian Cain
Tested-by: Brian Cain
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.ma
Adding Matheus, Marco -- their "quic_" email addresses might be
deactivated soon if not already.
On 4/16/2025 9:45 AM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Philippe Mathieu-Daudé
Sent: Wednesday, April 16, 2025 12:18 AM
To: Taylor Simpson ; qemu-devel@nongnu.org
C
: Brian Cain
Sent: Monday, April 7, 2025 1:27 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; matheus.bernard...@oss.qualcomm.com;
a...@rev.ng;
a...@rev.ng; marco.lie...@oss.qualcomm.com;
ltaylorsimp...@gmail.com; alex.ben...@linaro.org
On 4/16/2025 12:54 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 10:26 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
On 4/14/2025 12:04 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Monday, April 7, 2025 1:27 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; matheus.bernard...@oss.qualcomm.com; a...@rev.ng
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 6803908718..a2dcb0aa2e 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon
To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".
Signed-off-by: Brian Cain
---
target/hexagon/idef-parser/README.rst | 2 +-
target/hexagon/insn.h | 4 ++--
target/h
We should raise an exception in the event that we encounter a packet
that can't be correctly decoded, not fault.
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
The BADVA reg is referred to with the wrong identifier. The
CAUSE reg field of SSR is not yet modeled.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 766b678651
Changes since previous "misc hexagon patches" series (v2):
- changed author to match MAINTAINERS (I was fooled by the mailmap before --
so, for real this time).
Brian Cain (5):
target/hexagon: handle .new values
target/hexagon: Fix badva reference, delete CAUSE
target/hexagon: A
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 758e5fd12d..6803908718 100755
--- a/target/hexagon/hex_common.py
+++ b/target
From: Brian Cain
The BADVA reg is referred to with the wrong identifier. The
CAUSE reg field of SSR is not yet modeled.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index
76854-1-phi...@linaro.org/
Brian Cain (5):
target/hexagon: handle .new values
target/hexagon: Fix badva reference, delete CAUSE
target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof
target/hexagon: s/pkt_has_store/pkt_has_scalar_store
target/hexagon: Remove unreachable
target/hexag
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 6803908718..a2dcb0aa2e 100755
--- a/target/hexagon/hex_common.py
+++ b/target
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 758e5fd12d..6803908718 100755
--- a/target/hexagon
From: Brian Cain
To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".
Signed-off-by: Brian Cain
---
target/hexagon/idef-parser/README.rst | 2 +-
target/hexagon/insn.h | 4 ++--
From: Brian Cain
We should raise an exception in the event that we encounter a packet
that can't be correctly decoded, not fault.
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/decode.c b/t
On 3/3/2025 6:26 AM, Philippe Mathieu-Daudé wrote:
Hi Brian and Sid,
On 1/3/25 18:20, Brian Cain wrote:
From: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Co-authored-by: Damien Hedde
Signed-off-by: Brian Cain
---
MAINTAINERS | 2 +
docs/devel/hexagon
On 4/4/2025 9:33 AM, Richard Henderson wrote:
On 4/3/25 19:52, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu-param.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 45ee7b4640
On 3/26/2025 7:42 AM, 'Anton Johansson' wrote:
On 25/03/25, Brian Cain wrote:
On 3/24/2025 8:53 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Anton Johansson
Sent: Wednesday, March 12, 2025 2:46 PM
To: qemu-devel@nongnu.org
Cc: a...@rev.ng; ltaylorsimp...
On 4/4/2025 8:25 AM, Matheus Tavares Bernardino wrote:
On Thu, 3 Apr 2025 19:51:58 -0700 Brian Cain
wrote:
From: Brian Cain
Perhaps it would be best to reset the autorship here to
brian.c...@oss.qualcomm.com?
Good catch -- will do.
Signed-off-by: Brian Cain
---
target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 242dee3731..85eabc9876 100755
--- a/target/hexagon/hex_common.py
+++ b/target
While preparing the system emulation patches, these ones stuck out as
not-strictly-related to sysemu. We can review and apply them independently
of those.
Brian Cain (6):
target/hexagon: handle .new values
target/hexagon: Fix badva reference, delete CAUSE
target/hexagon: Add missing A_CALL
On 3/24/2025 9:14 PM, Taylor Simpson wrote:
I noticed that analyze_packet is marking the implicit pred reads after
marking all the writes. However, the semantics of the instrucion and
packet are to do all the reads, then do the operation, then do all the
writes.
Here is the old code
static vo
On 4/2/2025 6:42 AM, Anton Johansson wrote:
A default macOS build with xcode cli tools installed lacks the `indent`
program needed by the idef-parser postprocess step. If `indent` is
installed through homebrew it doesn't support the `-linux` flag.
Conditionally run `indent` only on linux hosts.
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 758e5fd12d..242dee3731 100755
--- a/target/hexagon
From: Brian Cain
We should raise an exception in the event that we encounter a packet
that can't be correctly decoded, not fault.
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/decode.c b/t
From: Brian Cain
The BADVA reg is referred to with the wrong identifier. The
CAUSE reg field of SSR is not yet modeled.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu-param.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 45ee7b4640..ccaf6a9d28 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
From: Brian Cain
To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".
Signed-off-by: Brian Cain
---
target/hexagon/idef-parser/README.rst | 2 +-
target/hexagon/insn.h | 4 ++--
On 4/3/2025 10:49 AM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
Reviewed-by: Brian Cain
target/hexagon/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 766b678651..59fc9ed698 100644
--- a/target
`
and replace the script with a meson custom_target.
Signed-off-by: Anton Johansson
---
Reviewed-by: Brian Cain
target/hexagon/idef-parser/prepare | 24
target/hexagon/meson.build | 3 ++-
2 files changed, 2 insertions(+), 25 deletions(-)
delete mode
On 4/2/2025 6:42 AM, Anton Johansson wrote:
indent on macOS, installed via homebrew, doesn't support -linux. Only
run indent on linux hosts.
Signed-off-by: Anton Johansson
---
Reviewed-by: Brian Cain
target/hexagon/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 del
On 3/19/2025 2:50 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 11:28 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
On 3/17/2025 1:43 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 11:28 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
On 3/3/2025 6:26 AM, Philippe Mathieu-Daudé wrote:
Hi Brian and Sid,
On 1/3/25 18:20, Brian Cain wrote:
From: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Co-authored-by: Damien Hedde
Signed-off-by: Brian Cain
---
MAINTAINERS | 2 +
docs/devel/hexagon
On 3/24/2025 2:40 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Saturday, March 1, 2025 11:21 AM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
.
Signed-off-by: Taylor Simpson
---
I found no regressions when testing this patch downstream. I agree that
this reordering makes sense regardless of whether we can find a test
that fails now.
Reviewed-by: Brian Cain
Tested-by: Brian Cain
target/hexagon/translate.c | 18 +++
On 3/24/2025 8:53 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Anton Johansson
Sent: Wednesday, March 12, 2025 2:46 PM
To: qemu-devel@nongnu.org
Cc: a...@rev.ng; ltaylorsimp...@gmail.com; brian.c...@oss.qualcomm.com;
phi...@linaro.org
Subject: [PATCH 2/2] target/hexag
On 3/18/2025 2:14 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Sid Manning
Sent: Tuesday, March 18, 2025 1:34 PM
To: ltaylorsimp...@gmail.com; 'Brian Cain'
; qemu-devel@nongnu.org
Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
On 3/12/2025 2:19 PM, Philippe Mathieu-Daudé wrote:
On 1/3/25 06:26, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 36a93cc22f..2b6a707fca
On 3/5/2025 3:21 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Wednesday, March 5, 2025 2:13 PM
To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org
Cc: richard.hender...@linaro.org; phi...@linaro.org;
quic_mathb...@quicinc.com; a...@rev.ng; a
On 3/5/2025 1:36 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 11:26 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
On 3/4/2025 6:51 AM, Peter Maydell wrote:
On Tue, 4 Mar 2025 at 11:56, Alex Bennée wrote:
Peter Maydell writes:
+# GCC versions 12/13/14/15 at least incorrectly complain about
+# "'SHA1Transform' reading 64 bytes from a region of size 0"; see the gcc bug
+# https://gcc.gnu.org/bugzilla/show
On 3/5/2025 2:37 AM, Benjamin Charlton wrote:
Hello.
Sorry to bother you, I am very new to all of this and but I am looking
for a ia64 emulator, sadly it has to be this to run a piece of old
software. GPT suggested I clone your project and emulate this
processor. However I am receiving an e
On 3/5/2025 2:05 AM, Thomas Huth wrote:
On 04/03/2025 16.46, Philippe Mathieu-Daudé wrote:
Hi Brian,
On 1/3/25 18:20, Brian Cain wrote:
From: Brian Cain
A bit opaque...
Signed-off-by: Brian Cain
---
MAINTAINERS | 1 +
tests/functional/meson.build
On 3/4/2025 10:15 AM, Brian Cain wrote:
On 3/4/2025 9:46 AM, Philippe Mathieu-Daudé wrote:
Hi Brian,
On 1/3/25 18:20, Brian Cain wrote:
From: Brian Cain
A bit opaque...
Whoops -- will fix it.
Signed-off-by: Brian Cain
---
MAINTAINERS | 1 +
tests
On 3/4/2025 9:46 AM, Philippe Mathieu-Daudé wrote:
Hi Brian,
On 1/3/25 18:20, Brian Cain wrote:
From: Brian Cain
A bit opaque...
Whoops -- will fix it.
Signed-off-by: Brian Cain
---
MAINTAINERS | 1 +
tests/functional/meson.build | 8
On 3/4/2025 9:46 AM, Philippe Mathieu-Daudé wrote:
Hi Brian,
On 1/3/25 18:20, Brian Cain wrote:
From: Brian Cain
A bit opaque...
Whoops -- will fix it.
Signed-off-by: Brian Cain
---
MAINTAINERS | 1 +
tests/functional/meson.build | 8
On 3/4/2025 12:27 AM, Markus Armbruster wrote:
Brian Cain writes:
From: Brian Cain
Co-authored-by: Mike Lambert
Co-authored-by: Sid Manning
Signed-off-by: Brian Cain
[...]
diff --git a/qapi/machine.json b/qapi/machine.json
index a6b8795b09..a7070bad4d 100644
--- a/qapi/machine.json
On 2/28/2025 11:28 PM, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/sys_macros.h | 8 +--
target/hexagon/op_helper.c | 104
2 files changed, 108 insertions(+), 4 deletions(-)
diff --git a/target/hexagon
From: Brian Cain
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h | 6 ++
target/hexagon/internal.h | 4 ++
target/hexagon/cpu.c | 17 ++
target/hexagon/gdbstub.c | 45 ++
target/hexagon/op_helper.c | 16
From: Brian Cain
Also: add nop TCG overrides for break,unpause,fetchbo,dczeroa
break: this hardware breakpoint instruction is used with the in-silicon
debugger feature, this is not modeled.
unpause: this instruction is used to resume hardware threads that are
stalled by pause instructions
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/attribs_def.h.inc | 414 +++--
target/hexagon/imported/macros.def | 558 +
2 files changed, 942 insertions(+), 30 deletions(-)
mode change 100755 => 100644 target/hexagon/impor
From: Brian Cain
siad is the 'Set interrupt auto disable' instruction.
Signed-off-by: Brian Cain
---
target/hexagon/op_helper.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 687e7f45c2..
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 2 ++
target/hexagon/gen_tcg_funcs.py | 32 +++-
2 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index ff596e2a94
From: Brian Cain
{TLB,k0}lock counts are used to represent the TLB, k0 locks among
hardware threads.
wait_next_pc represents the program counter to set when resuming from
a wait-for-interrupts state.
cause_code contains the precise exception cause.This will be used by
subsequent commits
Signed-off-by: Brian Cain
Signed-off-by: Matheus Tavares Bernardino
---
target/hexagon/cpu.c| 10 +++---
target/hexagon/cpu_helper.c | 17 ++---
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 80f5e23794
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 1e94e1fef5..7b5bb2cd46 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon
From: Brian Cain
The hardware-assisted scheduler helps manage tasks on the run queue
and interrupt steering.
This instruction is defined in the Qualcomm Hexagon V71 Programmer's Reference
Manual -
https://docs.qualcomm.com/bundle/publicresource/80-
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h | 1 +
target/hexagon/cpu.c | 7 ++-
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index baa48ec051..4667a1f748 100644
--- a/target/hexagon/cpu.h
+++ b/target
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/translate.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index d4b22acb72..ff881d1060 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon
From: Brian Cain
Define the register fields for ssr, schedcfg, stid, bestwait, ccr,
modectl, imask, ipendad.
Define the fields for TLB entries.
Signed-off-by: Brian Cain
---
target/hexagon/reg_fields_def.h.inc | 96 +
1 file changed, 96 insertions(+)
diff --git a
From: Sid Manning
Signed-off-by: Sid Manning
---
target/hexagon/cpu.h | 1 +
hw/hexagon/hexagon_dsp.c | 10 ++
target/hexagon/cpu.c | 6 ++
3 files changed, 17 insertions(+)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 73c3bb34b0..0608d3265c 100644
--- a
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu_helper.h | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
index e8d89d8526..1cdf4f8dd0 100644
--- a/target/hexagon/cpu_helper.h
+++ b
Signed-off-by: Brian Cain
---
MAINTAINERS | 1 +
configs/devices/hexagon-softmmu/default.mak | 7 +++
configs/targets/hexagon-softmmu.mak | 6 ++
target/Kconfig | 1 +
target/hexagon/Kconfig | 2
From: Brian Cain
Signed-off-by: Brian Cain
---
configs/devices/hexagon-softmmu/default.mak | 1 +
configs/targets/hexagon-softmmu.mak | 1 +
include/hw/hexagon/virt.h | 41 ++
hw/hexagon/virt.c | 395
target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
MAINTAINERS | 1 +
tests/functional/meson.build| 8 +
tests/functional/test_hexagon_minivm.py | 42 +
3 files changed, 51 insertions(+)
create mode 100755 tests/functional
uction set simulator included with
the Hexagon SDK. These programs generally depend on semihosting
support, which will come later.
Brian Cain (6):
hw/hexagon: Add machine configs for sysemu
hw/hexagon: Add v68, sa8775-cdsp0 defs
hw/hexagon: Modify "Standalone" symbols
target/hexag
From: Brian Cain
Signed-off-by: Brian Cain
---
hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc | 64 ++
hw/hexagon/machine_cfg_v68n_1024.h.inc| 65 +++
2 files changed, 129 insertions(+)
create mode 100644 hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc
create
From: Brian Cain
These symbols are used by Hexagon Standalone OS to indicate whether
the program should halt and wait for interrupts at startup. For QEMU,
we want these programs to just continue crt0 startup through to the user
program's main().
Signed-off-by: Brian Cain
---
hw/he
From: Brian Cain
Co-authored-by: Mike Lambert
Co-authored-by: Sid Manning
Signed-off-by: Brian Cain
---
MAINTAINERS| 2 +
qapi/machine.json | 2 +-
include/hw/hexagon/hexagon.h | 151 +
hw/hexagon
From: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Co-authored-by: Damien Hedde
Signed-off-by: Brian Cain
---
MAINTAINERS| 2 +
docs/devel/hexagon-l2vic.rst | 59 +
docs/devel/index-internals.rst | 1 +
include/hw/intc/l2vic.h| 37 +++
hw
From: Brian Cain
Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}).
Signed-off-by: Brian Cain
---
target/hexagon/cpu_helper.h | 32
target/hexagon/gen_tcg_sys.h | 41
target/hexagon/helper.h | 1 +
target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index db50defeb6..7fb11a0819 100755
--- a/target/hexagon/hex_common.py
+++ b/target
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/gen_analyze_funcs.py | 21 +++-
target/hexagon/hex_common.py| 163
2 files changed, 181 insertions(+), 3 deletions(-)
diff --git a/target/hexagon/gen_analyze_funcs.py
b/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/helper.h| 3 +++
target/hexagon/op_helper.c | 20
2 files changed, 23 insertions(+)
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 730eaf8b9a..3df663baeb 100644
--- a/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/macros.h | 2 +
target/hexagon/hex_common.py | 15 +-
target/hexagon/imported/encode_pp.def | 213 +++--
target/hexagon/imported/system.idef | 262 +++---
4 files
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h | 8
target/hexagon/cpu.c | 17 +
2 files changed, 25 insertions(+)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 20ea0adcca..b7789a3c90 100644
--- a/target/hexagon/cpu.h
+++ b
From: Brian Cain
This commit provides handlers to generate TCG for guest and system
register reads and writes. They will be leveraged by a future commit.
Signed-off-by: Brian Cain
---
target/hexagon/genptr.c | 159
1 file changed, 159 insertions
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu_helper.h | 1 +
target/hexagon/cpu_helper.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
index e0c0c037a6..6f0c6697ad 100644
--- a/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_mmu.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c
index d2297c036d..07ad8e9616 100644
--- a/target/hexagon/hex_mmu.c
+++ b
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/translate.h | 36
1 file changed, 36 insertions(+)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index f611c854dc..0eaa3db03e 100644
--- a/target/hexagon/translate.h
+++ b
From: Brian Cain
Co-authored-by: Sid Manning
Signed-off-by: Brian Cain
---
target/hexagon/cpu_helper.h | 8 +++
target/hexagon/cpu.c| 1 +
target/hexagon/cpu_helper.c | 37
target/hexagon/op_helper.c | 114 ++--
4 files changed, 156
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h| 1 +
target/hexagon/cpu_helper.h | 1 +
target/hexagon/cpu_helper.c | 37 +
target/hexagon/op_helper.c | 3 ++-
4 files changed, 41 insertions(+), 1 deletion(-)
diff --git a
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/translate.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index ff881d1060..248ed60f29 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon
From: Brian Cain
The PCYCLE register can be enabled to indicate accumulated clock cycles.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h | 3 ++-
target/hexagon/cpu.c | 3 +++
target/hexagon/machine.c | 25 -
3 files changed, 29 insertions(+), 2 deletions
Hexagon Virtual Machine Specification.
[1] https://github.com/quic/hexagonMVM
Brian Cain (38):
docs: Add hexagon sysemu docs
docs/system: Add hexagon CPU emulation
target/hexagon: Add System/Guest register definitions
target/hexagon: Make gen_exception_end_tb non-static
target/hexagon: Switc
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h | 37 +++--
target/hexagon/cpu.c | 6 ++
target/hexagon/machine.c | 4
3 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/gen_helper_funcs.py | 23 ++-
target/hexagon/gen_helper_protos.py | 23 ---
target/hexagon/gen_idef_parser_funcs.py | 2 ++
target/hexagon/gen_op_attribs.py| 2 +-
target
this series.
Brian Cain (38):
target/hexagon: Implement ciad helper
target/hexagon: Implement {c,}swi helpers
target/hexagon: Implement iassign{r,w} helpers
target/hexagon: Implement start/stop helpers
target/hexagon: Implement modify SSR
target/hexagon: Implement {g,s}etimask helpers
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu_helper.h | 2 ++
target/hexagon/cpu_helper.c | 8
2 files changed, 10 insertions(+)
diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
index 5f5f15149a..e0c0c037a6 100644
--- a/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/translate.h | 1 +
target/hexagon/translate.c | 99 +-
2 files changed, 99 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 9bc4b3ce8b
From: Brian Cain
iassign{r,w} are the "Interrupt to thread assignment {read,write}"
instructions.
Signed-off-by: Brian Cain
---
target/hexagon/op_helper.c | 48 --
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/op_
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/op_helper.c | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 9f79b1a20c..83088cfaa3 100644
--- a/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/internal.h | 5 +
target/hexagon/op_helper.c | 20
2 files changed, 25 insertions(+)
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index 9658141316..7cf7bcaa6c 100644
--- a/target
From: Brian Cain
{c,}swi are the "software interrupt"/"Cancel pending interrupts" instructions.
Signed-off-by: Brian Cain
---
target/hexagon/op_helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/op_helper.c b/target/hexag
From: Brian Cain
ciad is the clear interrupt auto disable instruction.
This instruction is defined in the Qualcomm Hexagon V71 Programmer's Reference
Manual -
https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf
See §11.9.2 S
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