Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

PR for the spec fix, in case anyone is interested. Found a couple of other references to Smcsrind that I also removed. https://github.com/riscv/riscv-control-transfer-records/pull/29 On Tue, Jun 4, 2024 at 8:41 PM Beeman Strong wrote: > Ah, good catch. We removed that dependency late. I

Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.

on for VU-mode. > > If there is any misunderstanding, please let me know. Also Sstateen0 does > not involve in CTR. Am I correct? > That all looks correct. sctrdepth gets that special treatment in VS-mode (bold and underlined above) because it is expected that a hypervisor will wis

Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

hapter 1 states that: > Smctr depends on the Smcsrind extension, while Ssctr depends on the > Sscsrind extension. Further, both Smctr and Ssctr depend upon > implementation of S-mode. > Beeman Strong 於 2024/6/5 上午 06:32 寫道: > > There is no dependency on Smcsrind, only Sscsrind. >

Re: [PATCH 0/6] target/riscv: Add support for Control Transfer Records Ext.

There is no dependency on Smcsrind, only Sscsrind. On Tue, Jun 4, 2024 at 12:29 AM Jason Chien wrote: > Smctr depends on the Smcsrind extension, Ssctr depends on the Sscsrind > extension, and both Smctr and Ssctr depend upon implementation of S-mode. > There should be a dependency check in riscv

Re: [PATCH 5/6] target/riscv: Add CTR sctrclr instruction.

On Tue, Jun 4, 2024 at 10:19 AM Jason Chien wrote: > > Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: > > CTR extension adds a new instruction sctrclr to quickly > > clear the recorded entries buffer. > > > > Signed-off-by: Rajnesh Kanwal > > --- > > target/riscv/cpu.h |