[PATCH v2 1/2] target/i386: Add TSA attack variants TSA-SQ and TSA-L1

: Babu Moger --- v2: Split the patches into two. Not adding the feature bit in CPU model now. Users can add the feature bits by using the option "-cpu EPYC-Genoa,+tsa-sq-no,+tsa-l1-no". v1: https://lore.kernel.org/qemu-devel/20250709104956.GAaG5JVO-74EF96hHO@fat_crate.local/ --- t

[PATCH v2 2/2] target/i386: Add TSA feature flag verw-clear

: Borislav Petkov (AMD) Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Babu Moger --- v2: Split the patches into two. Not adding the feature bit in CPU model now. Users can add the feature bits by using the option "-cpu EPYC-Genoa,+verw-clear". v1: https://lore.kernel.org/

[PATCH v7 3/6] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3f64293ba5..98fad3a2f9 100644 --- a/target/i386/cpu.c

[PATCH v7 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

m/ v3: https://lore.kernel.org/kvm/cover.1729807947.git.babu.mo...@amd.com/ v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (6): target/i386: Update EPYC CPU model for Cache prope

[PATCH v7 5/6] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH v7 4/6] target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX

. WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing. Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 4 ++-- target/i386

[PATCH v7 2/6] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 49d3ae8aac..3f64293ba5 100644 --- a/target/i386/cpu.c +++ b

[PATCH v7 6/6] target/i386: Add support for EPYC-Turin model

-overflow-whitepaper.pdf Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- target/i386/cpu.c | 138 ++ 1 file changed, 138 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8384ad6eff..247dcdbc34 100644 --- a/target/i386/cpu.c

[PATCH v7 1/6] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6f21d5ed22..49d3ae8aac 100644 --- a/target/i386/cpu.c

[PATCH v6 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

bu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (6): target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits target/i386: U

[PATCH v6 6/6] target/i386: Add support for EPYC-Turin model

vulnerable to SRSO at the user-kernel boundary Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Signed-off-by: Babu Moger

[PATCH v6 5/6] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH v6 2/6] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7908b90b77..be8dcf9739 100644 --- a/target/i386/cpu.c +++ b

[PATCH v6 1/6] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 72ab147e85..7908b90b77 100644 --- a/target/i386/cpu.c

[PATCH v6 4/6] target/i386: Add feature that indicates WRMSR to BASE reg is non-serializing

/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b

[PATCH v6 3/6] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index be8dcf9739..a5427620d0 100644 --- a/target/i386/cpu.c

[PATCH v5 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

ps://lore.kernel.org/kvm/cover.1729807947.git.babu.mo...@amd.com/ v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (6): target/i386: Update EPYC CPU model for Cache property, RAS,

[PATCH v5 4/6] target/i386: Add feature that indicates WRMSR to BASE reg is non-serializing

/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index

[PATCH v5 5/6] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 710b862eec..3b6a6

[PATCH v5 6/6] target/i386: Add support for EPYC-Turin model

vulnerable to SRSO at the user-kernel boundary Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Signed-off-by: Babu Moger

[PATCH v5 2/6] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 94292bfaa2..e2c3c797ed 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c

[PATCH v5 1/6] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b5dd60d281..94292bfaa2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c

[PATCH v5 3/6] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e2c3c797ed..7d18557877 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c

[PATCH v4 1/5] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 58c96eafea..a632c8030c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2181,6 +2181,60 @@ static

[PATCH v4 0/5] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature bits

t.babu.mo...@amd.com/ v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (5): target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPY

[PATCH v4 2/5] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

-off-by: Babu Moger --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a632c8030c..c21b232e75 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2343,6 +2343,60 @@ static

[PATCH v4 5/5] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- target/i386/cpu.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 107ecd2bde..1d241fcd13 100644 --- a/target/i386/

[PATCH v4 3/5] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c21b232e75..4a4e9b81d8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2505,6 +2505,60

[PATCH v4 4/5] target/i386: Add feature that indicates WRMSR to BASE reg is non-serializing

/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4a4e9b81d8..107ecd2bde

[PATCH v3 6/7] target/i386: Expose new feature bits in CPUID 8000_0021_EAX/EBX

-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger --- v3: New patch --- target/i386/cpu.c | 11 +-- target/i386/cpu.h | 9 + 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 642e71b636..5bfa07adbf 100644

[PATCH v3 2/7] target/i386: Add RAS feature bits on EPYC CPU models

interrupts. McaOverflowRecov: MCA overflow recovery support. Reviewed-by: Zhao Liu Signed-off-by: Babu Moger --- v3: No changes v2: Added reviewed by from Zhao. --- target/i386/cpu.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/target/i386/cpu.c b/target/i386

[PATCH v3 7/7] target/i386: Add support for EPYC-Turin model

RAP Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Signed-off-by: Babu Moger --- v3: Removed Zhao's Reviewed-by a

[PATCH v3 3/7] target/i386: Add PerfMonV2 feature bit

determine the number of available counters for different PMUs. It also denotes the availability of global control and status registers. Add the required CPUID feature word and feature bit to allow guests to make use of the PerfMonV2 features. Signed-off-by: Sandipan Das Signed-off-by: Babu Moger

[PATCH v3 0/7] target/i386: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

#x27; of https://repo.or.cz/qemu/kevin into staging") v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (6): target/i386: Fix minor typo in NO_NESTED_DATA_BP feature bit target/i

[PATCH v3 5/7] target/i386: Expose bits related to SRSO vulnerability

-references/57238.zip Signed-off-by: Babu Moger --- v3: New patch --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 14 +++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 690efd4085..642e71b636 100644 --- a/target/i386/cpu.c +++ b

[PATCH v3 4/7] target/i386: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa

3.41. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Zhao Liu Signed-off-by: Babu Moger --- v3: No changes v2: Minor typo. Added Reviewed-by from Zhao. --- target/i386/cpu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/i386/cpu.c b/target

[PATCH v3 1/7] target/i386: Fix minor typo in NO_NESTED_DATA_BP feature bit

Rename CPUID_8000_0021_EAX_No_NESTED_DATA_BP to CPUID_8000_0021_EAX_NO_NESTED_DATA_BP. No functional change intended. Signed-off-by: Babu Moger --- v3: New patch. --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a

[PATCH v2 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

of 6d00c6f98256 ("Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging") v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ -- 2.34.1 Babu Moger (3): i386/cpu: Add RAS feature bits on EPYC CPU models i386/cpu: Enabl

[PATCH v2 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models

interrupts. McaOverflowRecov: MCA overflow recovery support. Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v2: Just added reviewed by from Zhao. --- target/i386/cpu.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH v2 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa

3.41. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v2: Minor typo. Added Reviewed-by from Zhao. --- target/i386/cpu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH v2 2/4] i386/cpu: Add PerfMonV2 feature bit

determine the number of available counters for different PMUs. It also denotes the availability of global control and status registers. Add the required CPUID feature word and feature bit to allow guests to make use of the PerfMonV2 features. Signed-off-by: Sandipan Das Signed-off-by: Babu Moger

[PATCH v2 4/4] i386/cpu: Add support for EPYC-Turin model

avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair of Mask Register avx-vnni : AVX VNNI Instruction Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v2: Fixed minor typo. Added Zhao's Reviewed-by. --- target/i386/cpu.c

[PATCH 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model

This series adds the support for following features in qemu. 1. RAS feature bits (SUCCOR, McaOverflowRecov) 2. perfmon-v2 3. Update EPYC-Genoa to support perfmon-v2 and RAS bits 4. Add support for EPYC-Turin Babu Moger (3): i386/cpu: Add RAS feature bits on EPYC CPU models i386/cpu: Enable

[PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa

3.41. Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- target/i386/cpu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f1837cdc9..64e6dc62e2 100644 --- a/target/i386/cpu.c +++ b/target/i386/

[PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models

interrupts. McaOverflowRecov: MCA overflow recovery support. Signed-off-by: Babu Moger --- target/i386/cpu.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 165b982c8c..86a90b1405 100644 --- a/target/i386/cpu.c +++ b

[PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit

determine the number of available counters for different PMUs. It also denotes the availability of global control and status registers. Add the required CPUID feature word and feature bit to allow guests to make use of the PerfMonV2 features. Signed-off-by: Sandipan Das Signed-off-by: Babu Moger

[PATCH 4/4] i386/cpu: Add support for EPYC-Turin model

avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair of Mask Register avx-vnni : AVX VNNI Instruction Signed-off-by: Babu Moger --- target/i386/cpu.c | 131 ++ 1 file changed, 131 insertions(+) diff --git a/target

[PATCH v3] target/i386: Fix CPUID encoding of Fn8000001E_ECX

01E for AMD") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Reviewed-by: Zhao Liu Signed-off-by: Babu Moger --- v3: Rebased to the latest tree. Updated the pc_compat_9_0 for the new flag. v2: https://lore.kernel.org/kvm/20240102231738.46553-1-babu.mo...@amd.com/ Rebased to t

[PATCH v2] target/i386: Fix CPUID encoding of Fn8000001E_ECX

01E for AMD") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- v2: Rebased to the latest tree. Updated the pc_compat_8_2 for the new flag. Added the comment for new property legacy_multi_node. Added Rev

[PATCH] target/i386: Fix CPUID encoding of Fn8000001E_ECX

01E for AMD") Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- hw/i386/pc.c | 4 +++- target/i386/cpu.c | 18 ++ target/i386/cpu.h | 1 + 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 1

[PATCH v4 3/7] target/i386: Add a couple of feature bits in 8000_0008_EBX

s on. The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://w

[PATCH v4 5/7] target/i386: Add missing feature bits in EPYC-Milan model

G c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/documents/securit

[PATCH v4 4/7] target/i386: Add feature bits for CPUID_Fn80000021_EAX

2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf --- target/i386/cpu.c | 24 target/i386/cpu.h | 8 2 files changed

[PATCH v4 6/7] target/i386: Add VNMI and automatic IBRS feature bits

chitecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Santosh Shukla Signed-off-by: Kim Phillips Signed-off-by: Babu Moger Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/file

[PATCH v4 7/7] target/i386: Add EPYC-Genoa model to support Zen 4 processor series

is a "set-and-forget" feature that means that, unlike e.g., s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. Signed-off-by: Babu Moger --- target/i3

[PATCH v4 0/7] Add EPYC-Genoa model and update previous EPYC Models

LR_BASE to match the kernel name. https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phill...@amd.com/ v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/ v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.mo...@amd.com/ v3: https://lore.kernel.

[PATCH v4 2/7] target/i386: Add new EPYC CPU versions with updated cache_info

lse in the future. Setting this bit will also cause CPUID validation failures when running SEV-SNP guests. Signed-off-by: Michael Roth Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin --- target/i386/cpu.c | 118 ++ 1 file changed, 118 insertion

[PATCH v4 1/7] target/i386: allow versioned CPUs to specify new cache_info

Definition", to allow new cache_info pointers to be specified for a new CPU version. Co-developed-by: Wei Huang Signed-off-by: Wei Huang Signed-off-by: Michael Roth Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin --- target/i386/cpu.c | 35 ---

[PATCH v3 0/7] Add EPYC-Genoa model and update previous EPYC Models

ARS_BASE to NULL_SEL_CLR_BASE to match the kernel name. https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phill...@amd.com/ v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/ v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.mo...@amd.com

[PATCH v3 4/7] target/i386: Add feature bits for CPUID_Fn80000021_EAX

2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf --- target/i386/cpu.c | 24 target/i386/cpu.h | 8 2 files changed

[PATCH v3 6/7] target/i386: Add VNMI and automatic IBRS feature bits

chitecture Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Santosh Shukla Signed-off-by: Kim Phillips Signed-off-by: Babu Moger Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/file

[PATCH v3 5/7] target/i386: Add missing feature bits in EPYC-Milan model

Programmer’s Manual Volumes 1–5 Publication No. Revision 40332 4.05 Date October 2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store

[PATCH v3 2/7] target/i386: Add new EPYC CPU versions with updated cache_info

lse in the future. Setting this bit will also cause CPUID validation failures when running SEV-SNP guests. Signed-off-by: Michael Roth Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin --- target/i386/cpu.c | 118 ++ 1 file changed, 118 insertion

[PATCH v3 7/7] target/i386: Add EPYC-Genoa model to support Zen 4 processor series

is a "set-and-forget" feature that means that, unlike e.g., s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. Signed-off-by: Babu Moger --- target/i3

[PATCH v3 1/7] target/i386: allow versioned CPUs to specify new cache_info

to be specified for a new CPU version. Co-developed-by: Wei Huang Signed-off-by: Wei Huang Signed-off-by: Michael Roth Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin --- target/i386/cpu.c | 36 +--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --

[PATCH v3 3/7] target/i386: Add a couple of feature bits in 8000_0008_EBX

s on. The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://w

[PATCH 0/5] Update AMD EPYC CPU Models

This series adds following changes. a. Allow versioned CPUs to specify new cache_info pointers. b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the cache_info.complex_indexing. c. Introduce EPYC-Milan-v2 by adding few missing feature bits. --- Babu Moger (3): target/i386: Add a

[PATCH 3/5] target/i386: Add a couple of feature bits in 8000_0008_EBX

tive-store-forwarding.pdf Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Signed-off-by: Babu Moger --- target/i386/cpu.c |4 ++-- target/i386/cpu.h |4 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index

[PATCH 4/5] target/i386: Add feature bits for CPUID_Fn80000021_EAX

2022 Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf Signed-off-by: Babu Moger --- target/i386/cpu.c | 24 target/i386/cpu.h |8 2 files changed, 32 insertions(+) diff

[PATCH 2/5] target/i386: Add new EPYC CPU versions with updated cache_info

lse in the future. Setting this bit will also cause CPUID validation failures when running SEV-SNP guests. Signed-off-by: Michael Roth Signed-off-by: Babu Moger --- target/i386/cpu.c | 118 + 1 file changed, 118 insertions(+) diff --git a/t

[PATCH 1/5] target/i386: allow versioned CPUs to specify new cache_info

to be specified for a new CPU version. Co-developed-by: Wei Huang Signed-off-by: Wei Huang Signed-off-by: Michael Roth Signed-off-by: Babu Moger --- target/i386/cpu.c | 36 +--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/t

[PATCH 5/5] target/i386: Add missing feature bits in EPYC-Milan model

/TechDocs/40332_4.05.pdf Signed-off-by: Babu Moger --- target/i386/cpu.c | 70 + 1 file changed, 70 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e9175da92f..54549a5127 100644 --- a/target/i386/cpu.c +++ b/target/i386

Re: [RFC PATCH 1/1] i386: Remove features from Epyc-Milan cpu

6:08 AM Daniel P. Berrangé >>> wrote: >>>> CC'ing Babu Moger who aded the Milan CPU model. >>>> >>>> On Sat, Jan 29, 2022 at 07:23:37AM -0300, Leonardo Bras wrote: >>>>> While trying to bring a VM with EPYC-Milan cpu on a host with >>&g

Re: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM

David, Are you still working on v2 of these series? I was going to test and review. Thanks > -Original Message- > From: David Edmondson > Sent: Tuesday, June 8, 2021 3:25 AM > To: qemu-devel@nongnu.org > Cc: k...@vger.kernel.org; Eduardo Habkost ; Paolo > Bonzini ; Marcelo Tosatti ; > Ric

Re: [PATCH] target/i386: Fix cpuid level for AMD

On 6/29/21 9:06 AM, Dr. David Alan Gilbert wrote: > * zhenwei pi (pizhen...@bytedance.com) wrote: >> A AMD server typically has cpuid level 0x10(test on Rome/Milan), it >> should not be changed to 0x1f in multi-dies case. >> >> Fixes: a94e1428991 (target/i386: Add CPUID.1F generation support >>

Re: constant_tsc support for SVM guest

Hi Wei, I dont know the background of this feature. I will let some else to comment on that. The patch exposes the feature TscInvariant to the guest successfully. Tested it on my AMD box. I have few comments on your patch below. On 4/23/21 12:32 AM, Wei Huang wrote: > There was a customer reques

RE: [PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome model

86: Add missing cpu feature bits in EPYC-Rome > model > > On Wed, Mar 3, 2021 at 5:24 PM wrote: > > > > On Wednesday, 2021-03-03 at 09:45:30 -06, Babu Moger wrote: > > > > > Found the following cpu feature bits missing from EPYC-Rome model. > > > ibrs

[Bug 1915063] Re: Windows 10 wil not install using qemu-system-x86_64

@Christian, Yes. This following patch fixes the problem https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg01020.html I saw your ping on the patch. I am not sure why it is not picked up. I am going ping them today. >If I might ask - how does the kernel fix you referenced interact with th

[Bug 1915063] Re: Windows 10 wil not install using qemu-system-x86_64

I remember seeing something similar before. This was supposed to be fixed by the linux kernel commit. commit 841c2be09fe4f495fe5224952a419bd8c7e5b455 Author: Maxim Levitsky Date: Wed Jul 8 14:57:31 2020 +0300 kvm: x86: replace kvm_spec_ctrl_test_value with runtime test on the host # git descr

[PATCH v2] i386: Add missing cpu feature bits in EPYC-Rome model

machine type) x86 EPYC-Rome-v1 AMD EPYC-Rome Processor x86 EPYC-Rome-v2 AMD EPYC-Rome Processor Reported-by: Pankaj Gupta Signed-off-by: Babu Moger Signed-off-by: Pankaj Gupta --- v2: Model-id remains same between EPYC-Rome-v1 and EPYC-Rome-v2. Removed model-id in the patch

Re: [PATCH] i386: Add missing cpu feature bits in EPYC-Rome model

On 3/3/21 3:42 AM, David Edmondson wrote: > On Tuesday, 2021-03-02 at 15:20:00 -06, Babu Moger wrote: > >> Found the following cpu feature bits missing from EPYC-Rome model. >> ibrs: Indirect Branch Restricted Speculation >> ssbd: Speculative Store Bypass

[PATCH] i386: Add missing cpu feature bits in EPYC-Rome model

machine type) x86 EPYC-Rome-v1 AMD EPYC-Rome Processor x86 EPYC-Rome-v2 AMD EPYC-Rome Processor Reported-by: Pankaj Gupta Signed-off-by: Babu Moger Signed-off-by: Pankaj Gupta --- target/i386/cpu.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target

Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

issue at my end, Sorry! for the confusion. > Can you please post the official patch for inclusion. > > Best regards, > Pankaj > > On Mon, Mar 1, 2021 at 9:38 PM Babu Moger wrote: >> >> >> >>> -Original Message- >>> From: Pankaj Gupt

RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

> -Original Message- > From: Pankaj Gupta > Sent: Monday, March 1, 2021 2:22 PM > To: Moger, Babu > Cc: Pankaj Gupta ; Paolo Bonzini > ; richard.hender...@linaro.org; Eduardo Habkost > ; Qemu Developers > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation > proc

RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

Pankaj, > -Original Message- > From: Pankaj Gupta > Sent: Monday, March 1, 2021 10:46 AM > To: Pankaj Gupta > Cc: Moger, Babu ; Paolo Bonzini > ; richard.hender...@linaro.org; Eduardo Habkost > ; Qemu Developers > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation

RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

Hi Pankaj, > -Original Message- > From: Pankaj Gupta > Sent: Wednesday, February 24, 2021 2:19 AM > To: Moger, Babu > Cc: Paolo Bonzini ; richard.hender...@linaro.org; > Eduardo Habkost ; Qemu Developers de...@nongnu.org> > Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd

Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

cept_dr to generic intercepts") >> 03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts") >> c45ad7229d13 ("KVM: SVM: Introduce >> vmcb_(set_intercept/clr_intercept/_is_intercept)") >> a90c1ed9f11d ("(pcid) KVM: nSVM: Remove u

[PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

t/_is_intercept)") a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field") fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code") 38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on AMD") 37486135d3a7 ("KVM: x86: Fix pk

Re: [PATCH] i386: Add the support for AMD EPYC 3rd generation processors

, Eduardo Habkost wrote: > On Fri, Jan 22, 2021 at 10:36:27AM -0600, Babu Moger wrote: >> Adds the support for AMD 3rd generation processors. The model >> display for the new processor will be EPYC-Milan. >> >> Adds the following new feature bits on top of the feature bits f

[PATCH] i386: Add the support for AMD EPYC 3rd generation processors

Restricted Speculation ssbd: Speculative Store Bypass Disable erms: Enhanced REP MOVSB/STOSB support fsrm: Fast Short REP MOVSB support invpcid : Invalidate processor context ID pku : Protection keys support Signed-off-by: Babu Moger --- target/i386/cpu.c | 105

[PATCH v2] target/i386: Remove core_id assert check in CPUID 0x8000001E

tps://bugzilla.redhat.com/show_bug.cgi?id=1834200 Signed-off-by: Babu Moger --- v2: Resubmitting an old patch which was lost in the mix. Just rebased on the latest tree. v1: https://lore.kernel.org/qemu-devel/159257395689.52908.4409314503988289481.st...@naples-babu.amd.com/ target/i386/cpu.c |

Re: [PATCH v6 10/10] i386: Simplify CPUID_8000_001E for AMD

On 9/18/20 4:38 PM, Eduardo Habkost wrote: > On Mon, Aug 31, 2020 at 01:43:07PM -0500, Babu Moger wrote: >> apic_id contains all the information required to build >> CPUID_8000_001E. core_id and node_id is already part of >> apic_id generated by x86_topo_ids_from_apicid.

[PATCH v7 0/2] Remove EPYC mode apicid decode and use generic decode

49.st...@naples-babu.amd.com Babu Moger (2): i386: Simplify CPUID_8000_001d for AMD i386: Simplify CPUID_8000_001E for AMD target/i386/cpu.c | 226 ++--- 1 file changed, 61 insertions(+), 165 deletions(-) --

[PATCH v7 1/2] i386: Simplify CPUID_8000_001d for AMD

Remove all the hardcoded values and replace with generalized fields. Signed-off-by: Babu Moger --- target/i386/cpu.c | 31 --- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ba4667b33c..b12addf323 100644

[PATCH v7 2/2] i386: Simplify CPUID_8000_001E for AMD

. Refer the Processor Programming Reference (PPR) documentation available from the bugzilla Link below. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov --- target/i386/cpu.c | 195 - 1

Re: [PATCH v6 09/10] i386: Simplify CPUID_8000_001E for AMD

On 9/1/20 6:52 AM, Igor Mammedov wrote: > On Mon, 31 Aug 2020 13:43:01 -0500 > Babu Moger wrote: > >> Remove all the hardcoded values and replace with generalized >> fields. >> >> Signed-off-by: Babu Moger >> --- >> target/i386/cpu.c | 31 +

[PATCH v6 09/10] i386: Simplify CPUID_8000_001E for AMD

Remove all the hardcoded values and replace with generalized fields. Signed-off-by: Babu Moger --- target/i386/cpu.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ba4667b33c..d434c8545a 100644

[PATCH v6 10/10] i386: Simplify CPUID_8000_001E for AMD

. Refer the Processor Programming Reference (PPR) documentation available from the bugzilla Link below. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- target/i386/cpu.c | 195 - 1 file changed, 45 insertions

[PATCH v6 03/10] Revert "hw/i386: Move arch_id decode inside x86_cpus_init"

This reverts commit 2e26f4ab3bf8390a2677d3afd9b1a04f015d7721. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- hw/i386/pc.c |6 +++--- hw/i386/x86.c | 37 +++-- 2 files changed, 10 insertions

[PATCH v6 05/10] Revert "hw/i386: Introduce apicid functions inside X86MachineState"

This reverts commit 6121c7fbfd98dbc3af1b00b56ff2eef66df87828. Remove the EPYC specific apicid decoding and use the generic default decoding. Signed-off-by: Babu Moger --- hw/i386/x86.c |5 - include/hw/i386/x86.h |9 - 2 files changed, 14 deletions(-) diff --git a

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