[PATCH v2 1/2] target/riscv: Fix the hpmevent mask

As per the latest privilege specification v1.13[1], the sscofpmf only reserves first 8 bits of hpmeventX. Update the corresponding masks accordingly. [1]https://github.com/riscv/riscv-isa-manual/issues/1578 Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv

[PATCH v2 0/2] Minor mhpmevent related fixes

Here are two small fixes around mhpmevent encoding and reset value. The first patch is picked from the platform specific event encoding series[1]. [1] https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e...@rivosinc.com/ Signed-off-by: Atish Patra --- Changes in v2

[PATCH v2 2/2] target/riscv: Mask out upper sscofpmf bits during validation

OF bit to indicate disable interrupt. Ensure that correct value is checked after masking while clearing the event encodings. Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH 2/2] target/riscv: Mask out upper sscofpmf bits during validation

OF bit to indicate disable interrupt. Ensure that correct value is checked after masking while clearing the event encodings. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index

[PATCH 0/2] Minor mhpmevent related fixes

Here are two small fixes around mhpmevent encoding and reset value. The first patch is picked from the platform specific event encoding series[1]. [1] https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e...@rivosinc.com/ Signed-off-by: Atish Patra --- Atish Patra (2

[PATCH 1/2] target/riscv: Fix the hpmevent mask

As per the latest privilege specification v1.13[1], the sscofpmf only reserves first 8 bits of hpmeventX. Update the corresponding masks accordingly. [1]https://github.com/riscv/riscv-isa-manual/issues/1578 Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h | 9 ++--- 1 file changed, 6

[PATCH v5 08/11] target/riscv: Add counter delegation/configuration support

From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra

[PATCH v5 06/11] target/riscv: Add counter delegation definitions

From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 8 +++- target

[PATCH v5 10/11] target/riscv: Add implied rule for counter delegation extensions

. Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da40f6871572..671fc3d1c1fc 100644 --- a/target/riscv/cpu.c

[PATCH v5 01/11] target/riscv: Add properties for Indirect CSR Access extension

From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2

[PATCH v5 02/11] target/riscv: Decouple AIA processing from xiselect and xireg

From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 165

[PATCH v5 04/11] target/riscv: Support generic CSR indirect access

. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h | 28 +- target/riscv/csr.c | 144 ++-- 2 files changed, 166

[PATCH v5 09/11] target/riscv: Invoke pmu init after feature enable

The dependant ISA features are enabled at the end of cpu_realize in finalize_features. Thus, PMU init should be invoked after that only. Move the init invocation to riscv_tcg_cpu_finalize_features. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/tcg/tcg-cpu.c | 28

[PATCH v5 03/11] target/riscv: Enable S*stateen bits for AIA

CSR accessor functions. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 85 +- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 123e9fd2bd7b

[PATCH v5 07/11] target/riscv: Add select value range check for counter delegation

From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by

[PATCH v5 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg

Add configuration options so that they can be enabled/disabld from qemu commandline. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv

[PATCH v5 05/11] target/riscv: Add properties for counter delegation ISA extensions

This adds the properties for counter delegation ISA extensions (Smcdeleg/Ssccfg). Definitions of new registers and and implementation will come in the next set of patches. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.c

[PATCH v5 00/11] Add RISC-V Counter delegation ISA extension support

ub.com/atishp04/linux/tree/b4/counter_delegation_v2 [1] https://github.com/riscv/riscv-indirect-csr-access [2] https://github.com/riscv/riscv-smcdeleg-ssccfg Cc: kaiwenx...@gmail.com Signed-off-by: Atish Patra --- Changes in v5: - Rebased on top of the riscv-to-apply.next - Added RB/AB tags. - Lin

[PATCH v4 06/11] target/riscv: Add counter delegation definitions

From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 8 +++- target

[PATCH v4 03/11] target/riscv: Enable S*stateen bits for AIA

CSR accessor functions. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 85 +- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 52e0139fc99c

[PATCH v4 04/11] target/riscv: Support generic CSR indirect access

. Co-developed-by: Atish Patra Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu_bits.h | 28 +- target/riscv/csr.c | 144 ++-- 2 files changed, 166 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h

[PATCH v4 00/11] Add RISC-V Counter delegation ISA extension support

ub.com/atishp04/linux/tree/b4/counter_delegation_v2 [1] https://github.com/riscv/riscv-indirect-csr-access [2] https://github.com/riscv/riscv-smcdeleg-ssccfg Cc: kaiwenx...@gmail.com Signed-off-by: Atish Patra --- Changes in v4: - Fixed the comments recieved on v3. - code style comments and remo

[PATCH v4 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg

Add configuration options so that they can be enabled/disabld from qemu commandline. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv

[PATCH v4 10/11] target/riscv: Add implied rule for counter delegation extensions

. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 82edd28e2e1d..410ca2e3a666 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v4 02/11] target/riscv: Decouple AIA processing from xiselect and xireg

From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 165

[PATCH v4 01/11] target/riscv: Add properties for Indirect CSR Access extension

From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 2

[PATCH v4 09/11] target/riscv: Invoke pmu init after feature enable

The dependant ISA features are enabled at the end of cpu_realize in finalize_features. Thus, PMU init should be invoked after that only. Move the init invocation to riscv_tcg_cpu_finalize_features. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/tcg/tcg-cpu.c | 28

[PATCH v4 07/11] target/riscv: Add select value range check for counter delegation

From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by

[PATCH v4 05/11] target/riscv: Add properties for counter delegation ISA extensions

This adds the properties for counter delegation ISA extensions (Smcdeleg/Ssccfg). Definitions of new registers and and implementation will come in the next set of patches. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h

[PATCH v4 08/11] target/riscv: Add counter delegation/configuration support

From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Signed

[PATCH v3 08/11] target/riscv: Add counter delegation/configuration support

From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Signed

[PATCH v3 02/11] target/riscv: Decouple AIA processing from xiselect and xireg

From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 165

[PATCH v3 10/11] target/riscv: Add implied rule for counter delegation extensions

. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 82edd28e2e1d..410ca2e3a666 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2642,6 +2642,16 @@ static

[PATCH v3 07/11] target/riscv: Add select value range check for counter delegation

From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by

[PATCH v3 09/11] target/riscv: Invoke pmu init after feature enable

The dependant ISA features are enabled at the end of cpu_realize in finalize_features. Thus, PMU init should be invoked after that only. Move the init invocation to riscv_tcg_cpu_finalize_features. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/tcg/tcg-cpu.c | 28

[PATCH v3 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg

Add configuration options so that they can be enabled/disabld from qemu commandline. Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 410ca2e3a666..2a4f285a974f

[PATCH v3 03/11] target/riscv: Enable S*stateen bits for AIA

CSR accessor functions. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 85 +- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 52e0139fc99c

[PATCH v3 06/11] target/riscv: Add counter delegation definitions

From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 8 +++- target

[PATCH v3 00/11] Add RISC-V Counter delegation ISA extension support

ub.com/atishp04/linux/tree/b4/counter_delegation_v2 [1] https://github.com/riscv/riscv-indirect-csr-access [2] https://github.com/riscv/riscv-smcdeleg-ssccfg Cc: kaiwenx...@gmail.com Signed-off-by: Atish Patra --- Changes in v3: 1. Updated the priv version in extensions 2. Fixed minor issues point

[PATCH v3 04/11] target/riscv: Support generic CSR indirect access

. Co-developed-by: Atish Patra Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu_bits.h | 28 - target/riscv/csr.c | 149 ++-- 2 files changed, 171 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b

[PATCH v3 01/11] target/riscv: Add properties for Indirect CSR Access extension

From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 4 insertions

[PATCH v3 05/11] target/riscv: Add properties for counter delegation ISA extensions

This adds the properties for counter delegation ISA extensions (Smcdeleg/Ssccfg). Definitions of new registers and and implementation will come in the next set of patches. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 4 insertions

[PATCH RFC 06/10] target/riscv: Define PMU event related structures

Signed-off-by: Atish Patra --- target/riscv/cpu.h | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2ac391a7cf74..53426710f73e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -189,6 +189,28 @@ typedef struct

[PATCH RFC 05/10] target/riscv: Rename the PMU events

functional changes introduced. Signed-off-by: Atish Patra --- target/riscv/cpu.h| 26 +++- target/riscv/cpu_helper.c | 8 +++--- target/riscv/pmu.c| 62 ++- target/riscv/pmu.h| 2 +- 4 files changed, 48 insertions

[PATCH RFC 02/10] target/riscv: Introduce helper functions for pmu hashtable lookup

The pmu implementation requires hashtable lookup operation sprinkled through the file. Add a helper function that allows to consolidate the implementation and extend it in the future easily. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 56

[PATCH RFC 08/10] target/riscv: Update event mapping hashtable for invalid events

If the software programs an invalid hpmevent or selects a invalid counter mapping, the hashtable entry should be updated accordingly. Otherwise, the user may get stale value from the old mapped counter. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 39

[PATCH RFC 03/10] target/riscv: Protect the hashtable modifications with a lock

Add a read/write lock to protect the hashtable access operations in multi-threaded scenario. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 + target/riscv/pmu.c | 10 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH RFC 01/10] target/riscv: Fix the hpmevent mask

As per the latest privilege specification v1.13[1], the sscofpmf only reserves first 8 bits of hpmeventX. Update the corresponding masks accordingly. [1]https://github.com/riscv/riscv-isa-manual/issues/1578 Signed-off-by: Atish Patra --- target/riscv/cpu_bits.h | 4 ++-- 1 file changed, 2

[PATCH RFC 10/10] hw/riscv/virt.c: Generate the PMU node from the machine

code instead of generic PMU code. Move the PMU DT node generation code from virt.c from common pmu code. Signed-off-by: Atish Patra --- hw/riscv/virt.c| 21 +++-- target/riscv/pmu.c | 36 target/riscv/pmu.h | 1 - 3 files changed, 19

[PATCH RFC 07/10] hw/riscv/virt.c : Disassociate virt PMU events

The virt PMU related implemention should belong to virt machine file rather than common pmu.c which can be used for other implementations. Make pmu.c generic by moving all the virt PMU event related structures to it's appropriate place. Signed-off-by: Atish Patra --- hw/riscv/virt.c

[PATCH RFC 09/10] target/riscv : Use the new tlb fill event functions

We have TLB related event call back available now. Invoke them from generic cpu helper code so that other machines can implement those as well in the future. The virt machine is the only user for now though. Signed-off-by: Atish Patra --- target/riscv/cpu_helper.c | 21

[PATCH RFC 04/10] target/riscv: Use uint64 instead of uint as key

The event ID can be a upto 56 bit value when sscofpmf is implemented. Change the event to counter hashtable to store the keys as 64 bit value instead of uint. Signed-off-by: Atish Patra --- target/riscv/pmu.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a

[PATCH] target/riscv: Add asserts for out-of-bound access

etect any wrong usage of these arrays in the future. Suggested-by: Peter Maydell Signed-off-by: Atish Patra --- The lore discussion can be found here https://lore.kernel.org/all/CAHBxVyGQHBobpf71o4Qp51iQGXKBh0Ajup=e_a95xdLF==v...@mail.gmail.com/ --- target/riscv/pmu.c | 4 1 file chang

[PATCH v2 08/13] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg

Add configuration options so that they can be enabled/disabld from qemu commandline. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac2dce734d80..1731dc461376 100644 --- a/target/riscv/cpu.c

[PATCH v2 05/13] target/riscv: Add counter delegation definitions

From: Kaiwen Xue This adds definitions for counter delegation, including the new scountinhibit register and the mstateen.CD bit. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 8 +++- target/riscv/machine.c | 1 + 3

[PATCH v2 10/13] target/riscv: Enable sscofpmf for bare cpu by default

Sscofpmf has been supported on virt machine for a long time. It is required to enable profiling on virt machines. Let's enable it by default for ease of usage. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/

[PATCH v2 04/13] target/riscv: Support generic CSR indirect access

. Co-developed-by: Atish Patra Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 + target/riscv/cpu_bits.h | 28 - target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 149 ++-- 4 files changed, 175

[PATCH v2 02/13] target/riscv: Decouple AIA processing from xiselect and xireg

From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/csr.c | 165 - 1 file

[PATCH v2 07/13] target/riscv: Add counter delegation/configuration support

From: Kaiwen Xue The Smcdeleg/Ssccfg adds the support for counter delegation via S*indcsr and Ssccfg. It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE) to enable this extension and scountovf virtualization. Signed-off-by: Kaiwen Xue Co-developed-by: Atish Patra Signed

[PATCH v2 09/13] target/riscv: Invoke pmu init after feature enable

The dependant ISA features are enabled at the end of cpu_realize in finalize_features. Thus, PMU init should be invoked after that only. Move the init invocation to riscv_tcg_cpu_finalize_features. Signed-off-by: Atish Patra --- target/riscv/tcg/tcg-cpu.c | 28 ++-- 1

[PATCH v2 12/13] target/riscv: Add a preferred ISA extension rule

allows to enable multiple extensions together without burdening the qemu commandline user. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 4 target/riscv/cpu.h | 17 ++ target/riscv/tcg/tcg-cpu.c | 57 -- 3 files

[PATCH v2 11/13] target/riscv: Repurpose the implied rule startergy

The current infrastructure for implied ISA extension enabling can be used for other cases where a particular ISA is dependant on multiple other ISA extension to enable all the features. Rename the implied rule functions/data structures to accomodate that. Signed-off-by: Atish Patra --- target

[PATCH v2 00/13] Add RISC-V Counter delegation ISA extension support

-5d5f7def9...@ventanamicro.com/T/ [1] https://github.com/riscv/riscv-indirect-csr-access [2] https://github.com/riscv/riscv-smcdeleg-ssccfg Cc: kaiwenx...@gmail.com Signed-off-by: Atish Patra --- Atish Patra (7): target/riscv: Enable S*stateen bits for AIA target/riscv: Add configuration for S[

[PATCH v2 03/13] target/riscv: Enable S*stateen bits for AIA

CSR accessor functions. Signed-off-by: Atish Patra --- target/riscv/csr.c | 88 +- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58be8bc3cc8c..18b9ae802b15 100644 --- a/target/riscv

[PATCH v2 13/13] target/riscv: Enable PMU related extensions to preferred rule

e all of these if Ssccfg extension is enabled from the commandline. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 22ba43c7ff2a..abebfcc46dea 100644 --- a/target/

[PATCH v2 06/13] target/riscv: Add select value range check for counter delegation

From: Kaiwen Xue This adds checks in ops performed on xireg and xireg2-xireg6 so that the counter delegation function will receive a valid xiselect value with the proper extensions enabled. Co-developed-by: Atish Patra Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv

[PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension

From: Kaiwen Xue This adds the properties for sxcsrind. Definitions of new registers and implementations will come with future patches. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 2 ++ 2 files changed, 4 insertions

[PATCH v8 08/13] target/riscv: Save counter values during countinhibit update

counter is stopped. Thus, save the value of the counter during the inhibit update operation and return that value during the read if corresponding bit in mcountihibit is set. Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1

[PATCH v8 07/13] target/riscv: Implement privilege mode filtering for cycle/instret

: Atish Patra --- target/riscv/cpu.h| 11 + target/riscv/cpu_helper.c | 9 +++- target/riscv/csr.c| 117 -- target/riscv/pmu.c| 92 target/riscv/pmu.h| 2 + 5 files changed, 194

[PATCH v8 05/13] target/riscv: Add cycle & instret privilege mode filtering support

: Atish Patra Reviewed-by: Daniel Henrique Barboza Signed-off-by: Kaiwen Xue --- target/riscv/cpu_bits.h | 12 + target/riscv/csr.c | 138 +++- 2 files changed, 149 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target

[PATCH v8 10/13] target/riscv: Start counters from both mhpmcounter and mcountinhibit

From: Rajnesh Kanwal Currently we start timer counter from write_mhpmcounter path only without checking for mcountinhibit bit. This changes adds mcountinhibit check and also programs the counter from write_mcountinhibit as well. When a counter is stopped using mcountinhibit we simply update the

[PATCH v8 09/13] target/riscv: Enforce WARL behavior for scounteren/hcounteren

scounteren/hcountern are also WARL registers similar to mcountern. Only set the bits for the available counters during the write to preserve the WARL behavior. Signed-off-by: Atish Patra Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/csr.c | 12

[PATCH v8 11/13] target/riscv: More accurately model priv mode filtering.

From: Rajnesh Kanwal In case of programmable counters configured to count inst/cycles we often end-up with counter not incrementing at all from kernel's perspective. For example: - Kernel configures hpm3 to count instructions and sets hpmcounter to -1 and all modes except U mode are inhibi

[PATCH v8 02/13] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: A

[PATCH v8 04/13] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29

[PATCH v8 13/13] target/riscv: Expose the Smcntrpmf config

Create a new config for Smcntrpmf extension so that it can be enabled/ disabled from the qemu commandline. Signed-off-by: Atish Patra --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 63f553c92b00..ef50130a91e7 100644 --- a

[PATCH v8 03/13] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + 2 files changed, 2 insertions

[PATCH v8 00/13] Add RISC-V ISA extension smcntrpmf support

vosinc.com/ Cc: Rajnesh Kanwal Signed-off-by: Atish Patra --- Atish Patra (7): target/riscv: Fix the predicate functions for mhpmeventhX CSRs target/riscv: Only set INH fields if priv mode is available target/riscv: Implement privilege mode filtering for cycle/instret

[PATCH v8 06/13] target/riscv: Only set INH fields if priv mode is available

Currently, the INH fields are set in mhpmevent uncoditionally without checking if a particular priv mode is supported or not. Suggested-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 29 + 1 file changed, 25 insertions(+), 4 deletions

[PATCH v8 01/13] target/riscv: Combine set_mode and set_virt functions.

From: Rajnesh Kanwal Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode() functions. This is to make complete mode change information available through a single function. This allows to easily differentiate between HS->VS, VS->HS and VS->VS transitions when executing state update code

[PATCH v8 12/13] target/riscv: Do not setup pmu timer if OF is disabled

Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/pmu.c | 56 ++ 1 file changed, 44 insertions(+), 12 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a4729f6c53bb..3cc0b3648cad 100644 --- a/target/riscv/pmu.c +++ b

[PATCH v7 02/11] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: A

[PATCH v7 04/11] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra --- target/riscv/cpu.h | 6 ++ target/riscv/cpu_bits.h | 29 + 2 files changed, 35

[PATCH v7 10/11] target/riscv: More accurately model priv mode filtering.

From: Rajnesh Kanwal In case of programmable counters configured to count inst/cycles we often end-up with counter not incrementing at all from kernel's perspective. For example: - Kernel configures hpm3 to count instructions and sets hpmcounter to -1 and all modes except U mode are inhibi

[PATCH v7 11/11] target/riscv: Do not setup pmu timer if OF is disabled

The timer is setup function is invoked in both hpmcounter write and mcountinhibit write path. If the OF bit set, the LCOFI interrupt is disabled. There is no benefitting in setting up the qemu timer until LCOFI is cleared to indicate that interrupts can be fired again. Signed-off-by: Atish Patra

[PATCH v7 09/11] target/riscv: Start counters from both mhpmcounter and mcountinhibit

From: Rajnesh Kanwal Currently we start timer counter from write_mhpmcounter path only without checking for mcountinhibit bit. This changes adds mcountinhibit check and also programs the counter from write_mcountinhibit as well. When a counter is stopped using mcountinhibit we simply update the

[PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c

[PATCH v7 08/11] target/riscv: Enforce WARL behavior for scounteren/hcounteren

scounteren/hcountern are also WARL registers similar to mcountern. Only set the bits for the available counters during the write to preserve the WARL behavior. Signed-off-by: Atish Patra Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/csr.c | 12

[PATCH v7 07/11] target/riscv: Save counter values during countinhibit update

counter is stopped. Thus, save the value of the counter during the inhibit update operation and return that value during the read if corresponding bit in mcountihibit is set. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 - target/riscv/csr.c | 34

[PATCH v7 01/11] target/riscv: Combine set_mode and set_virt functions.

From: Rajnesh Kanwal Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode() functions. This is to make complete mode change information available through a single function. This allows to easily differentiate between HS->VS, VS->HS and VS->VS transitions when executing state update code

[PATCH v7 06/11] target/riscv: Implement privilege mode filtering for cycle/instret

/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Co-Developed-by: Rajnesh Kanwal Signed-off-by: Atish Patra Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h| 11 + target

[PATCH v7 05/11] target/riscv: Add cycle & instret privilege mode filtering support

: Atish Patra Reviewed-by: Daniel Henrique Barboza Signed-off-by: Kaiwen Xue --- target/riscv/csr.c | 88 ++ 1 file changed, 88 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3ad851707e5c..665c534db1a0 100644 --- a

[PATCH v7 00/11] Add RISC-V ISA extension smcntrpmf support

vosinc.com/ Cc: Rajnesh Kanwal Signed-off-by: Atish Patra --- Atish Patra (5): target/riscv: Fix the predicate functions for mhpmeventhX CSRs target/riscv: Implement privilege mode filtering for cycle/instret target/riscv: Save counter values during countinhibit update

Re: [PATCH 0/3] Assorted fixes for PMU

On Tue, May 14, 2024 at 2:16 AM Peter Maydell wrote: > > On Mon, 29 Apr 2024 at 20:29, Atish Patra wrote: > > > > This series contains few miscallenous fixes related to hpmcounters > > and related code. The first patch fixes an issue with cycle/instret > >

Re: [PATCH 0/3] Assorted fixes for PMU

On Tue, May 14, 2024 at 3:18 AM Alistair Francis wrote: > > On Tue, May 14, 2024 at 5:15 PM Atish Kumar Patra wrote: > > > > On Mon, May 13, 2024 at 11:29 PM Alistair Francis > > wrote: > > > > > > On Tue, Apr 30, 2024 at 5:29 AM Atish Patra wrote

[PATCH 0/3] Assorted fixes for PMU

This series contains few miscallenous fixes related to hpmcounters and related code. The first patch fixes an issue with cycle/instret counters overcouting while the remaining two are more for specification compliance. Signed-off-by: Atish Patra --- Atish Patra (3): target/riscv: Save

[PATCH 1/3] target/riscv: Save counter values during countinhibit update

counter is stopped. Thus, save the value of the counter during the inhibit update operation and return that value during the read if corresponding bit in mcountihibit is set. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 1 - target/riscv/csr.c | 32

[PATCH 3/3] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: A

[PATCH 2/3] target/riscv: Enforce WARL behavior for scounteren/hcounteren

scounteren/hcountern are also WARL registers similar to mcountern. Only set the bits for the available counters during the write to preserve the WARL behavior. Signed-off-by: Atish Patra --- target/riscv/csr.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a

Re: [PATCH v5 5/5] target/riscv: Implement privilege mode filtering for cycle/instret

On 3/19/24 21:54, Alistair Francis wrote: On Thu, Mar 7, 2024 at 7:26 PM Atish Patra wrote: On 3/4/24 22:47, LIU Zhiwei wrote: On 2024/2/29 2:51, Atish Patra wrote: Privilege mode filtering can also be emulated for cycle/instret by tracking host_ticks/icount during each privilege mode

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