On Thu, Jan 9, 2025 at 6:10 PM Alistair Francis wrote:
>
> On Wed, Dec 4, 2024 at 9:18 AM Atish Patra wrote:
> >
> > This series adds the counter delegation extension support. The counter
> > delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA
> > extensions.
> >
> > 1. S[m
On Mon, Dec 2, 2024 at 1:49 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 12/2/24 6:15 PM, Atish Kumar Patra wrote:
> > On Thu, Nov 28, 2024 at 4:53 AM Daniel Henrique Barboza
> > wrote:
> >>
> >>
> >>
> >> On 11/17/24 10:15 PM, Atish P
On Thu, Nov 28, 2024 at 3:52 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 11/17/24 10:15 PM, Atish Patra wrote:
> > From: Kaiwen Xue
> >
> > This adds the indirect access registers required by sscsrind/smcsrind
> > and the operations on them. Note that xiselect and xireg are used for
> > both AIA
On Thu, Nov 28, 2024 at 4:53 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 11/17/24 10:15 PM, Atish Patra wrote:
> > From: Kaiwen Xue
> >
> > The Smcdeleg/Ssccfg adds the support for counter delegation via
> > S*indcsr and Ssccfg.
> >
> > It also adds a new shadow CSR scountinhibit and menvcfg ena
On Fri, Nov 22, 2024 at 3:43 AM Aleksei Filippov
wrote:
>
>
>
> > On 21 Nov 2024, at 22:54, Atish Kumar Patra wrote:
> >
> > On Wed, Nov 20, 2024 at 6:25 AM Aleksei Filippov
> > wrote:
> >>
> >>
> >>
> >>> On 22 Oct 2024, a
On Wed, Nov 20, 2024 at 6:25 AM Aleksei Filippov
wrote:
>
>
>
> > On 22 Oct 2024, at 15:58, Atish Kumar Patra wrote:
> >
> > On Mon, Oct 21, 2024 at 6:45 AM Aleksei Filippov
> > wrote:
> >>
> >>
> >>
> >>> On 11 Oct 2024, a
On Mon, Oct 21, 2024 at 6:45 AM Aleksei Filippov
wrote:
>
>
>
> > On 11 Oct 2024, at 23:45, Atish Kumar Patra wrote:
> >
> > On Thu, Oct 10, 2024 at 5:44 AM Alexei Filippov
> > wrote:
> >>
> >>
> >>
> >> On
On Thu, Oct 10, 2024 at 5:44 AM Alexei Filippov
wrote:
>
>
>
> On 10.10.2024 02:09, Atish Patra wrote:
> > Signed-off-by: Atish Patra
> > ---
> > target/riscv/cpu.h | 25 +
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
On Thu, Oct 10, 2024 at 5:10 AM Alexei Filippov
wrote:
>
>
>
> On 10.10.2024 02:09, Atish Patra wrote:
> > The current PMU events are defined by SBI PMU
> > specification. As there is no standard event encoding
> > scheme, Virt machine chooses to use the SBI PMU encoding.
> > A platform may choos
On Thu, Aug 8, 2024 at 1:24 AM Alistair Francis wrote:
>
> On Thu, Aug 8, 2024 at 6:12 PM Atish Kumar Patra wrote:
> >
> > On Wed, Aug 7, 2024 at 5:27 PM Alistair Francis
> > wrote:
> > >
> > > On Wed, Aug 7, 2024 at 5:44 PM Atish Kumar Patra
> &
On Wed, Aug 7, 2024 at 5:27 PM Alistair Francis wrote:
>
> On Wed, Aug 7, 2024 at 5:44 PM Atish Kumar Patra wrote:
> >
> > On Tue, Aug 6, 2024 at 7:01 PM Alistair Francis
> > wrote:
> > >
> > > On Wed, Aug 7, 2024 at 2:
On Mon, Aug 5, 2024 at 5:12 PM Alistair Francis wrote:
>
> On Wed, Jul 24, 2024 at 9:31 AM Atish Patra wrote:
> >
> > As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
> > access.
> >
> > Bit 60 controls the indirect CSRs
> > Bit 59 controls the most AIA CSR state
> > Bit 58 c
On Wed, Jul 31, 2024 at 2:24 AM Alistair Francis wrote:
>
> On Sat, Jul 27, 2024 at 11:33 AM Atish Kumar Patra
> wrote:
> >
> > On Fri, Jul 26, 2024 at 12:42 AM Alistair Francis
> > wrote:
> > >
> > > On Wed, Jul 24, 2024 at 9:31 AM Atish P
On Mon, Aug 5, 2024 at 5:15 PM Alistair Francis wrote:
>
> On Wed, Jul 24, 2024 at 9:32 AM Atish Patra wrote:
> >
> > From: Kaiwen Xue
> >
> > This adds the indirect access registers required by sscsrind/smcsrind
> > and the operations on them. Note that xiselect and xireg are used for
> > both
On Mon, Aug 5, 2024 at 6:21 PM Alistair Francis wrote:
>
> On Wed, Jul 24, 2024 at 9:32 AM Atish Patra wrote:
> >
> > From: Kaiwen Xue
> >
> > The Smcdeleg/Ssccfg adds the support for counter delegation via
> > S*indcsr and Ssccfg.
> >
> > It also adds a new shadow CSR scountinhibit and menvcfg
On Mon, Aug 5, 2024 at 6:48 PM Alistair Francis wrote:
>
> On Wed, Jul 24, 2024 at 9:32 AM Atish Patra wrote:
> >
> > In addition to the implied rule, a preferred rule will be useful
> > where an ISA extension may require a list of ISA extension to be
> > enabled to use all the features defined i
On Tue, Aug 6, 2024 at 7:01 PM Alistair Francis wrote:
>
> On Wed, Aug 7, 2024 at 2:06 AM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 8/6/24 5:46 AM, Andrew Jones wrote:
> > > On Tue, Jul 23, 2024 at 04:30:10PM GMT, Atish Patra wrote:
> > >> Counter delegation/configuration extension requ
On Thu, Jul 25, 2024 at 10:12 PM Alistair Francis wrote:
>
> On Wed, Jul 24, 2024 at 6:33 PM Atish Patra wrote:
> >
> > Coverity complained about the possible out-of-bounds access with
> > counter_virt/counter_virt_prev because these two arrays are
> > accessed with privilege mode. However, these
On Fri, Jul 26, 2024 at 12:42 AM Alistair Francis wrote:
>
> On Wed, Jul 24, 2024 at 9:31 AM Atish Patra wrote:
> >
> > From: Kaiwen Xue
> >
> > This adds the properties for sxcsrind. Definitions of new registers and
> > implementations will come with future patches.
> >
> > Signed-off-by: Atish
On Thu, Jul 25, 2024 at 10:12 PM Alistair Francis wrote:
>
> On Wed, Jul 24, 2024 at 6:33 PM Atish Patra wrote:
> >
> > Coverity complained about the possible out-of-bounds access with
> > counter_virt/counter_virt_prev because these two arrays are
> > accessed with privilege mode. However, these
On Wed, Jun 5, 2024 at 4:49 AM Jason Chien wrote:
>
> The predicate functions should contain the access control by the
> state-enable CSRs, which is not presented in this patch. Do you mind
> that I take over the indirect CSR access control part? The Signed-off-by
> will be kept.
>
> Atish Patra 於
On Sat, Jul 20, 2024 at 8:19 AM Peter Maydell wrote:
>
> On Thu, 18 Jul 2024 at 03:15, Alistair Francis wrote:
> >
> > From: Atish Patra
> >
> > The timer is setup function is invoked in both hpmcounter
> > write and mcountinhibit write path. If the OF bit set, the
> > LCOFI interrupt is disable
On Sat, Jul 20, 2024 at 7:44 AM Peter Maydell wrote:
>
> On Thu, 18 Jul 2024 at 03:12, Alistair Francis wrote:
> >
> > From: Atish Patra
> >
> > Privilege mode filtering can also be emulated for cycle/instret by
> > tracking host_ticks/icount during each privilege mode switch. This
> > patch imp
On Tue, Jul 2, 2024 at 6:19 PM Alistair Francis wrote:
>
> On Thu, Jun 27, 2024 at 10:00 AM Atish Patra wrote:
> >
> > From: Kaiwen Xue
> >
> > QEMU only calculates dummy cycles and instructions, so there is no
> > actual means to stop the icount in QEMU. Hence this patch merely adds
> > the fun
On Tue, Jul 2, 2024 at 7:03 PM Alistair Francis wrote:
>
> On Thu, Jun 27, 2024 at 9:59 AM Atish Patra wrote:
> >
> > From: Kaiwen Xue
> >
> > This adds the properties for ISA extension smcntrpmf. Patches
> > implementing it will follow.
> >
> > Signed-off-by: Atish Patra
> > Signed-off-by: Kai
On Tue, Jun 18, 2024 at 4:27 AM Clément Léger wrote:
>
> When icount is enabled, rather than returning the virtual CPU time, we
> should return the instruction count itself. Add an instructions bool
> parameter to get_ticks() to correctly return icount_get_raw() when
> icount_enabled() == 1 and in
Hi Daniel,
On Sat, Jun 1, 2024 at 2:52 AM Daniel Henrique Barboza
wrote:
>
> Hi Atish,
>
>
> I see that Rajnesh sent some patches that were built on top of this
> work [1], and this series no longer applies neither to alistair's
> risc-to-apply.next nor to master.
>
> If you could send a rebased
On Mon, May 13, 2024 at 11:29 PM Alistair Francis wrote:
>
> On Tue, Apr 30, 2024 at 5:29 AM Atish Patra wrote:
> >
> > This series contains few miscallenous fixes related to hpmcounters
> > and related code. The first patch fixes an issue with cycle/instret
> > counters overcouting while the rem
On Thu, May 2, 2024 at 5:39 AM Andrew Jones wrote:
>
> On Tue, Apr 30, 2024 at 03:00:45PM GMT, Daniel Henrique Barboza wrote:
> >
> >
> > On 4/29/24 16:28, Atish Patra wrote:
> > > Currently, if a counter monitoring cycle/instret is stopped via
> > > mcountinhibit we just update the state while th
On Thu, Apr 11, 2024 at 4:34 AM Clément Léger wrote:
>
> When icount is enabled, rather than returning the virtual CPU time, we
> should return the instruction count itself. Add an instructions bool
> parameter to get_ticks() to correctly return icount_get_raw() when
> icount_enabled() == 1 and in
On Tue, Mar 12, 2024 at 6:53 AM Fei Wu wrote:
>
> The RISC-V Server Platform specification[1] defines a standardized set
> of hardware and software capabilities, that portable system software,
> such as OS and hypervisors can rely on being present in a RISC-V server
> platform.
>
> A corresponding
On Fri, Mar 22, 2024 at 2:20 AM Marcin Juszkiewicz
wrote:
>
> W dniu 22.03.2024 o 09:50, Heinrich Schuchardt pisze:
> >>> I see no mention of device trees in the spec, but I do see ACPI. Do we
> >>> really expect a server platform to use DTs?
> >>
> >> This platform "kind of" follows sbsa-ref
ncis wrote:
> > >>> On Thu, Mar 7, 2024 at 5:13 AM Atish Kumar Patra
> > >>> wrote:
> > >>>>
> > >>>> On Wed, Mar 6, 2024 at 4:56 AM Wu, Fei wrote:
> > >>>>>
> > >>>>> On 3/6/202
On Wed, Mar 6, 2024 at 4:56 AM Wu, Fei wrote:
>
> On 3/6/2024 8:19 AM, Alistair Francis wrote:
> > On Mon, Mar 4, 2024 at 8:28 PM Fei Wu wrote:
> >>
> >> The RISC-V Server Platform specification[1] defines a standardized set
> >> of hardware and software capabilities, that portable system softwar
On Wed, Feb 21, 2024 at 6:58 AM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Hi Atish,
>
> This series and its dependency, which I assume it's
>
> "[PATCH v4 0/5] Add ISA extension smcntrpmf support"
>
> Doesn't apply in neither master nor riscv-to-apply.next because of this
> pat
On Tue, Jan 23, 2024 at 4:15 PM Atish Kumar Patra
wrote:
> On Sun, Jan 21, 2024 at 9:04 PM Alistair Francis
> wrote:
> >
> > On Tue, Jan 9, 2024 at 10:29 AM Atish Patra wrote:
> > >
> > > Privilege mode filtering can also be emulated for cycle/instret by
>
On Sun, Jan 21, 2024 at 9:04 PM Alistair Francis wrote:
>
> On Tue, Jan 9, 2024 at 10:29 AM Atish Patra wrote:
> >
> > Privilege mode filtering can also be emulated for cycle/instret by
> > tracking host_ticks/icount during each privilege mode switch. This
> > patch implements that for both cycle
On Mon, Jan 8, 2024 at 10:10 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 1/5/24 19:13, Atish Patra wrote:
> > From: Kaiwen Xue
> >
> > This adds the properties for ISA extension smcntrpmf. Patches
> > implementing it will follow.
> >
> > Signed-off-by: Atish Patra
> > Signed-off-by: Kaiwen Xue
On Thu, Jan 4, 2024 at 6:46 PM Alistair Francis wrote:
>
> On Fri, Dec 29, 2023 at 12:08 PM Atish Patra wrote:
> >
> > From: Kaiwen Xue
> >
> > This adds the definitions for ISA extension smcntrpmf.
> >
> > Signed-off-by: Kaiwen Xue
> > Signed-off-by: Atish Patra
> > ---
> > target/riscv/cpu.
On Wed, Jan 3, 2024 at 12:18 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 12/28/23 21:49, Atish Patra wrote:
> > From: Kaiwen Xue
> >
> > QEMU only calculates dummy cycles and instructions, so there is no
> > actual means to stop the icount in QEMU. Hence this patch merely adds
> > the functional
On Wed, Jan 3, 2024 at 12:11 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 12/28/23 21:49, Atish Patra wrote:
> > From: Kaiwen Xue
> >
> > This adds the properties for ISA extension smcntrpmf. Patches
> > implementing it will follow.
> >
> > Signed-off-by: Atish Patra
> > Signed-off-by: Kaiwen Xu
On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford wrote:
>
> A 32-bit mask can be trivially created using the 64-bit macro so make
> use of that instead.
>
> Signed-off-by: Rob Bradford
> Reviewed-by: Alistair Francis
> ---
> target/riscv/pmu.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions
On Sun, Oct 22, 2023 at 7:04 PM Alistair Francis wrote:
>
> On Thu, Oct 19, 2023 at 1:47 AM Rob Bradford wrote:
> >
> > This has been replaced by a "pmu-mask" property that provides much more
> > flexibility.
> >
> > Signed-off-by: Rob Bradford
> > Acked-by: LIU Zhiwei
>
> Reviewed-by: Alistair
On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford wrote:
>
> During the FDT generation use the existing mask containing the enabled
> counters rather then generating a new one. Using the existing mask will
> support the use of discontinuous counters.
>
> Signed-off-by: Rob Bradford
> Reviewed-by: LIU
On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford wrote:
>
> Check the PMU available bitmask when checking if a counter is valid
> rather than comparing the index against the number of PMUs.
>
> Signed-off-by: Rob Bradford
> Reviewed-by: LIU Zhiwei
> Reviewed-by: Alistair Francis
> ---
> target/ris
On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford wrote:
>
> More closely follow the QEMU style by returning an Error and propagating
> it there is an error relating to the PMU setup.
>
> Further simplify the function by removing the num_counters parameter as
> this is available from the passed in cpu
On Sun, Oct 8, 2023 at 5:58 PM Alistair Francis wrote:
>
> On Wed, Oct 4, 2023 at 7:36 PM Rob Bradford wrote:
> >
> > Hi Atish,
> >
> > On Tue, 2023-10-03 at 13:25 -0700, Atish Kumar Patra wrote:
> > > On Tue, Oct 3, 2023 at 5:51 AM Rob Bradford
&
On Tue, Oct 3, 2023 at 5:51 AM Rob Bradford wrote:
>
> There is no requirement that the enabled counters in the platform are
> continuously numbered. Add a "pmu-mask" property that, if specified, can
> be used to specify the enabled PMUs. In order to avoid ambiguity if
> "pmu-mask" is specified th
On Tue, Nov 29, 2022 at 3:54 PM wrote:
>
> +CC Rob, which I probably should've done earlier, so
> context all preserved
>
> On 29/11/2022 09:42, Conor Dooley wrote:
> > On 29/11/2022 09:27, Atish Kumar Patra wrote:
> >> EXTERNAL EMAIL: Do not click links or o
rote:
> >> On 28/11/2022 20:41, Atish Kumar Patra wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know
> >>> the content is safe
> >>>
> >>> On Mon, Nov 28, 2022 at 12:38 PM wrote:
> >>>>
>
On Mon, Nov 28, 2022 at 12:38 PM wrote:
>
> On 28/11/2022 20:16, Atish Kumar Patra wrote:
> > On Thu, Nov 24, 2022 at 5:17 AM Conor Dooley
> > wrote:
> >>
> >> On Wed, Aug 24, 2022 at 03:17:00PM -0700, Atish Patra wrote:
> >>> Qemu virt machin
On Thu, Nov 24, 2022 at 5:17 AM Conor Dooley wrote:
>
> On Wed, Aug 24, 2022 at 03:17:00PM -0700, Atish Patra wrote:
> > Qemu virt machine can support few cache events and cycle/instret counters.
> > It also supports counter overflow for these events.
> >
> > Add a DT node so that OpenSBI/Linux ke
On Mon, Nov 21, 2022 at 10:11 PM Alistair Francis wrote:
>
> On Sun, Nov 13, 2022 at 7:52 PM Atish Patra wrote:
> >
> > The imsic DT binding[1] has changed and no longer require an ipi-id.
> > The latest IMSIC driver dynamically allocates ipi id if slow-ipi
> > is not defined.
> >
> > Get rid of
On Fri, Nov 11, 2022 at 4:39 PM Bin Meng wrote:
> On Sat, Nov 12, 2022 at 4:14 AM Atish Patra wrote:
> >
> > The imsic DT binding has changed and no longer require an ipi-id.
>
> requires
>
>
Sure. Will fix it.
> Could you please put a link here to the upstream imsic DT binding for
> reference
On Mon, Sep 19, 2022 at 3:08 PM Alistair Francis
wrote:
> On Thu, Aug 25, 2022 at 8:22 AM Atish Patra wrote:
> >
> > The latest version of the SBI specification includes a Performance
> Monitoring
> > Unit(PMU) extension[1] which allows the supervisor to
> start/stop/configure
> > various PMU ev
On Tue, Aug 23, 2022 at 2:10 PM Alistair Francis
wrote:
> On Thu, Aug 11, 2022 at 4:57 AM Atish Patra wrote:
> >
> > Historically, The mtime/mtimecmp has been part of the CPU because
> > they are per hart entities. However, they actually belong to aclint
> > which is a MMIO device.
> >
> > Move
On Mon, Aug 22, 2022 at 5:38 PM Alistair Francis
wrote:
> On Wed, Aug 17, 2022 at 9:24 AM Atish Patra wrote:
> >
> > From: Atish Patra
> >
> > Qemu can monitor the following cache related PMU events through
> > tlb_fill functions.
> >
> > 1. DTLB load/store miss
> > 3. ITLB prefetch miss
> >
>
On Sun, Aug 14, 2022 at 5:02 PM Alistair Francis
wrote:
> On Fri, Aug 12, 2022 at 12:05 PM Atish Patra
> wrote:
> >
> > On Tue, Aug 2, 2022 at 4:33 PM Atish Patra wrote:
> > >
> > > The latest version of the SBI specification includes a Performance
> Monitoring
> > > Unit(PMU) extension[1] whic
On Mon, Aug 15, 2022 at 12:54 AM Andrew Jones
wrote:
> On Tue, Aug 02, 2022 at 04:33:03PM -0700, Atish Patra wrote:
> > All the hpmcounters and the fixed counters (CY, IR, TM) can be
> represented
> > as a unified counter. Thus, the predicate function doesn't need handle
> each
> > case separatel
On Tue, Aug 9, 2022 at 6:33 PM Weiwei Li wrote:
>
> 在 2022/8/10 上午3:34, Atish Kumar Patra 写道:
>
>
>
>
> On Tue, Aug 9, 2022 at 12:01 AM Weiwei Li wrote:
>
>>
>> 在 2022/8/9 上午1:20, Atish Kumar Patra 写道:
>>
>>
>>
>> On Sun, Aug 7, 20
On Tue, Aug 9, 2022 at 12:01 AM Weiwei Li wrote:
>
> 在 2022/8/9 上午1:20, Atish Kumar Patra 写道:
>
>
>
> On Sun, Aug 7, 2022 at 6:50 PM Weiwei Li wrote:
>
>>
>> 在 2022/8/4 上午9:42, Atish Patra 写道:
>> > vstimecmp CSR allows the guest OS or to program th
On Sun, Aug 7, 2022 at 6:50 PM Weiwei Li wrote:
>
> 在 2022/8/4 上午9:42, Atish Patra 写道:
> > vstimecmp CSR allows the guest OS or to program the next guest timer
> > interrupt directly. Thus, hypervisor no longer need to inject the
> > timer interrupt to the guest if vstimecmp is used. This was rat
On Wed, Aug 3, 2022 at 3:26 AM Ben Dooks wrote:
> On 03/08/2022 09:25, Atish Patra wrote:
> > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > to program the next timer interrupt. This CSR is part of the Sstc
> > extension which was ratified recently.
> >
> > Signed-off-by:
On Wed, Aug 3, 2022 at 1:42 AM Weiwei Li wrote:
>
> 在 2022/8/3 下午4:25, Atish Patra 写道:
> > stimecmp allows the supervisor mode to update stimecmp CSR directly
> > to program the next timer interrupt. This CSR is part of the Sstc
> > extension which was ratified recently.
> >
> > Signed-off-by: At
On Wed, Aug 3, 2022 at 1:49 AM Weiwei Li wrote:
>
> 在 2022/8/3 下午4:25, Atish Patra 写道:
> > vstimecmp CSR allows the guest OS or to program the next guest timer
> > interrupt directly. Thus, hypervisor no longer need to inject the
> > timer interrupt to the guest if vstimecmp is used. This was rat
On Tue, Aug 2, 2022 at 7:13 PM Weiwei Li wrote:
>
> 在 2022/8/3 上午7:33, Atish Patra 写道:
> > The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
> > and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
> > extension allows the perf to handle overflow interrupts and filt
On Wed, Jul 27, 2022 at 5:56 PM Weiwei Li wrote:
>
> 在 2022/7/28 上午5:40, Atish Kumar Patra 写道:
>
>
>
> On Wed, Jul 27, 2022 at 1:35 AM Weiwei Li wrote:
>
>>
>> 在 2022/7/27 下午2:49, Atish Patra 写道:
>> > All the hpmcounters and the fixed counters (C
On Sat, Jul 30, 2022 at 9:11 PM Rahul Pathak
wrote:
> Hi Atish,
>
> I tried your riscv_pmu_v12 branch but I couldn't made it working
> without below change -
> without this change qemu was not exporting the sscofpmf in the cpu dt nodes
>
> -
> diff --git a/target/riscv/cpu.c b/target
On Wed, Jul 27, 2022 at 1:27 AM Weiwei Li wrote:
>
> 在 2022/7/27 下午2:49, Atish Patra 写道:
> > The sscofpmf extension was ratified as a part of priv spec v1.12.
> > Mark the csr_ops accordingly.
> >
> > Reviewed-by: Alistair Francis
> > Signed-off-by: Atish Patra
> > ---
> > target/riscv/csr.c
On Wed, Jul 27, 2022 at 1:35 AM Weiwei Li wrote:
>
> 在 2022/7/27 下午2:49, Atish Patra 写道:
> > All the hpmcounters and the fixed counters (CY, IR, TM) can be
> represented
> > as a unified counter. Thus, the predicate function doesn't need handle
> each
> > case separately.
> >
> > Simplify the pre
On Wed, Jul 27, 2022 at 1:11 AM Weiwei Li wrote:
>
> 在 2022/7/27 下午2:49, Atish Patra 写道:
> > The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
> > and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
> > extension allows the perf to handle overflow interrupts and fi
On Wed, Jul 27, 2022 at 5:23 AM Alistair Francis
wrote:
> On Sat, Jul 23, 2022 at 7:22 PM Atish Patra wrote:
> >
> > Since commit 40244040a7ac, multi-socket configuration with plic is
> > broken as the hartid for second socket is calculated incorrectly.
> > The hartid stored in addr_config alrea
On Wed, Jul 27, 2022 at 12:27 AM Sunil V L wrote:
> Hi Atish,
>
> On Tue, Jul 26, 2022 at 11:49:11PM -0700, Atish Patra wrote:
> > Qemu virt machine can support few cache events and cycle/instret
> counters.
> > It also supports counter overflow for these events.
> >
> > Add a DT node so that Ope
On Sun, Jul 24, 2022 at 6:14 PM Alistair Francis
wrote:
> On Sat, Jul 23, 2022 at 7:22 PM Atish Patra wrote:
> >
> > Since commit 40244040a7ac, multi-socket configuration with plic is
> > broken as the hartid for second socket is calculated incorrectly.
> > The hartid stored in addr_config alrea
On Mon, Jul 4, 2022 at 8:19 AM Weiwei Li wrote:
>
>
> 在 2022/6/21 上午7:15, Atish Patra 写道:
>
> All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
> as a unified counter. Thus, the predicate function doesn't need handle each
> case separately.
>
> Simplify the predicate funct
On Mon, Jul 4, 2022 at 5:38 PM Weiwei Li wrote:
>
>
> 在 2022/7/4 下午11:26, Weiwei Li 写道:
> >
> > 在 2022/6/21 上午7:15, Atish Patra 写道:
> >> The RISC-V privilege specification provides flexibility to implement
> >> any number of counters from 29 programmable counters. However, the QEMU
> >> implements
On Mon, Jul 4, 2022 at 8:31 AM Weiwei Li wrote:
>
>
> 在 2022/6/21 上午7:15, Atish Patra 写道:
> > From: Atish Patra
> >
> > As per the privilege specification v1.11, mcountinhibit allows to start/stop
> > a pmu counter selectively.
> >
> > Reviewed-by: Bin Meng
> > Reviewed-by: Alistair Francis
> >
On Mon, Jul 4, 2022 at 6:31 PM Weiwei Li wrote:
>
>
> 在 2022/6/21 上午7:15, Atish Patra 写道:
>
> The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
> and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
> extension allows the perf to handle overflow interrupts and filter
On Wed, Jun 22, 2022 at 9:15 PM Alistair Francis wrote:
>
> On Wed, Jun 8, 2022 at 4:41 PM Bin Meng wrote:
> >
> > +Atish
> >
> > On Wed, Jun 8, 2022 at 2:20 PM Alistair Francis
> > wrote:
> > >
> > > From: Alistair Francis
> > >
> > > We previously stored the device tree at a 16MB alignment fr
On Wed, Jun 8, 2022 at 12:19 AM Alistair Francis wrote:
>
> On Mon, Jun 6, 2022 at 2:23 AM Atish Patra wrote:
> >
> > On Thu, Jun 2, 2022 at 12:02 AM Alistair Francis
> > wrote:
> > >
> > > On Wed, Jun 1, 2022 at 4:16 AM Atish Patra wrote:
> > > >
> > > > stimecmp allows the supervisor mode to
On Thu, May 26, 2022 at 7:07 PM Alistair Francis wrote:
>
> On Thu, May 26, 2022 at 5:16 PM Atish Patra wrote:
> >
> > On Wed, May 25, 2022 at 10:11 PM Alistair Francis
> > wrote:
> > >
> > > On Sat, May 14, 2022 at 4:39 AM Atish Patra wrote:
> > > >
> > > > stimecmp allows the supervisor mode
On Wed, May 18, 2022 at 3:46 AM Peter Maydell wrote:
>
> On Wed, 18 May 2022 at 09:25, Daniel P. Berrangé wrote:
> > The fact that RISC-V ecosystem is so young & has relatively few
> > users, and even fewer expecting long term stability, is precisely
> > why we should just modify the existing 'v
On Thu, May 12, 2022 at 11:29 PM Frank Chang wrote:
>
> On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote:
>>
>> From: Atish Patra
>>
>> mcycle/minstret are actually WARL registers and can be written with any
>> given value. With SBI PMU extension, it will be used to store a initial
>> value pro
On Wed, May 11, 2022 at 9:48 PM Anup Patel wrote:
>
> On Tue, May 10, 2022 at 3:03 AM Atish Patra wrote:
> >
> > vstimecmp CSR allows the guest OS or to program the next guest timer
> > interrupt directly. Thus, hypervisor no longer need to inject the
> > timer interrupt to the guest if vstimecmp
On Fri, May 6, 2022 at 4:00 AM Peter Maydell wrote:
>
> On Fri, 6 May 2022 at 09:18, Daniel P. Berrangé wrote:
> >
> > On Fri, May 06, 2022 at 06:34:47AM +1000, Alistair Francis wrote:
> > > Even if we didn't worry about backwards compatibility the current virt
> > > machine would still be what m
On Thu, May 5, 2022 at 1:35 PM Alistair Francis wrote:
>
> On Thu, May 5, 2022 at 8:04 PM Daniel P. Berrangé wrote:
> >
> > On Thu, May 05, 2022 at 07:36:51PM +1000, Alistair Francis wrote:
> > > On Tue, May 3, 2022 at 5:57 PM Atish Patra wrote:
> > > >
> > > > On Tue, Apr 19, 2022 at 5:26 PM At
On Thu, May 5, 2022 at 2:37 AM Alistair Francis wrote:
>
> On Tue, May 3, 2022 at 5:57 PM Atish Patra wrote:
> >
> > On Tue, Apr 19, 2022 at 5:26 PM Atish Patra wrote:
> > >
> > > On Tue, Apr 19, 2022 at 9:51 AM Daniel P. Berrangé
> > > wrote:
> > > >
> > > > On Mon, Apr 11, 2022 at 07:10:06PM
On Tue, Apr 26, 2022 at 5:50 PM Richard Henderson
wrote:
>
> On 4/26/22 16:08, Atish Patra wrote:
> > +.num_offset = vmstate_offset_value(_state, _field_num, uint32_t),\
> ...
> > } else if (field->flags & VMS_VARRAY_UINT32) {
> > n_elems = *(uint32_t *)(opaque + field->num_off
On Tue, Apr 26, 2022 at 5:50 PM Richard Henderson
wrote:
>
> On 4/26/22 16:08, Atish Patra wrote:
> > @@ -334,7 +334,6 @@ const VMStateDescription vmstate_riscv_cpu = {
> > VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> > VMSTATE_UINT64(env.mfromhost, RISCVCPU),
> > VMSTAT
On Wed, Apr 13, 2022 at 12:08 AM Alistair Francis wrote:
>
> On Thu, Mar 31, 2022 at 10:19 AM Atish Patra wrote:
> >
> > The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
> > and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
> > extension allows the perf to handl
On Tue, Mar 15, 2022 at 2:17 AM Bin Meng wrote:
>
> On Tue, Mar 15, 2022 at 7:43 AM Atish Patra wrote:
> >
> > The Linux kernel parses the ISA extensions from "riscv,isa" DT
> > property. It used to parse only the single letter base extensions
> > until now. A generic ISA extension parsing framew
On Wed, Mar 9, 2022 at 5:47 AM Frank Chang wrote:
>
> Atish Patra 於 2022年3月9日 週三 上午8:53寫道：
>>
>> The Linux kernel parses the ISA extensions from "riscv,isa" DT
>> property. It used to parse only the single letter base extensions
>> until now. A generic ISA extension parsing framework was proposed
On Sat, Mar 5, 2022 at 9:36 PM Frank Chang wrote:
> On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra
> wrote:
>
>>
>>
>> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stuebner wrote:
>>
>>> Hi,
>>>
>>> Am Donnerstag, 3. März 2022, 19:58:38
On Sat, Mar 5, 2022 at 10:05 AM Heiko Stuebner wrote:
> Hi,
>
> Am Donnerstag, 3. März 2022, 19:58:38 CET schrieb Atish Patra:
> > On Fri, Feb 25, 2022 at 11:46 PM Frank Chang
> wrote:
> > > Atish Patra 於 2022年2月23日 週三 上午6:39寫道：
> > >>
> > >> The Linux kernel parses the ISA extensions from "ris
fa
On Wed, Mar 2, 2022 at 2:37 PM Alistair Francis wrote:
>
> On Sat, Feb 19, 2022 at 10:31 AM Atish Patra wrote:
> >
> > The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
> > and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
> > extension allows the perf to ha
On Mon, Feb 28, 2022 at 10:14 PM Alistair Francis wrote:
>
> On Sat, Feb 19, 2022 at 10:32 AM Atish Patra wrote:
> >
> > From: Atish Patra
> >
> > mcycle/minstret are actually WARL registers and can be written with any
> > given value. With SBI PMU extension, it will be used to store a initial
>
On Wed, Mar 2, 2022 at 9:22 PM Alistair Francis wrote:
>
> On Sat, Feb 19, 2022 at 10:34 AM Atish Patra wrote:
> >
> > From: Atish Patra
> >
> > The predicate function calculates the counter index incorrectly for
> > hpmcounterx. Fix the counter index to reflect correct CSR number.
> >
> > Fixes
On Thu, Feb 3, 2022 at 4:23 AM Heiko Stübner wrote:
> Hi Atish,
>
> Am Donnerstag, 20. Januar 2022, 21:07:34 CET schrieb Atish Patra:
> > The RISC-V privileged specification v1.12 defines few execution
> > environment configuration CSRs that can be used enable/disable
> > extensions per privilege
On Fri, Jan 28, 2022 at 5:50 PM angell1518 wrote:
>
> 在 2022/1/29 上午9:28, Atish Patra 写道:
>
>
>
> On Wed, Jan 26, 2022 at 12:37 AM Weiwei Li wrote:
>
>>
>> 在 2022/1/21 上午4:07, Atish Patra 写道:
>> > The RISC-V privileged specification v1.12 defines few execution
>> > environment configuration CSRs
On Sun, Jan 23, 2022 at 11:59 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 1/21/22 7:07 AM, Atish Patra wrote:
> > Add the definition for ratified privileged specification version v1.12
> >
> > Signed-off-by: Atish Patra
> > ---
> > target/riscv/cpu.h | 1 +
> > 1 file chan
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