On Fri, 4 Jan 2019 09:17:41 +0100
Sascha Hauer wrote:
> On Fri, Jan 04, 2019 at 01:56:41AM +0300, Antony Pavlov wrote:
> > Hi Sascha!
> >
> > I have some good news and some bad news.
> >
> > First the good news.
> >
> > Barebox was used for Day
gestion?
--
Best regards,
Antony Pavlov
On Tue, 8 May 2018 00:08:38 +0300
Antony Pavlov wrote:
Please comment this patch!
> The RISC-V Instruction Set Manual, Volume II:
> Privileged Architecture, Version 1.10 states
> that upon reset the pc is set to
> an implementation-defined reset vector
> (see chapter 3.3 Re
operty
for TYPE_RISCV_HART_ARRAY.
Signed-off-by: Antony Pavlov
Cc: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Peter Crosthwaite
Cc: Peter Maydell
---
hw/riscv/riscv_hart.c | 3 +++
include/hw/riscv/riscv_hart.h | 1 +
target/riscv/cpu.c
On Tue, 10 Apr 2018 08:17:32 +0200
Thomas Huth wrote:
> On 10.04.2018 05:21, Antony Pavlov wrote:
> > On Sat, 3 Mar 2018 02:51:47 +1300
> > Michael Clark wrote:
> >
> >> QEMU model of the UART on the SiFive E300 and U500 series SOCs.
> >> BBL supports t
+};
> +
> +enum {
> +SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */
> +SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */
> +};
> +
> +#define TYPE_SIFIVE_UART "riscv.sifive.uart"
> +
> +#define SIFIVE_UART(obj) \
> +OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART)
> +
> +typedef struct SiFiveUARTState {
> +/*< private >*/
> +SysBusDevice parent_obj;
You use SysBusDevive in this header file but there is no 'include
"hw/sysbus.h"' in the header file itself.
Please see my comment
https://github.com/riscv/riscv-qemu/pull/130#issuecomment-379640538
> +/*< public >*/
> +qemu_irq irq;
> +MemoryRegion mmio;
> +CharBackend chr;
Just the same thing. CharBackend is defined in "chardev/char-fe.h" please
include it.
> +uint8_t rx_fifo[8];
> +unsigned int rx_fifo_len;
> +uint32_t ie;
> +uint32_t ip;
> +uint32_t txctrl;
> +uint32_t rxctrl;
> +uint32_t div;
> +} SiFiveUARTState;
> +
> +SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
> +Chardev *chr, qemu_irq irq);
> +
> +#endif
> --
> 2.7.0
>
>
--
Best regards,
Antony Pavlov
VE_E300_DTIM] = { 0x8000, 0x4000 }
> +};
> +
> +static uint64_t identity_translate(void *opaque, uint64_t addr)
> +{
> +return addr;
> +}
> +
> +static uint64_t load_kernel(const char *kernel_filename)
> +{
> +uint64_t kernel_entry, kernel_high;
> +
> +if (load_elf(kernel_filename, identity_translate, NULL,
> + &kernel_entry, NULL, &kernel_high,
> + /* little_endian = */ 0, ELF_MACHINE, 1, 0) < 0) {
"little_endian =" is misleading.
Actually it's "big_endian = 0".
The same comment is present in the U500 code.
--
Best regards,
Antony Pavlov
, uint32_t num_priorities,
> +uint32_t priority_base, uint32_t pending_base,
> +uint32_t enable_base, uint32_t enable_stride,
> +uint32_t context_base, uint32_t context_stride,
> +uint32_t aperture_size);
> +
> +#endif
> +
> --
> 2.7.0
'git am' reports on 'new blank line at EOF' here
(include/hw/riscv/sifive_plic.h):
Applying: SiFive RISC-V PLIC Block
.git/rebase-apply/patch:664: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
--
Best regards,
Antony Pavlov
t SiFiveE300State {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +
> +/*< public >*/
> +RISCVHartArrayState soc;
I suppose that name 'soc' is misleading because it contain only CPU
core-related information
but it does not contain any SoC-related information.
> +DeviceState *plic;
> +} SiFiveE300State;
> +
--
Best regards,
Antony Pavlov
e/hw/riscv/riscv_hart.h
@@ -27,6 +27,10 @@
#ifndef HW_RISCV_HART_H
#define HW_RISCV_HART_H
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "target/riscv/cpu.h"
+
#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
#define RISCV_HART_ARRAY(obj) \
Some files in include/hw/riscv/ are affected by this problem (e.g.
sifive_uart.h).
--
Best regards,
Antony Pavlov
,
> +SIFIVE_UART_DIV = 24,
> +SIFIVE_UART_MAX = 32
> +};
> +
> +enum {
> +SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */
> +SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */
> +};
> +
> +enum {
> +SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */
> +SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */
> +};
> +
> +#define TYPE_SIFIVE_UART "riscv.sifive.uart"
> +
> +#define SIFIVE_UART(obj) \
> +OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART)
> +
> +typedef struct SiFiveUARTState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +
> +/*< public >*/
> +qemu_irq irq;
> +MemoryRegion mmio;
> +CharBackend chr;
> +uint8_t rx_fifo[8];
> +unsigned int rx_fifo_len;
> +uint32_t ie;
> +uint32_t ip;
> +uint32_t txctrl;
> +uint32_t rxctrl;
> +uint32_t div;
> +} SiFiveUARTState;
> +
> +SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
> +Chardev *chr, qemu_irq irq);
> +
> +#endif
> --
> 2.7.0
>
>
--
Best regards,
Antony Pavlov
On Thu, 4 Jan 2018 20:33:57 +1300
Michael Clark wrote:
> On Thu, Jan 4, 2018 at 7:47 PM, Antony Pavlov
> wrote:
>
> > On Wed, 3 Jan 2018 13:44:07 +1300
> > Michael Clark wrote:
> >
> > > Add CPU state header, CPU definitions and initialization routine
-y += sifive_prci.o
obj-y += sifive_plic.o
-obj-y += sifive_u500.o
+obj-$(CONFIG_SIFIVE_U500) += sifive_u500.o
obj-y += sifive_uart.o
obj-y += spike_v1_09.o
obj-y += spike_v1_10.o
--
Best regards,
Antony Pavlov
IP_MSIP(1 << IRQ_M_SOFT)
> +#define MIP_STIP (1 << IRQ_S_TIMER)
> +#define MIP_HTIP(1 << IRQ_H_TIMER)
> +#define MIP_MTIP(1 << IRQ_M_TIMER)
> +#define MIP_SEIP(1 << IRQ_S_EXT)
> +#define MIP_HEIP(1 << IRQ_H_EXT)
> +#define MIP_MEIP(1 << IRQ_M_EXT)
> +
> +#define SIP_SSIP MIP_SSIP
> +#define SIP_STIP MIP_STIP
> +#define SIP_SEIP MIP_SEIP
> +
> +#define PRV_U 0
> +#define PRV_S 1
> +#define PRV_H 2
> +#define PRV_M 3
> +
> +/* privileged ISA 1.9.1 VM modes (mstatus.vm) */
> +#define VM_1_09_MBARE 0
> +#define VM_1_09_MBB 1
> +#define VM_1_09_MBBID 2
> +#define VM_1_09_SV32 8
> +#define VM_1_09_SV39 9
> +#define VM_1_09_SV48 10
> +
> +/* privileged ISA 1.10.0 VM modes (satp.mode) */
> +#define VM_1_10_MBARE 0
> +#define VM_1_10_SV32 1
> +#define VM_1_10_SV39 8
> +#define VM_1_10_SV48 9
> +#define VM_1_10_SV57 10
> +#define VM_1_10_SV64 11
> +
> +/* privileged ISA interrupt causes */
> +#define IRQ_U_SOFT 0 /* since: priv-1.10 */
> +#define IRQ_S_SOFT 1
> +#define IRQ_H_SOFT 2 /* until: priv-1.9.1 */
> +#define IRQ_M_SOFT 3 /* until: priv-1.9.1 */
> +#define IRQ_U_TIMER 4 /* since: priv-1.10 */
> +#define IRQ_S_TIMER 5
> +#define IRQ_H_TIMER 6 /* until: priv-1.9.1 */
> +#define IRQ_M_TIMER 7 /* until: priv-1.9.1 */
> +#define IRQ_U_EXT 8 /* since: priv-1.10 */
> +#define IRQ_S_EXT 9
> +#define IRQ_H_EXT 10 /* until: priv-1.9.1 */
> +#define IRQ_M_EXT 11 /* until: priv-1.9.1 */
> +#define IRQ_X_COP 12 /* non-standard */
> +#define IRQ_X_HOST 13 /* non-standard */
> +
> +/* Default addresses */
> +#define DEFAULT_RSTVEC 0x1000
> +#define DEFAULT_NMIVEC 0x1004
> +#define DEFAULT_MTVEC 0x1010
> +#define CONFIG_STRING_ADDR 0x100C
> +#define EXT_IO_BASE0x4000
> +#define DRAM_BASE 0x8000
> +
> +/* RV32 satp field masks */
> +#define SATP32_MODE 0x8000
> +#define SATP32_ASID 0x7fc0
> +#define SATP32_PPN 0x003f
> +
> +/* RV64 satp field masks */
> +#define SATP64_MODE 0xF000
> +#define SATP64_ASID 0x0000
> +#define SATP64_PPN 0x0FFF
> +
> +#if defined(TARGET_RISCV32)
> +#define SATP_MODE SATP32_MODE
> +#define SATP_ASID SATP32_ASID
> +#define SATP_PPN SATP32_PPN
> +#endif
> +#if defined(TARGET_RISCV64)
> +#define SATP_MODE SATP64_MODE
> +#define SATP_ASID SATP64_ASID
> +#define SATP_PPN SATP64_PPN
> +#endif
> +
> +/* breakpoint control fields */
> +#define BPCONTROL_X 0x0001
> +#define BPCONTROL_W 0x0002
> +#define BPCONTROL_R 0x0004
> +#define BPCONTROL_U 0x0008
> +#define BPCONTROL_S 0x0010
> +#define BPCONTROL_H 0x0020
> +#define BPCONTROL_M 0x0040
> +#define BPCONTROL_BPMATCH 0x0780
> +#define BPCONTROL_BPAMASKMAX 0x0F80
> +#define BPCONTROL_TDRTYPE0xF000
> +
> +/* page table entry (PTE) fields */
> +#define PTE_V 0x001 /* Valid */
> +#define PTE_R 0x002 /* Read */
> +#define PTE_W 0x004 /* Write */
> +#define PTE_X 0x008 /* Execute */
> +#define PTE_U 0x010 /* User */
> +#define PTE_G 0x020 /* Global */
> +#define PTE_A 0x040 /* Accessed */
> +#define PTE_D 0x080 /* Dirty */
> +#define PTE_SOFT 0x300 /* Reserved for Software */
> +
> +#define PTE_PPN_SHIFT 10
> +
> +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
> +/* end Spike decode.h, encoding.h section */
> --
> 2.7.0
>
>
--
Best regards,
Antony Pavlov
On Mon, 6 Jul 2015 11:58:54 -0700
Serge Vakulenko wrote:
> On Mon, Jul 6, 2015 at 12:33 AM, Antony Pavlov
> wrote:
> > On Sun, 5 Jul 2015 21:18:11 -0700
> > Serge Vakulenko wrote:
> >
> >> On Wed, Jul 1, 2015 at 6:41 AM, Aurelien Jarno
> >> wrote:
&
ter_machine(&pic32_board[0]);
> +qemu_register_machine(&pic32_board[1]);
> +qemu_register_machine(&pic32_board[2]);
Use cycle and ARRAY_SIZE() here (see again mips_defs[] handling).
> +}
> +
> +type_init(pic32_register_types)
> +machine_init(pic32_machine_init);
> --
> 2.2.2
>
>
--
--
Best regards,
Antony Pavlov
On Sun, 5 Jul 2015 21:27:04 -0700
Serge Vakulenko wrote:
> On Wed, Jul 1, 2015 at 10:56 PM, Antony Pavlov
> wrote:
> > On Tue, 30 Jun 2015 21:12:34 -0700
> > Serge Vakulenko wrote:
> >
> >> Signed-off-by: Serge Vakulenko
> >> ---
> >>
mode 100644 hw/mips/pic32_spi.c
> >> create mode 100644 hw/mips/pic32_uart.c
> >> create mode 100644 hw/mips/pic32mx.h
> >> create mode 100644 hw/mips/pic32mz.h
> >
> > This patch is huge, and needs to be splitted to ease the review.
>
> I'll prepare a new patch set, with every new file put into a separate
> message. Other issues fixed as well.
Putting every new file into a separate message is a nonsense.
Please separate __logical changes__ into a single patch.
--
Best regards,
Antony Pavlov
9df 100644
> --- a/hw/mips/cputimer.c
> +++ b/hw/mips/cputimer.c
> @@ -25,21 +25,13 @@
> #include "qemu/timer.h"
> #include "sysemu/kvm.h"
>
> -#define TIMER_FREQ 100 * 1000 * 1000
> -
This is a part of the 'Speed of MIPS CPU timer made configurable per platform.'
patch.
--
Best regards,
Antony Pavlov
; + */
> +
> +/* Only 32-bit little endian mode supported. */
> +#include "config.h"
> +#if !defined TARGET_MIPS64 && !defined TARGET_WORDS_BIGENDIAN
Please don't use C preprocessor directive for conditional compilation of the
whole file.
Use Makefile instead. See CONFIG_FULONG for example (fulong2e is mips64le-only).
--
Best regards,
Antony Pavlov
terrupt controller (EIC) mode.
> Two new processor variants: M4K and microAptivP.
> Two new machine platforms: pic32mz7 and pic32mz.
Please fix your subject lines according to "Write a good commit message" section
of http://wiki.qemu.org/Contribute/SubmitAPatch.
Also please use the imperative mood in the subject line.
--
Best regards,
Antony Pavlov
ng fixes the problem.
Signed-off-by: Antony Pavlov
Acked-by: Alexander Graf
---
Changes since v3:
* rebase over latest 'master';
* add 'Acked-by: Alexander Graf' tag; see
http://lists.gnu.org/archive/html/qemu-devel/2014-11/msg01051.html;
* drop unicore32; here is gcc 4.9
Signed-off-by: Antony Pavlov
---
hw/block/pflash_cfi02.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index 8513a17..389b4aa 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
@@ -744,6 +744,7 @@ static void
fault() messages appears on enabling ANY
> > logging! It's not very handy.
> >
> > Adding separate log category for *_cpu_handle_mmu_fault()
> > logging fixes the problem.
> >
> > Signed-off-by: Antony Pavlov
>
> Have you benchmarked the perform
ng fixes the problem.
Signed-off-by: Antony Pavlov
---
Changes since v2:
* fix target-ppc/mmu-hash64.c and target-ppc/mmu_helper.c too;
* drop LOG_MMU wrapping macros: compile-in qemu_log_mask() always;
* use VADDR_PRIx for fixing this microblaze warning:
CCmicroblazeel-softm
ng fixes the problem.
Signed-off-by: Antony Pavlov
---
Changes since v1:
* add cris, i386, microblaze, ppc, s390x, sparc and unicore32 support.
---
cputlb.c | 3 ++-
include/qemu/log.h | 1 +
qemu-log.c | 2 ++
target-cris/helper.c | 12 +
ng fixes the problem.
Signed-off-by: Antony Pavlov
---
include/qemu/log.h | 1 +
qemu-log.c | 2 ++
target-mips/helper.c | 6 --
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/qemu/log.h b/include/qemu/log.h
index d515424..195f665 100644
--- a/include/qemu
n or CHDK;
* barebox.
I know nothing about MPU fault handling in barebox.
I'm planning to merge current qemu DIGIC support with patches from MagicLantern
qemu patches.
May be during this work I'll be capable to answer your question, but just now I
have no answer, sorry.
May be Magic Lantern people (especiall g3gg0) can help? I have added them to
Cc.
--
Best regards,
Antony Pavlov
http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg00923.html
--
Best regards,
Antony Pavlov
Signed-off-by: Antony Pavlov
Reviewed-by: Richard Henderson
Reviewed-by: Andreas Färber
---
hw/mips/mips_malta.c | 25 +
include/hw/mips/bios.h | 3 ++-
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index
The sizes.h macros is an easy-to-read method of
power-of-two memory sizes representation. The sizes.h
macros are actively used in the linux kernel and other
projects, so let's use them in QEMU too.
Antony Pavlov (2):
include/qemu: introduce sizes.h
hw/mips: use sizes.h macros
hw
The header file sizes.h is used in linux kernel,
barebox bootloader and u-boot bootloader. It provides
short and easy-to-read names for power-of-two
numbers. The numbers like this are othen used
for memory range sizes.
Signed-off-by: Antony Pavlov
Reviewed-by: Richard Henderson
Reviewed-by
On Mon, 16 Dec 2013 00:04:18 +0100
Andreas Färber wrote:
> Hi,
>
> Am 13.12.2013 22:42, schrieb Antony Pavlov:
> > Also this patch adds initial support for Canon
> > PowerShot A1100 IS compact camera.
> >
> > Signed-off-by: Antony Pavlov
> > ---
> &
On Sat, 14 Dec 2013 16:41:44 +1000
Peter Crosthwaite wrote:
> On Sat, Dec 14, 2013 at 7:42 AM, Antony Pavlov
> wrote:
> > Signed-off-by: Antony Pavlov
> > ---
> > hw/arm/digic.c | 28 +
> > hw/timer/Makefile.objs | 1 +
>
Signed-off-by: Antony Pavlov
---
hw/arm/digic_boards.c | 70 +++
1 file changed, 70 insertions(+)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 87a9c4b..217c506 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
Signed-off-by: Antony Pavlov
Reviewed-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
hw/arm/digic.c | 16
hw/char/Makefile.objs| 1 +
hw/char/digic-uart.c | 195 +++
include/hw/arm/digic.h | 2
Signed-off-by: Antony Pavlov
Reviewed-by: Peter Crosthwaite
---
hw/arm/digic.c | 28 +++
hw/timer/Makefile.objs | 1 +
hw/timer/digic-timer.c | 163 +
include/hw/arm/digic.h | 6 ++
include/hw/timer/digic
Also this patch adds initial support for Canon
PowerShot A1100 IS compact camera.
Signed-off-by: Antony Pavlov
---
hw/arm/Makefile.objs | 1 +
hw/arm/digic_boards.c | 84 +++
2 files changed, 85 insertions(+)
create mode 100644 hw/arm
(http://www.magiclantern.fm) projects
contributors.
Signed-off-by: Antony Pavlov
Reviewed-by: Andreas Färber
Reviewed-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/digic.c
Signed-off-by: Antony Pavlov
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f45d1d..1fce9a5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -233,6 +233,12 @@ S: Supported
F: hw/arm/highbank.c
F: hw/net/xgmac.c
+Canon DIGIC
+M: Antony
[PATCH v9 1/6] hw/arm: add very initial support for Canon DIGIC SoC
[PATCH v9 2/6] hw/arm/digic: prepare DIGIC-based boards support
[PATCH v9 3/6] hw/arm/digic: add timer support
[PATCH v9 4/6] hw/arm/digic: add UART support
[PATCH v9 5/6] hw/arm/digic: add NOR ROM support
[PATCH v9 6/6] MAINTAINER
On Sun, 15 Dec 2013 09:06:30 +1000
Peter Crosthwaite wrote:
> On Sat, Dec 14, 2013 at 6:26 AM, Antony Pavlov
> wrote:
> > Hi, Andreas!
> >
> > Here is a quote from http://wiki.qemu.org/QOMConventions
> >
> >> a FooClass structure definition containin
[PATCH v8 1/6] hw/arm: add very initial support for Canon DIGIC SoC
[PATCH v8 2/6] hw/arm/digic: prepare DIGIC-based boards support
[PATCH v8 3/6] hw/arm/digic: add timer support
[PATCH v8 4/6] hw/arm/digic: add UART support
[PATCH v8 5/6] hw/arm/digic: add NOR ROM support
[PATCH v8 6/6] MAINTAINER
Signed-off-by: Antony Pavlov
---
hw/arm/digic_boards.c | 70 +++
1 file changed, 70 insertions(+)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 87a9c4b..217c506 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
Signed-off-by: Antony Pavlov
Reviewed-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
hw/arm/digic.c | 16
hw/char/Makefile.objs | 1 +
hw/char/digic-uart.c | 195 +
hw/char/digic-uart.h | 45
include/hw
Signed-off-by: Antony Pavlov
---
hw/arm/digic.c | 28 +
hw/timer/Makefile.objs | 1 +
hw/timer/digic-timer.c | 168 +
hw/timer/digic-timer.h | 38 +++
include/hw/arm/digic.h | 6 ++
5 files changed, 241 insertions
(http://www.magiclantern.fm) projects
contributors.
Signed-off-by: Antony Pavlov
Reviewed-by: Andreas Färber
Reviewed-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/digic.c
Also this patch adds initial support for Canon
PowerShot A1100 IS compact camera.
Signed-off-by: Antony Pavlov
---
hw/arm/Makefile.objs | 1 +
hw/arm/digic_boards.c | 84 +++
2 files changed, 85 insertions(+)
create mode 100644 hw/arm
Signed-off-by: Antony Pavlov
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f45d1d..1fce9a5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -233,6 +233,12 @@ S: Supported
F: hw/arm/highbank.c
F: hw/net/xgmac.c
+Canon DIGIC
+M: Antony
t; public >*/
>
> [any fields you need]
> } FooClass;
What do the "< private >" and "< public >" comments exactly mean here?
--
Best regards,
Antony Pavlov
> +#define AW_A10_PIT_TIMER_RELOAD0x2
> +#define AW_A10_PIT_TIMER_MODE 0x80
> +
> +#define AW_A10_PIT_TIMER_INTERVAL 0x4
> +#define AW_A10_PIT_TIMER_COUNT 0x8
> +#define AW_A10_PIT_WDOG_CONTROL0x90
> +#define AW_A10_PIT_WDOG_MODE 0x94
> +
> +#define AW_A10_PIT_COUNT_CTL 0xa0
> +#define AW_A10_PIT_COUNT_RL_EN 0x2
> +#define AW_A10_PIT_COUNT_CLR_EN0x1
> +#define AW_A10_PIT_COUNT_LO0xa4
> +#define AW_A10_PIT_COUNT_HI0xa8
> +
> +#define AW_A10_PIT_TIMER_BASE 0x10
> +#define AW_A10_PIT_TIMER_BASE_END \
> +(AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT)
> +
> +#define AW_A10_PIT_DEFAULT_CLOCK 0x4
> +
> +typedef struct AwA10PITState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +/*< public >*/
> +qemu_irq irq[AW_A10_PIT_TIMER_NR];
> +ptimer_state * timer[AW_A10_PIT_TIMER_NR];
> +MemoryRegion iomem;
> +
> +uint32_t irq_enable;
please fix extra whitespaces here.
> +uint32_t irq_status;
> +uint32_t control[AW_A10_PIT_TIMER_NR];
> +uint32_t interval[AW_A10_PIT_TIMER_NR];
> +uint32_t count[AW_A10_PIT_TIMER_NR];
> +uint32_t watch_dog_mode;
> +uint32_t watch_dog_control;
> +uint32_t count_lo;
> +uint32_t count_hi;
> +uint32_t count_ctl;
> +} AwA10PITState;
> +
> +#endif
> +
And here.
> --
> 1.7.2.5
>
>
--
Best regards,
Antony Pavlov
On Fri, 13 Dec 2013 09:20:27 +1000
Peter Crosthwaite wrote:
> On Fri, Dec 13, 2013 at 8:23 AM, Antony Pavlov
> wrote:
> > Signed-off-by: Antony Pavlov
> > Reviewed-by: Peter Maydell
> > ---
> > hw/arm/digic.c | 28 ++
> > hw/timer/Makef
Signed-off-by: Antony Pavlov
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7eed206..02ad9fb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -233,6 +233,12 @@ S: Supported
F: hw/arm/highbank.c
F: hw/net/xgmac.c
+Canon DIGIC
+M: Antony
Signed-off-by: Antony Pavlov
---
hw/arm/digic_boards.c | 70 +++
1 file changed, 70 insertions(+)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 20c8054..ad62c7e 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
Signed-off-by: Antony Pavlov
Reviewed-by: Peter Maydell
---
hw/arm/digic.c | 16
hw/char/Makefile.objs | 1 +
hw/char/digic-uart.c | 195 +
hw/char/digic-uart.h | 45
include/hw/arm/digic.h | 2 +
5 files
(http://www.magiclantern.fm) projects
contributors.
Signed-off-by: Antony Pavlov
Reviewed-by: Andreas Färber
Reviewed-by: Peter Maydell
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/digic.c | 71 +
in
Signed-off-by: Antony Pavlov
Reviewed-by: Peter Maydell
---
hw/arm/digic.c | 28 ++
hw/timer/Makefile.objs | 1 +
hw/timer/digic-timer.c | 140 +
hw/timer/digic-timer.h | 36 +
include/hw/arm/digic.h | 6 +++
5
Also this patch adds initial support for Canon
PowerShot A1100 IS compact camera.
Signed-off-by: Antony Pavlov
---
hw/arm/Makefile.objs | 1 +
hw/arm/digic_boards.c | 83 +++
2 files changed, 84 insertions(+)
create mode 100644 hw/arm
[PATCH v7 1/6] hw/arm: add very initial support for Canon DIGIC SoC
[PATCH v7 2/6] hw/arm/digic: prepare DIGIC-based boards support
[PATCH v7 3/6] hw/arm/digic: add timer support
[PATCH v7 4/6] hw/arm/digic: add UART support
[PATCH v7 5/6] hw/arm/digic: add NOR ROM support
[PATCH v7 6/6] MAINTAINER
Signed-off-by: Antony Pavlov
---
target-arm/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index b60e3fc..b6199c5 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -120,6 +120,11 @@ static void arm_cpu_reset(CPUState *s)
env
[RFC v2 1/2] ARM: cpu: add "reset_hivecs" property (high vectors on
[RFC v2 2/2] ARM: arm_cpu_reset: make possible to use high vectors
Changes since v1:
* rebase over Peter Crosthwaite's "Fix Support for ARM A9 CBAR" v3 series;
* rewrite according to Peter Crosthwaite's and Peter Maydell's comme
Signed-off-by: Antony Pavlov
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 24
2 files changed, 25 insertions(+)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index b55306a..116320c 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
On Sat, 7 Dec 2013 11:08:40 +1000
Peter Crosthwaite wrote:
> On Sat, Dec 7, 2013 at 10:55 AM, Antony Pavlov
> wrote:
> > Signed-off-by: Antony Pavlov
> > ---
> > target-arm/cpu.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/tar
On Sat, 7 Dec 2013 11:00:05 +1000
Peter Crosthwaite wrote:
> On Sat, Dec 7, 2013 at 10:55 AM, Antony Pavlov
> wrote:
> > Signed-off-by: Antony Pavlov
> > ---
> > target-arm/cpu-qom.h | 1 +
> > target-arm/cpu.c | 13 +
> > 2 files changed,
On Fri, 06 Dec 2013 22:59:29 +0400
Michael Tokarev wrote:
> 04.12.2013 10:27, Antony Pavlov wrote:
> > scripts/checkpatch.pl reports about some style problems,
> > this commit fixes some of them:
>
> Thanks, applied to trivial-patches queue.
>
> I'm a bit afraid
Signed-off-by: Antony Pavlov
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index f838499..6f548c7 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -126,6 +126,10 @@ static void arm_cpu_reset(CPUState *s)
env
[RFC 1/2] ARM: cpu: add "hivecs" property (high vectors on reset)
[RFC 2/2] ARM: arm_cpu_reset: make possible to use high vectors for
Signed-off-by: Antony Pavlov
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 13 +
2 files changed, 14 insertions(+)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index b55306a..116320c 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -128,6 +128,7
On Wed, 4 Dec 2013 20:29:05 +
Peter Maydell wrote:
> On 4 December 2013 20:22, Antony Pavlov wrote:
> > Here is my proposition:
> >
> > 1. qemu board code setup CPU to start from 0x. (0x is a ROM
> > address
> > on DIGIC chips)
>
>
27;jump-to-beginning-of-ROM' instruction to 0x.
(We can't put barebox to 0x as barebox image is bigger that 64K.)
There is at least two possibilities to do so:
* we can use specially prepared ROM image;
* qemu board code can insert by itself a 'jump-to-beginning-of-ROM' instruction
after loading ROM image (as qemu MIPS Malta board code does).
3. CPU starts as usual. Branching to barebox code in ROM happends in a natural
way!
Please comment my proposition.
--
Best regards,
Antony Pavlov
On Thu, 28 Nov 2013 18:08:32 +0100
Stefan Weil wrote:
> Am 28.11.2013 07:29, schrieb Antony Pavlov:
> > Signed-off-by: Antony Pavlov
> > Reviewed-by: Richard Henderson
> > ---
> > hw/mips/mips_malta.c | 25 +
> > include/hw/mips/bio
On Thu, 28 Nov 2013 15:27:18 +0100
Andreas Färber wrote:
> Am 28.11.2013 07:29, schrieb Antony Pavlov:
> > Signed-off-by: Antony Pavlov
> > Reviewed-by: Richard Henderson
>
> Are the int -> long changes caused by the BIT() macro usage? Otherwise I
> would'
o
> >comments, include it here.
>
> Hi Anthony, Hi Blue,
>
> please discard this pull request. There was some feedback, i wasn't getting
> before. I try to make the suggested changes, sending update patches for
> reviews and after that i'll make a new pull request.
Hi!
Are you planning on pull request renewing?
--
Best regards,
Antony Pavlov
Signed-off-by: Antony Pavlov
Reviewed-by: Richard Henderson
---
hw/mips/mips_malta.c | 25 +
include/hw/mips/bios.h | 3 ++-
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 05c8771..604832f 100644
The header file sizes.h is used in linux kernel,
barebox bootloader and u-boot bootloader. It provides
the short and easy-to-read names for power-of-two
numbers. The numbers like this are othen used
for memory range sizes.
Signed-off-by: Antony Pavlov
Reviewed-by: Richard Henderson
---
include
[PATCH 1/2] include/qemu: introduce sizes.h
[PATCH 2/2] hw/mips: use sizes.h macros
The sizes.h macros is a easy-to-read method of
power-of-two memory sizes representation. The sizes.h
macros are actively used in linux kernel and other
projects, so let's use them in QEMU too.
a0: 0a004a21addit2,t2,10
>3a4: 0010b 0x3a4
>3a8: nop
>3ac: nop
>
> I expect that swr instruction in line 384 would change `addi
> t2,t2,1`0 to `nop`
> This should work because no cache is used for this memory region.
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/qemu/+bug/1248168/+subscriptions
>
--
--
Best regards,
Antony Pavlov
On Fri, 01 Nov 2013 15:18:28 +0400
Michael Tokarev wrote:
> 01.11.2013 15:14, Antony Pavlov wrote:
> > On Fri, 01 Nov 2013 14:29:24 +0400
> > Michael Tokarev wrote:
> >
> >> 29.10.2013 08:36, Antony Pavlov wrote
> >>> The following error occu
figure it?
Do you really need this "in-kernel" gdb support? As I have already write,
qemu itself has gdb server functionality support.
> --
> Best Regards,
> Yu Rong Tan
--
--
Best regards,
Antony Pavlov
Signed-off-by: Antony Pavlov
Reviewed-by: Peter Maydell
---
hw/arm/digic.c | 16
hw/char/Makefile.objs | 1 +
hw/char/digic-uart.c | 195 +
hw/char/digic-uart.h | 45
include/hw/arm/digic.h | 2 +
5 files
Signed-off-by: Antony Pavlov
---
hw/arm/digic.c | 28 ++
hw/timer/Makefile.objs | 1 +
hw/timer/digic-timer.c | 140 +
hw/timer/digic-timer.h | 36 +
include/hw/arm/digic.h | 6 +++
5 files changed, 211 insertions
Signed-off-by: Antony Pavlov
---
hw/arm/digic_boards.c | 71 +++
1 file changed, 71 insertions(+)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 77cfc81..bf6e015 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
Also this patch adds initial support for Canon
PowerShot A1100 IS compact camera.
Signed-off-by: Antony Pavlov
---
hw/arm/Makefile.objs | 1 +
hw/arm/digic_boards.c | 88 +++
2 files changed, 89 insertions(+)
create mode 100644 hw/arm
(http://www.magiclantern.fm) projects
contributors.
Signed-off-by: Antony Pavlov
Reviewed-by: Andreas Färber
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/digic.c | 65 +
include/hw/arm/digic.h
[PATCH v6 1/5] hw/arm: add very initial support for Canon DIGIC SoC
[PATCH v6 2/5] hw/arm/digic: prepare DIGIC-based boards support
[PATCH v6 3/5] hw/arm/digic: add timer support
[PATCH v6 4/5] hw/arm/digic: add UART support
[PATCH v6 5/5] hw/arm/digic: add NOR ROM support
Changes since v5:
1. re
On Tue, 24 Sep 2013 08:32:10 +0400
Antony Pavlov wrote:
ping-ping
> On Fri, 13 Sep 2013 11:33:24 +0400
> Antony Pavlov wrote:
>
> ping
>
> > Changes since v2:
> > * commit messages: drop ALL 'Reviewed-by' tags.
> > Drop Aurelien Jarno's
10 00 84 5e 01 00barebox..^..
f8400030: 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
canon> / md -b 0xf900+0x40
f900: 12 00 00 ea fe ff ff ea fe ff ff ea fe ff ff ea........
f910: fe ff ff ea fe ff ff ea fe ff ff ea fe ff ff ea
f920: 62 61 72 65 62 6f 78 00 00 00 10 00 84 5e 01 00barebox..^..
f930: 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
canon> /
--
Best regards,
Antony Pavlov
On Thu, 17 Oct 2013 18:54:28 +0100
Peter Maydell wrote:
> On 7 September 2013 08:04, Antony Pavlov wrote:
> > Signed-off-by: Antony Pavlov
> > --- a/hw/arm/digic_boards.c
> > +++ b/hw/arm/digic_boards.c
> > @@ -26,6 +26,13 @@
> > #include "hw/boards.h
/malta-linux-gnu/default
Also you can use VDE2 with qemu. See this file:
https://github.com/frantony/clab/blob/master/qemu-configs/malta-linux-gnu/vde-network
--
Best regards,
Antony Pavlov
/Kconfig
> create mode 100644 hw/scsi/Kconfig
> create mode 100644 hw/sd/Kconfig
> create mode 100644 hw/sh4/Kconfig
> create mode 100644 hw/sparc/Kconfig
> create mode 100644 hw/sparc64/Kconfig
> create mode 100644 hw/ssi/Kconfig
> create mode 100644 hw/timer/Kconfig
> create mode 100644 hw/tpm/Kconfig
> create mode 100644 hw/unicore32/Kconfig
> create mode 100644 hw/usb/Kconfig
> create mode 100644 hw/usb/hcd-ohci-pci.c
> create mode 100644 hw/usb/hcd-ohci-sysbus.c
> create mode 100644 hw/usb/hcd-ohci.h
> create mode 100644 hw/watchdog/Kconfig
> create mode 100644 hw/xtensa/Kconfig
> create mode 16 scripts/kconfig
>
> --
> 1.8.1.2
>
>
--
--
Best regards,
Antony Pavlov
On Fri, 20 Sep 2013 13:01:14 +0400
Antony Pavlov wrote:
ping-ping-ping
> On Fri, 13 Sep 2013 18:37:27 +0400
> Antony Pavlov wrote:
>
> ping-ping
>
> > On Sat, 7 Sep 2013 11:04:22 +0400
> > Antony Pavlov wrote:
> >
> > ping
> > > [RFC v5
On Fri, 13 Sep 2013 11:33:24 +0400
Antony Pavlov wrote:
ping
> Changes since v2:
> * commit messages: drop ALL 'Reviewed-by' tags.
> Drop Aurelien Jarno's tag because the patchseries
> was completely reworked, so it need additional review.
>
> Changes
On Fri, 13 Sep 2013 18:37:27 +0400
Antony Pavlov wrote:
ping-ping
> On Sat, 7 Sep 2013 11:04:22 +0400
> Antony Pavlov wrote:
>
> ping
> > [RFC v5 1/5] hw/arm: add very initial support for Canon DIGIC SoC
> > [RFC v5 2/5] hw/arm/digic: prepare DIGIC-based boards sup
On Sat, 7 Sep 2013 11:04:22 +0400
Antony Pavlov wrote:
ping
> [RFC v5 1/5] hw/arm: add very initial support for Canon DIGIC SoC
> [RFC v5 2/5] hw/arm/digic: prepare DIGIC-based boards support
> [RFC v5 3/5] hw/arm/digic: add timer support
> [RFC v5 4/5] hw/arm/digic: add UART suppo
Signed-off-by: Antony Pavlov
---
hw/mips/mips_malta.c | 25 +
include/hw/mips/bios.h | 3 ++-
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 05c8771..604832f 100644
--- a/hw/mips/mips_malta.c
+++ b/hw
Changes since v2:
* commit messages: drop ALL 'Reviewed-by' tags.
Drop Aurelien Jarno's tag because the patchseries
was completely reworked, so it need additional review.
Changes since v1:
* include/sizes.h -> include/qemu/sizes.h
* fix copyright header;
* fix formatting: drop tabs;
* use
The header file sizes.h is used in linux kernel,
barebox bootloader and u-boot bootloader. It provides
the short and easy-to-read names for power-of-two
numbers. The numbers like this are othen used
for memory range sizes.
Signed-off-by: Antony Pavlov
---
include/qemu/sizes.h | 61
Signed-off-by: Antony Pavlov
Reviewed-by: Aurelien Jarno
---
hw/mips/mips_malta.c | 25 +
include/hw/mips/bios.h | 3 ++-
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 05c8771..604832f 100644
--- a
The header file sizes.h is used in linux kernel,
barebox bootloader and u-boot bootloader. It provides
the short and easy-to-read names for power-of-two
numbers. The numbers like this are othen used
for memory range sizes.
Signed-off-by: Antony Pavlov
Reviewed-by: Aurelien Jarno
Reviewed-by
Changes since v1:
* include/sizes.h -> include/qemu/sizes.h
* fix copyright header;
* fix formatting: drop tabs;
* use the BIT() macro, so it's easy-to-read the constants column;
also the BIT() macro casts constant to UL;
* rebase on updated master;
* take into account the "mips_malta: s
1 - 100 of 162 matches
Mail list logo
