[PATCH v2 1/2] contrib/plugins: add meson build file

Add crossplatform Meson file to build TCG plugins since the Makefile makes wrong assumptions about it being used only on Linux. Tested on Linux and macOS. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1710 Signed-off-by: Anton Kochkov --- contrib/plugins/meson.build | 31

[PATCH v2 0/2] contrib/plugins: Migrate to the Meson build

Makefile made a lot of assumption regarding the system to compile for. It was also limited to the Linux (and possibly BSD) only, without the way to compile for macOS or Windows. Changes since v1: - Remove Makefile Anton Kochkov (2): contrib/plugins: add meson build file contrib/plugins

[PATCH v2 2/2] contrib/plugins: remove Makefile

Signed-off-by: Anton Kochkov --- contrib/plugins/Makefile | 46 1 file changed, 46 deletions(-) delete mode 100644 contrib/plugins/Makefile diff --git a/contrib/plugins/Makefile b/contrib/plugins/Makefile deleted file mode 100644 index b2b9db9f51

[PATCH] contrib/plugins: add meson build file

Add crossplatform Meson file to build TCG plugins since the Makefile makes wrong assumptions about it being used only on Linux. Tested on Linux and macOS. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1710 Signed-off-by: Anton Kochkov --- contrib/plugins/meson.build | 31

Writing TCG plugin - how to hook interrupts?

Hi, Is it possible to set a hook for interrupts from the TCG plugin? I searched in documentation, examples, and sources but found nothing of relevance. Did I miss something? Is this currently implemented? Thank you for the answers. Best regards, Anton.

Re: [RFC] hw/block/m25p80: implement Octal SPI commands

Aug 13] Sat 12:00:03, Anton Kochkov wrote: > > * Implement Octal SPI commands based on Micron MT35X series > > * Fix Micron 0x2C-based ID handling (incompatible with Numonyx) > > * Fix Micron configuration registers handling > > Would it be ok for you to split the patch up in

[RFC v2] m25p80: Implement Octal SPI commands

Signed-off-by: Anton Kochkov Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1148 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1149 --- hw/block/m25p80.c | 194 +++--- 1 file changed, 184 insertions(+), 10 deletions(-) diff --git a/hw

Re: [PATCH] target/tricore: Fix OPC1_16_SRO_LD_H translation

--- Original Message --- On Friday, January 13th, 2023 at 5:03 AM, Bastian Koppelmann wrote: > > > On Thu, Jan 12, 2023 at 02:24:02PM +0000, Anton Kochkov wrote: > > > Signed-off-by: Eitan Eliahu eitan_eli...@hotmail.com > > Resolves: https://gitlab.com/qe

[PATCH] po/meson: make i18n module optional

() method before use. 4 | i18n.gettext(meson.project_name(), ^ qemu/meson.build:3640:3: error in function subdir() 3640 | subdir('po') ^ Signed-off-by: Anton Kochkov --- po/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/po/meso

[PATCH] target/tricore: Fix OPC1_16_SRO_LD_H translation

Signed-off-by: Eitan Eliahu Resolves: https://gitlab.com/qemu-project/qemu/-/issues/652 --- target/tricore/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index df9e46c649..b2a5e11778 100644 --- a/target/trico

[PATCH v2] meson: be strict for boolean options

. See https://mesonbuild.com/Build-options.html Signed-off-by: Anton Kochkov Reviewed-by: Philippe Mathieu-Daudé --- meson_options.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meson_options.txt b/meson_options.txt index e58e158396..63f0725174 100644 --- a/meson_

[PATCH v2] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic

For consistency, function "update_rx_fifo()" should use the RX FIFO register names, not the TX FIFO ones even if they refer to the same memory region. Signed-off-by: Anton Kochkov Reviewed-by: Francisco Iglesias Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1123 --- hw/ne

[PATCH] meson: be strict for boolean options

. See https://mesonbuild.com/Build-options.html Signed-off-by: Anton Kochkov --- meson_options.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meson_options.txt b/meson_options.txt index e58e158396..63f0725174 100644 --- a/meson_options.txt +++ b/meson_options.txt @

[RFC] hw/block/m25p80: implement Octal SPI commands

* Implement Octal SPI commands based on Micron MT35X series * Fix Micron 0x2C-based ID handling (incompatible with Numonyx) * Fix Micron configuration registers handling Signed-off-by: Anton Kochkov Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1148 Resolves: https://gitlab.com/qemu

[PATCH] hw/arm/nvic: implement "num-prio-bits" property

expose priority bits as QDev property which is by default is set to 8 as it was hardcoded in the past. Thus, existing code doesn't require any additional changes, and it doesn't change the default behavior of NVIC. Signed-off-by: Anton Kochkov Resolves: https://gitlab.com/qemu-project/qem

[PATCH] can: fix Xilinx ZynqMP CAN RX FIFO logic

Function "update_rx_fifo()" should operate on the RX FIFO registers, not the TX FIFO ones. Signed-off-by: Anton Kochkov Resolves: https://gitlab.com/qemu-projects/qemu/-/issues/1123 --- hw/net/can/xlnx-zynqmp-can.c | 32 1 file changed, 16 inserti

[Qemu-devel] [Bug 741115] [NEW] Add support of coprocessor cp15, cp14 registers exposion in the embedded gdb server

Public bug reported: Please add support of exposion of ARM coprocesor registers/logic at the embedded gdb server, for example of cp15, cp14, etc registers. Related project http://jtagarmgdbsrvr.sourceforge.net/index.html Also filled bug in the GDB http://sourceware.org/bugzilla/show_bug.cgi?id