[PATCH v2] target/riscv: Fix fcvt.s.bf16 NaN box checking

fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16 quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN. Signed-off-by: Anton Blanchard --- target/riscv/fpu_helper.c | 2 +- target/riscv/internals.h | 16 2 files changed, 17 insertions(+), 1

Re: [PATCH v2 08/12] target/arm/cpu: remove TARGET_BIG_ENDIAN dependency

AN_LITTLE : > BFD_ENDIAN_BIG; > +info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : > BFD_ENDIAN_BIG; > } > info->flags &= ~INSN_ARM_BE32; > #ifndef CONFIG_USER_ONLY > -- > 2.47.2 > Reviewed-by: Anton Johansson

[PATCH] target/riscv: Fix fcvt.s.bf16 NaN box checking

fcvt.s.bf16 uses the FP16 check_nanbox_h() which returns an FP16 quiet NaN. Add check_nanbox_bf16() which returns a BF16 quiet NaN. --- target/riscv/fpu_helper.c | 2 +- target/riscv/internals.h | 16 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/riscv/fp

Re: [PATCH 09/13] target/arm/cpu: get endianness from cpu state

are not equivalent. My understanding is that arm_cpu_is_big_endian() models data endianness, and TARGET_BIG_ENDIAN instruction endianness. Also, for user mode where this branch is relevant, bswap_code() still depends on TARGET_BIG_ENDIAN anyway and the above branch would reduce to (on arm32) if (TARGET_BIG_ENDIAN ^ sctlr_b) { info->endian = sctlr_b ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; } giving the opposite result to the original code. -- Anton Johansson rev.ng Labs Srl.

Re: [PATCH v3 11/13] physmem: Restrict TCG IOTLB code to TCG accel

On 28/04/25, Richard Henderson wrote: > On 4/28/25 11:51, Anton Johansson wrote: > > On 24/04/25, Philippe Mathieu-Daudé wrote: > > > Restrict iotlb_to_section(), address_space_translate_for_iotlb() > > > and memory_region_section_get_iotlb() to TCG. Declare them

Re: [PATCH v3 11/13] physmem: Restrict TCG IOTLB code to TCG accel

; + * SPDX-License-Identifier: LGPL-2.1-or-later > + */ > +#ifndef ACCEL_TCG_IOMMU_H > +#define ACCEL_TCG_IOMMU_H > + > +#ifdef CONFIG_USER_ONLY > +#error Cannot include accel/tcg/iommu.h from user emulation > +#endif > + > +#include "exec/hwaddr.h" > +#include "exec/memattrs.h" Missing qemu/typedefs.h include Otherwise: Reviewed-by: Anton Johansson

Re: [PATCH v3 06/13] accel/tcg: Compile tb-maint.c twice

gt; accel/tcg/tb-maint.c | 2 -- > accel/tcg/meson.build | 2 +- > 3 files changed, 2 insertions(+), 5 deletions(-) Reviewed-by: Anton Johansson

Re: [PATCH v3 05/13] include/exec: Move tb_invalidate_phys_range to translation-block.h

> include/exec/exec-all.h | 5 - > include/exec/translation-block.h | 4 > 2 files changed, 4 insertions(+), 5 deletions(-) Reviewed-by: Anton Johansson

Re: [PATCH v3 02/13] accel/tcg: Use vaddr in user/page-protection.h

++--- > accel/tcg/user-exec.c | 51 -- > 2 files changed, 31 insertions(+), 37 deletions(-) Reviewed-by: Anton Johansson

Re: [PATCH v3 09/13] accel/tcg: Include 'accel/tcg/getpc.h' in 'exec/helper-proto'

inc" > #undef HELPER_H > > +#include "accel/tcg/getpc.h" > + Non-TCG builds will fail since exec/helper-proto.h is sometimes included outside CONFIG_TCG (e.g. target/arm/debug_helper.c). -- Anton Johansson rev.ng Labs Srl.

[PATCH] target/riscv: Fix vslidedown with rvv_ta_all_1s

vslidedown always zeroes elements past vl, where it should use the tail policy. Signed-off-by: Anton Blanchard --- target/riscv/vector_helper.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 67b3bafebb

Re: [RFC PATCH-for-10.1 4/4] tcg: Define guest_default_memory_order in TCGCPUOps

| 23 +++ > target/tricore/cpu.c | 2 ++ > target/xtensa/cpu.c | 3 +++ > 41 files changed, 90 insertions(+), 80 deletions(-) This is a nice change!:) Reviewed-by: Anton Johansson

CRITICAL Unexpected bottom half exception

2025-04-04 12:07:59,172 archtest CRITICAL Unexpected bottom half exception. This is a bug in the QMP library. Please report it to and CC: John Snow .:   | Traceback (most recent call last):   |   File "/home/anton/.local/lib/python3.13/site-packages/qemu/qmp/protocol.py", li

[PATCH v2 1/2] target/hexagon: Replace `prepare` script with meson target

custom_target. Signed-off-by: Anton Johansson --- target/hexagon/idef-parser/prepare | 24 target/hexagon/meson.build | 3 ++- 2 files changed, 2 insertions(+), 25 deletions(-) delete mode 100755 target/hexagon/idef-parser/prepare diff --git a/target/hexagon/idef-parser

[PATCH v2 2/2] target/hexagon: Only indent on linux

indent on macOS, installed via homebrew, doesn't support -linux. Only run indent on linux hosts. Signed-off-by: Anton Johansson --- target/hexagon/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build

[PATCH v2 0/2] target/hexagon: Fix macOS build

t bison on macOS is still too old (v2.3 vs v3.0) and a newer version needs to be installed via homebrew. I'll take a look at supporting v2.3. Changes in v2: * Don't remove the indent step but only run on linux hosts. Anton Johansson (2): target/hexagon: Replace `prepare` script with m

Re: [RFC PATCH-for-10.1 0/4] tcg: Move TCG_GUEST_DEFAULT_MO -> TCGCPUOps::guest_default_memory_order

.c | 2 ++ > target/ppc/cpu_init.c | 2 ++ > target/riscv/tcg/tcg-cpu.c| 2 ++ > target/rx/cpu.c | 3 +++ > target/s390x/cpu.c| 6 ++ > target/sh4/cpu.c | 3 +++ > target/sparc/cpu.c| 23 ++++

Re: [PATCH-for-10.1 0/8] target/mips: Make 'cpu-qom.h' target agnostic

| 42 - > target/mips/gdbstub.c | 14 +++--- > target/mips/tcg/system/tlb_helper.c | 2 +- > 7 files changed, 61 insertions(+), 25 deletions(-) > > -- > 2.47.1 > Reviewed-by: Anton Johansson

Re: [PATCH 2/2] target/hexagon: Drop `ident` postprocess step

On 25/03/25, Brian Cain wrote: > > On 3/24/2025 8:53 PM, ltaylorsimp...@gmail.com wrote: > > > > > -Original Message----- > > > From: Anton Johansson > > > Sent: Wednesday, March 12, 2025 2:46 PM > > > To: qemu-devel@nongnu.org > >

Re: [PATCH-for-10.1 4/4] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field

u_init.c| 1 + > target/riscv/tcg/tcg-cpu.c | 1 + > target/rx/cpu.c | 1 + > target/s390x/cpu.c | 1 + > target/sh4/cpu.c | 1 + > target/sparc/cpu.c | 1 + > targe

Re: [RFC PATCH-for-10.1 3/4] tcg: Have tcg_req_mo() use runtime TCGContext::guest_mo

On 21/03/25, Philippe Mathieu-Daudé wrote: > In order to use TCG with multiple targets, replace the > compile time use of TCG_GUEST_DEFAULT_MO by a runtime > access to tcg_ctx->guest_mo. > > Signed-off-by: Philippe Mathieu-Daudé > --- > accel/tcg/internal-target.h | 4 +--- > 1 file changed, 1 i

Re: [PATCH-for-10.1 3/4] tcg: Convert TCGState::mttcg_enabled to TriState

void tcg_set_thread(Object *obj, const char *value, Error **errp) > @@ -155,14 +157,10 @@ static void tcg_set_thread(Object *obj, const char > *value, Error **errp) > if (icount_enabled()) { > error_setg(errp, "No MTTCG when icount is enabled"); > } else { > -#ifndef TARGET_SUPPORTS_MTTCG > -warn_report("Guest not yet converted to MTTCG - " > -"you may get unexpected results"); > -#endif Patch itself looks good! My only concern is moving the warning, would it be worthwhile to have a mttcg_supported field in TCGState as well? I.e in a heterogeneous setup it would correspond to wether or not all targets support mttcg. Otherwise: Reviewed-by: Anton Johansson

Re: [PATCH-for-10.1 2/4] tcg: Simplify tcg_req_mo() macro

_mttcg_enabled(void) > return false; > } > #ifdef TARGET_SUPPORTS_MTTCG > -# ifndef TCG_GUEST_DEFAULT_MO > -# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO" > -# endif > return true; > #else > return false; > -- > 2.47.1 > Reviewed-by: Anton Johansson

Re: [PATCH-for-10.1 1/4] tcg: Always define TCG_GUEST_DEFAULT_MO

| 4 > 6 files changed, 15 insertions(+), 4 deletions(-) Reviewed-by: Anton Johansson

Re: [CAUTION - External Sender] Re: [PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases

an discuss the details further. Sorry for not getting back to you earlier but that would be great. Thanks, Anton

[PATCH 2/2] target/hexagon: Drop `ident` postprocess step

The indent command is not available on a default mac osx setup with xcode cli tools installed. While it does make idef-parser generated code nicer to debug, it's not crucial and can be dropped. Signed-off-by: Anton Johansson --- target/hexagon/meson.build | 21 ++--- 1

[PATCH 1/2] target/hexagon: Replace `prepare` script with meson target

custom_target. Signed-off-by: Anton Johansson --- target/hexagon/idef-parser/prepare | 24 target/hexagon/meson.build | 3 ++- 2 files changed, 2 insertions(+), 25 deletions(-) delete mode 100755 target/hexagon/idef-parser/prepare diff --git a/target/hexagon/idef-parser

[PATCH 0/2] target/hexagon: Fix macOS build

ake a look at supporting v2.3. Anton Johansson (2): target/hexagon: Replace `prepare` script with meson target target/hexagon: Drop `ident` postprocess step target/hexagon/idef-parser/prepare | 24 target/hexagon/meson.build | 24 2 fil

Re: [PATCH-for-10.1 0/2] target/hexagon: Remove use of MO_TE definition

parser-helpers.c | 2 +- > target/hexagon/translate.c | 6 +++--- > 4 files changed, 13 insertions(+), 13 deletions(-) > > -- > 2.47.1 > Series: Reviewed-by: Anton Johansson

Re: [PATCH 6/8] target/hexagon: add build config for softmmu

es this is an issue of default arguments added by cpp on mac, I ran into this a little while ago on a downstream fork. cpp on mac expands clang ... -traditional-cpp which alsos break macro concatenation.. I carry a patch which: * Removes indent pass on idef-parser output, as indent is not available on mac; * Replaces cpp with ${compiler} ... -E ... where compiler is gotten from meson. I'm a bit sad about the default meson version being outdated though..:( -- Anton Johansson rev.ng Labs Srl.

Re: [PATCH v3 10/17] hw/arm/xlnx-zynqmp: Use &error_abort for programming errors

re simplify and use &error_abort as this can't fail. > > > > Reported-by: Richard Henderson > > Signed-off-by: Philippe Mathieu-Daudé > > --- > > hw/arm/xlnx-zynqmp.c | 44 ++-- > > 1 file changed, 14 insertions(+), 30 deletions(-) > > Makes sense!:) Reviewed-by: Anton Johansson

[PATCH 06/12] target/riscv: handle vzext.vf2 form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index a873536eea..0952bcbe2c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH 05/12] target/riscv: handle vslide1down.vx form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f5ba1c4280..a873536eea 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH 01/12] target/riscv: Source vector registers cannot overlap mask register

Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/target

[PATCH 04/12] target/riscv: handle vadd.vv form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bc2780497e..f5ba1c4280 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH 08/12] target/riscv: handle vwadd.vv form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bc22b42801..45b2868c54 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH 10/12] target/riscv: handle vwadd.wv form vs1 and vs2 overlap

for 2*SEW = 2*SEW op SEW instructions vs2 and vs1 cannot overlap because it would mean a register is read with two different SEW settings. Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target

[PATCH 11/12] target/riscv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 312d8b1b81..2741f8bd8e 100644 --- a/target

[PATCH 07/12] target/riscv: handle vwadd.vx form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 0952bcbe2c..bc22b42801 100644 --- a/target/riscv

[PATCH 02/12] target/riscv: handle vrgather mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 20b1cb127b..c66cd95bdb 100644 --- a/target/riscv

[PATCH 12/12] target/riscv: handle overlap in widening instructions with overwrite

In these instructions vd is considered a source, so no overlap is allowed between vd and vs1/vs2. See: https://github.com/riscv/riscv-isa-manual/issues/1789 Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 71 +++-- 1 file changed, 56 insertions

[PATCH 00/12] target/riscv: Fix some RISC-V instruction corner cases

Tenstorrent fork of Whisper which models this behaviour better than Spike and Sail. Anton Blanchard (12): target/riscv: Source vector registers cannot overlap mask register target/riscv: handle vrgather mask and source overlap target/riscv: handle vadd.vx form mask and source overlap target/riscv

[PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index c66cd95bdb..bc2780497e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH 09/12] target/riscv: handle vwadd.wv form mask and source overlap

Signed-off-by: Anton Blanchard --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 45b2868c54..2309d9abd0 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc

[PATCH 1/2] target/hexagon: Use argparse in all python scripts

QOL commit, all the various gen_* python scripts take a large set arguments where order is implicit. Using argparse we also get decent error messages if a field is missing or too many are added. Signed-off-by: Anton Johansson Reviewed-by: Brian Cain --- target/hexagon/gen_analyze_funcs.py

[PATCH 0/2] Misc Hexagon QOL

Separate submission of patches 35 and 37 from the helper-to-tcg patchset: https://lore.kernel.org/qemu-devel/20241121014947.18666-1-a...@rev.ng/ Anton Johansson (2): target/hexagon: Use argparse in all python scripts target/hexagon: Make HVX vector args. restrict * target/hexagon

[PATCH 2/2] target/hexagon: Make HVX vector args. restrict *

Adds restrict qualifier to HVX pointer arguments. This will allow the compiler to produce better optimized code, as input vectors are now assumed not to alias, and no runtime aliasing checks will be required. Signed-off-by: Anton Johansson Reviewed-by: Brian Cain --- target/hexagon/mmvec

Re: [RFC PATCH v1 03/43] accel/tcg: Add gvec size changing operations

On 03/12/24, Richard Henderson wrote: > On 12/3/24 12:08, Anton Johansson wrote: > > On 22/11/24, Richard Henderson wrote: > > > On 11/20/24 19:49, Anton Johansson wrote: > > > > Adds new functions to the gvec API for truncating, sign- or zero > > >

Re: [RFC PATCH v1 01/43] Add option to enable/disable helper-to-tcg

On 22/11/24, Paolo Bonzini wrote: > On 11/22/24 18:30, Richard Henderson wrote: > > On 11/20/24 19:49, Anton Johansson wrote: > > > Adds a meson option for enabling/disabling helper-to-tcg along with a > > > CONFIG_* definition. > > > > > > CONFIG_* wi

Re: [RFC PATCH v1 08/43] include/helper-to-tcg: Introduce annotate.h

On 25/11/24, Philippe Mathieu-Daudé wrote: > On 22/11/24 19:12, Richard Henderson wrote: > > On 11/20/24 19:49, Anton Johansson wrote: > > > Wrap __attribute__((annotate(str))) in a macro for convenient > > > function annotations.  Will be used in future commits

Re: [RFC PATCH v1 00/43] Introduce helper-to-tcg

On 25/11/24, Philippe Mathieu-Daudé wrote: > On 21/11/24 02:49, Anton Johansson wrote: > > > create mode 100644 subprojects/helper-to-tcg/README.md > > create mode 100755 subprojects/helper-to-tcg/get-llvm-ir.py > > create mode 100644 subprojects/helper-to-tcg/

Re: [RFC PATCH v1 37/43] target/hexagon: Make HVX vector args. restrict *

should be "foo *bar" > > #32: FILE: target/hexagon/mmvec/macros.h:27: > > +#define VsV  (*(MMVector * restrict)(VsV_void)) > > > > ERROR: "foo * bar" should be "foo *bar" > > #33: FILE: target/hexagon/mmvec/macros.h:28: > > +#define VuV  (*(MMVector * restrict)(VuV_void)) > > I think checkpatch.pl has a point here. :) I'll switch to `*restrict`!:) //Anton

Re: [RFC PATCH v1 36/43] target/hexagon: Add temporary vector storage

On 22/11/24, Richard Henderson wrote: > On 11/20/24 19:49, Anton Johansson wrote: > > Temporary vectors in helper-to-tcg generated code are allocated from an > > array of bytes in CPUArchState, specified with --temp-vector-block. > > > > This commits adds such a bloc

Re: [RFC PATCH v1 34/43] target/hexagon: Add get_tb_mmu_index()

On 22/11/24, Richard Henderson wrote: > On 11/20/24 19:49, Anton Johansson wrote: > > Adds a functions to return the current mmu index given tb_flags of the > > current translation block. Required by helper-to-tcg in order to > > retrieve the mmu index for memory operations

Re: [RFC PATCH v1 28/43] helper-to-tcg: Introduce TcgType.h

On 22/11/24, Richard Henderson wrote: > On 11/20/24 19:49, Anton Johansson via wrote: > > Adds a struct representing everything a LLVM value might map to in TCG, > > this includes: > > > >* TCGv (IrValue); > >* TCGv_ptr (IrPtr); > >* TCGv_

Re: [RFC PATCH v1 09/43] helper-to-tcg: Introduce get-llvm-ir.py

On 22/11/24, Richard Henderson wrote: > On 11/20/24 19:49, Anton Johansson wrote: > > Introduces a new python helper script to convert a set of QEMU .c files to > > LLVM IR .ll using clang. Compile flags are found by looking at > > compile_commands.json, and llvm-link is used

Re: [RFC PATCH v1 05/43] tcg: Add helper function dispatcher and hook tcg_gen_callN

On 22/11/24, Richard Henderson wrote: > On 11/20/24 19:49, Anton Johansson wrote: > > Adds a function pointer to the TCGContext which may be set by targets via > > the TARGET_HELPER_DISPATCHER macro. The dispatcher is function > > > >(void *func, TCGTemp *ret

Re: [RFC PATCH v1 04/43] tcg: Add gvec functions for creating consant vectors

On 22/11/24, Richard Henderson wrote: > On 11/20/24 19:49, Anton Johansson wrote: > > This commit adds a gvec function for copying data from constant array > > given in C to a gvec intptr_t. For each element, a host store of > > each constant is performed, this is not ideal

Re: [RFC PATCH v1 03/43] accel/tcg: Add gvec size changing operations

On 22/11/24, Richard Henderson wrote: > On 11/20/24 19:49, Anton Johansson wrote: > > Adds new functions to the gvec API for truncating, sign- or zero > > extending vector elements. Currently implemented as helper functions, > > these may be mapped onto host vector instr

Re: [RFC PATCH v1 02/43] accel/tcg: Add bitreverse and funnel-shift runtime helper functions

On 22/11/24, Richard Henderson wrote: > On 11/20/24 19:49, Anton Johansson wrote: > > Adds necessary helper functions for mapping LLVM IR onto TCG. > > Specifically, helpers corresponding to the bitreverse and funnel-shift > > intrinsics in LLVM. > > > > Not

Re: [PATCH-for-10.0 6/6] accel/tcg: Allow tcg_exec_realizefn() initialize multiple frontends

itialize_once(); > -tcg_target_initialized = true; > +initialized_targets |= tcg_ops->arch_id; > } > > cpu->tb_jmp_cache = g_new0(CPUJumpCache, 1); > -- > 2.45.2 > Only suggestion would be to assert that arch_id is set, might save some headache in the future. Reviewed-by: Anton Johansson

Re: [PATCH-for-10.0 5/6] accel/tcg: Add TCGCPUOps::arch_id field

c/cpu_init.c | 1 + > target/riscv/tcg/tcg-cpu.c| 1 + > target/rx/cpu.c | 1 + > target/s390x/cpu.c| 1 + > target/sh4/cpu.c | 1 + > target/sparc/cpu.c| 1 + > target/tricore/cpu.c | 1 + > target/xt

Re: [PATCH-for-10.0 2/6] accel/tcg: Declare local tcg_ops variable in tcg_exec_realizefn()

On 27/11/24, Philippe Mathieu-Daudé wrote: > Ease reading code by declaring a local 'tcg_ops' variable. > > Signed-off-by: Philippe Mathieu-Daudé > --- > accel/tcg/cpu-exec.c | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Anton Johansson

Re: [PATCH-for-10.0 1/6] target/ppc: Indent ppc_tcg_ops[] with 4 spaces

On 27/11/24, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > Acked-by: Nicholas Piggin > --- > target/ppc/cpu_init.c | 29 ++--- > 1 file changed, 14 insertions(+), 15 deletions(-) Reviewed-by: Anton Johansson

[RFC PATCH v1 37/43] target/hexagon: Make HVX vector args. restrict *

If pointer arguments to HVX helper functions are not marked restrict *, then LLVM will assume that input vectors may alias and emit runtime checks. Signed-off-by: Anton Johansson --- target/hexagon/mmvec/macros.h | 36 +-- 1 file changed, 18 insertions(+), 18

[RFC PATCH v1 10/43] helper-to-tcg: Add meson.build

; 3. Building of helper-to-tcg. A meson option is added to specify the path to llvm-config. Signed-off-by: Anton Johansson --- subprojects/helper-to-tcg/meson.build | 70 + subprojects/helper-to-tcg/meson_options.txt | 2 + 2 files changed, 72 insertions(+) create

[RFC PATCH v1 08/43] include/helper-to-tcg: Introduce annotate.h

Wrap __attribute__((annotate(str))) in a macro for convenient function annotations. Will be used in future commits to tag functions for translation by helper-to-tcg, and to specify which helper function arguments correspond to immediate or vector values. Signed-off-by: Anton Johansson

[RFC PATCH v1 22/43] helper-to-tcg: PrepareForTcgPass, remove functions w. cycles

better suited as a helper anyway. Cycles are detected by iterating over Strongly Connected Components (SCCs) which imply the existence of cycles if: - a SCC contains more than one node, or; - it has a self-edge. Signed-off-by: Anton Johansson --- .../PrepareForTcgPass/PrepareForTcgPass.cpp

[RFC PATCH v1 41/43] target/hexagon: Manually call generated HVX instructions

For HVX instructions that were successfully translated by helper-to-tcg, emit calls to emit_*() "manually" from generate_*(). Recall that scalar instructions translated by helper-to-tcg are automatically called by a hook in tcg_gen_callN. Signed-off-by: Anton Johansson --- targ

[RFC PATCH v1 09/43] helper-to-tcg: Introduce get-llvm-ir.py

Introduces a new python helper script to convert a set of QEMU .c files to LLVM IR .ll using clang. Compile flags are found by looking at compile_commands.json, and llvm-link is used to link together all LLVM modules into a single module. Signed-off-by: Anton Johansson --- subprojects/helper

[RFC PATCH v1 12/43] helper-to-tcg: Introduce custom LLVM pipeline

behaviour across different hosts. Signed-off-by: Anton Johansson --- .../helper-to-tcg/include/CmdLineOptions.h| 23 +++ subprojects/helper-to-tcg/meson.build | 1 + .../helper-to-tcg/pipeline/Pipeline.cpp | 159 ++ 3 files changed, 183 insertions(+) create

[RFC PATCH v1 24/43] helper-to-tcg: PrepareForTcgPass, map TCG globals

the global cpu_mapping array. The name of this array is configurable via the --tcg-global-mappings flag. Signed-off-by: Anton Johansson --- .../helper-to-tcg/include/PrepareForTcgPass.h | 7 ++- .../helper-to-tcg/include/TcgGlobalMap.h | 31 + .../PrepareForTcgPass

[RFC PATCH v1 42/43] target/hexagon: Only translate w. idef-parser if helper-to-tcg failed

Only generate input functions to idef-parser for instructions which failed to be translated by helper-to-tcg. Signed-off-by: Anton Johansson --- target/hexagon/gen_idef_parser_funcs.py | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target

[RFC PATCH v1 16/43] helper-to-tcg: PrepareForOptPass, Cull unused functions

Make an early pass over all functions in the input module and filter out functions with: 1. Invalid return type; 2. No helper-to-tcg annotation. Signed-off-by: Anton Johansson --- .../helper-to-tcg/include/PrepareForOptPass.h | 7 +- .../PrepareForOptPass/PrepareForOptPass.cpp | 93

[RFC PATCH v1 04/43] tcg: Add gvec functions for creating consant vectors

impacting performance. A more suitable solution might store constant vectors separately, this can be handled either on the QEMU or helper-to-tcg side. Signed-off-by: Anton Johansson --- include/tcg/tcg-op-gvec-common.h | 2 ++ tcg/tcg-op-gvec.c| 30 ++ 2

[RFC PATCH v1 40/43] target/hexagon: Emit annotations for helpers

le containing all successfully translated helper functions, and secondly to expose the indices of immediate and pointer (vector) arguments to helper functions. The latter is needed to generate the input of helper-to-tcg. Signed-off-by: Anton Johansson --- target/hexagon/gen_helper_funcs.py |

[RFC PATCH v1 13/43] helper-to-tcg: Introduce Error.h

Simple function for creating Expected<> with nice error messages. Signed-off-by: Anton Johansson --- subprojects/helper-to-tcg/include/Error.h | 40 +++ 1 file changed, 40 insertions(+) create mode 100644 subprojects/helper-to-tcg/include/Error.h diff --git a/subpr

[RFC PATCH v1 17/43] helper-to-tcg: PrepareForOptPass, undef llvm.returnaddress

Convert llvm.returnaddress arguments to cpu_[ld|st]*() to undef, causing the LLVM optmizer to discard the intrinsics. Needed as llvm.returnadress is not representable in TCG, and usually results from usage of GETPC() in helper functions. Signed-off-by: Anton Johansson --- .../PrepareForOptPass

[RFC PATCH v1 31/43] helper-to-tcg: Introduce TcgGenPass

Adds a backend pass, taking previously optimized and canonicalized LLVM IR and for each function: 1. Runs the TcgV register allocator; 2. Iterates over instructions and calls appropriate functions in TcgEmit.h to emit TCG code. Signed-off-by: Anton Johansson --- .../helper-to-tcg

[RFC PATCH v1 14/43] helper-to-tcg: Introduce PrepareForOptPass

Adds a new LLVM pass that runs early in the pipeline with the goal of preparing the input module for optimization by doing some early culling of functions and information gathering. This commits sets up a new LLVM pass over the IR module and runs it from the pipeline. Signed-off-by: Anton

[RFC PATCH v1 11/43] helper-to-tcg: Introduce llvm-compat

Adds a translation unit with the sole purpose of handling inter-LLVM code changes. Instead of littering the code with #ifdefs, most of them will be limited to llvm-compat.[cpp|h] and a saner compat::*() function is exposed in its place. Signed-off-by: Anton Johansson --- subprojects/helper-to

[RFC PATCH v1 15/43] helper-to-tcg: PrepareForOptPass, map annotations

In the LLVM IR module function annotations are stored in one big global array of strings. Traverse this array and parse the data into a format more useful for future passes. A map between Functions * and a list of annotations is exposed. Signed-off-by: Anton Johansson --- .../include

[RFC PATCH v1 33/43] helper-to-tcg: Add end-to-end tests

Introduces simple end-to-end tests of helper-to-tcg of functions the translator is expected to handle, any translation failure will result in a test failure. More test cases to come. Signed-off-by: Anton Johansson --- subprojects/helper-to-tcg/meson.build | 2 + subprojects/helper-to

[RFC PATCH v1 34/43] target/hexagon: Add get_tb_mmu_index()

Adds a functions to return the current mmu index given tb_flags of the current translation block. Required by helper-to-tcg in order to retrieve the mmu index for memory operations without changing the signature of helper functions. Signed-off-by: Anton Johansson --- target/hexagon/cpu.h | 12

[RFC PATCH v1 23/43] helper-to-tcg: PrepareForTcgPass, demote phi nodes

PHI nodes have no clear analogue in TCG, this commits converts them to stack accesses using a built-in LLVM transformation. Signed-off-by: Anton Johansson --- .../PrepareForTcgPass/PrepareForTcgPass.cpp | 24 +++ 1 file changed, 24 insertions(+) diff --git a/subprojects

[RFC PATCH v1 26/43] helper-to-tcg: PrepareForTcgPass, canonicalize IR

Iterates over the IR with the goal of converting it to a form closer to TCG, taking care of IR disparencies between LLVM and TCG. This also simplifies the backend by containing the bulk of custom IR transformations, meaning the backend can be as dumb as possible. Signed-off-by: Anton Johansson

[RFC PATCH v1 01/43] Add option to enable/disable helper-to-tcg

Hexagon, as helper-to-tcg will be included as a subproject from target/hexagon. This will change in the future if multiple frontends adopt helper-to-tcg. Signed-off-by: Anton Johansson --- meson.build | 7 +++ meson_options.txt | 2 ++ scripts/meson-buildoptions.sh

[RFC PATCH v1 30/43] helper-to-tcg: TcgGenPass, introduce TcgEmit.[cpp|h]

A new translation unit is added with the purpose of containing all code which emits strings of TCG code. The idea is that maintainence of the backend will be simpler if all "tcg_*(*)" strings are contained and wrapped in functions. Signed-off-by: Anton Johansson --- .../helper-to-t

[RFC PATCH v1 43/43] target/hexagon: Use helper-to-tcg

def-parser can be reduced moving forward. Signed-off-by: Anton Johansson --- target/hexagon/meson.build | 151 +++-- 1 file changed, 111 insertions(+), 40 deletions(-) diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index bb4ebaae81..563d60e

[RFC PATCH v1 06/43] tcg: Introduce tcg-global-mappings

future commits to map between offsets into CPUArchState and TCGv globals in a target-agnostic way. Signed-off-by: Anton Johansson --- include/tcg/tcg-global-mappings.h | 111 ++ tcg/meson.build | 1 + tcg/tcg-global-mappings.c | 61

[RFC PATCH v1 03/43] accel/tcg: Add gvec size changing operations

. Signed-off-by: Anton Johansson --- accel/tcg/tcg-runtime-gvec.c | 41 + accel/tcg/tcg-runtime.h | 22 + include/tcg/tcg-op-gvec-common.h | 18 tcg/tcg-op-gvec.c| 78 4 files changed, 159 insertions

[RFC PATCH v1 28/43] helper-to-tcg: Introduce TcgType.h

subject to change due to rework of the TcgV type system. There is quite significant overlap in handling IrConst/IrImmediate and any other type with the ConstantExpression bool set. Space required for each TcgV can also be reduced by moving to a union. Signed-off-by: Anton Johansson --- .../helper-to

[RFC PATCH v1 25/43] helper-to-tcg: PrepareForTcgPass, transform GEPs

rithmetic in LLVM IR using "call @PtrAdd(...)". These three cases are treated differently in the backend and all other GEPs are considered an error. Signed-off-by: Anton Johansson --- subprojects/helper-to-tcg/meson.build | 1 + .../PrepareForTcgPass

[RFC PATCH v1 32/43] helper-to-tcg: Add README

Signed-off-by: Anton Johansson --- subprojects/helper-to-tcg/README.md | 265 1 file changed, 265 insertions(+) create mode 100644 subprojects/helper-to-tcg/README.md diff --git a/subprojects/helper-to-tcg/README.md b/subprojects/helper-to-tcg/README.md new file

[RFC PATCH v1 36/43] target/hexagon: Add temporary vector storage

Temporary vectors in helper-to-tcg generated code are allocated from an array of bytes in CPUArchState, specified with --temp-vector-block. This commits adds such a block of memory to CPUArchState, if CONFIG_HELPER_TO_TCG is set. Signed-off-by: Anton Johansson --- target/hexagon/cpu.h | 4

[RFC PATCH v1 00/43] Introduce helper-to-tcg

(patches 34-43) - helper-to-tcg is used on the Hexagon frontend to translate a majority of helper functions in place of idef-parser. For the time being idef-parser will remain in use to translate instructions with multiple return values that are not representable as helper funct

[RFC PATCH v1 02/43] accel/tcg: Add bitreverse and funnel-shift runtime helper functions

subset of LLVM IR. Signed-off-by: Anton Johansson --- accel/tcg/tcg-runtime.c | 29 + accel/tcg/tcg-runtime.h | 5 + 2 files changed, 34 insertions(+) diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 9fa539ad3d..6372fa3f6f 100644 --- a/accel

[RFC PATCH v1 20/43] helper-to-tcg: Introduce pseudo instructions

ng similar instruction mappings into a single opcode (idendity mapping). Mapping from a call instructions in LLVM IR to an enum representing the pseudo instruction is also handled, this avoids string comparisons in the backend, and is easy to switch over. Signed-off-by: Anton Johansson --- s

[RFC PATCH v1 35/43] target/hexagon: Use argparse in all python scripts

QOL commit, all the various gen_* python scripts take a large set arguments where order is implicit. Using argparse we also get decent error messages if a field is missing or too many are added. Signed-off-by: Anton Johansson --- target/hexagon/gen_analyze_funcs.py | 6 +++-- target

[RFC PATCH v1 38/43] target/hexagon: Use cpu_mapping to map env -> TCG

mapped TCGv global. Signed-off-by: Anton Johansson --- target/hexagon/translate.c | 116 + 1 file changed, 65 insertions(+), 51 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 4b1bee3c6d..f9a9de35fe 100644 --- a/target

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