On Wed, Jul 16, 2025 at 03:47:37PM +0800, BillXiang wrote:
> Consider a system with 8 harts, where each hart supports 5
> Guest Interrupt Files (GIFs), yielding 40 total GIFs.
> If we launch a QEMU guest with over 5 vCPUs using
> "-M virt,aia='aplic-imsic' -accel kvm,riscv-aia=hwaccel" – which
> re
On Mon, Jun 23, 2025 at 06:39:02PM -0300, Daniel Henrique Barboza wrote:
> Hi Radim,
>
> It seems like this patch is breaking 'make check-functional':
>
> 12/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi TIMEOUT
> 90.06s killed by signal 15 SIGTERM
>
> Checking the lo
ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
> ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> --
> 2.49.0
>
>
Reviewed-by: Andrew Jones
-by: Daniel Henrique Barboza
> ---
> hw/riscv/Kconfig | 1 +
> hw/riscv/server_platform_ref.c | 78 --
> 2 files changed, 75 insertions(+), 4 deletions(-)
>
Reviewed-by: Andrew Jones
On Wed, May 28, 2025 at 05:01:28PM -0300, Daniel Henrique Barboza wrote:
> From: Fei Wu
>
> The RISC-V Server Platform specification[1] defines a standardized set
> of hardware and software capabilities, that portable system software,
> such as OS and hypervisors can rely on being present in a RI
(def->profile) {
> assert(profile_extends(def->profile, mcc->def->profile));
> -assert(mcc->def->bare);
> mcc->def->profile = def->profile;
> }
> if (def->misa_mxl_max) {
> --
> 2.49.0
>
Reviewed-by: Andrew Jones
On Wed, May 28, 2025 at 05:01:27PM -0300, Daniel Henrique Barboza wrote:
> From: Fei Wu
>
> The harts requirements of RISC-V server platform [1] require RVA23 ISA
> profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
> a virt CPU type (rvsp-ref) as compliant as possible.
>
>
/qemu/-/issues/2931
> Signed-off-by: Meng Zhuo
I gave my r-b on the last version of this patch (please include those when
posting again without major changes), here it is again
Reviewed-by: Andrew Jones
drew
> ---
> target/riscv/cpu.c | 3 +--
> target/riscv/cpu.h
ote a situation where we'll set mmu=on without a virtual
> memory mode, which is a mistake.
>
> Only touch 'mmu' and satp_mode if the profile is being enabled.
>
> Suggested-by: Andrew Jones
> Fixes: 55398025e7 ("target/riscv: add satp_mode profile support")
&
-1396,7 +1403,7 @@ static void cpu_get_profile(Object *obj, Visitor *v,
> const char *name,
> static void riscv_cpu_add_profiles(Object *cpu_obj)
> {
> for (int i = 0; riscv_profiles[i] != NULL; i++) {
> -const RISCVCPUProfile *profile = riscv_profiles[i];
> +RISCVCPUProfile *profile = riscv_profiles[i];
>
> object_property_add(cpu_obj, profile->name, "bool",
> cpu_get_profile, cpu_set_profile,
> @@ -1408,7 +1415,7 @@ static void riscv_cpu_add_profiles(Object *cpu_obj)
> * case.
> */
> if (profile->enabled) {
> -object_property_set_bool(cpu_obj, profile->name, true, NULL);
> +riscv_cpu_set_profile(RISCV_CPU(cpu_obj), profile, true);
> }
> }
> }
> --
> 2.49.0
>
Reviewed-by: Andrew Jones
t;name;
> -parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name,
> NULL);
> -profile->enabled = parent_enabled;
> +profile->present = parent->present;
> }
>
> static void riscv_cpu_validate_profile(RISCVCPU *cpu,
> @@ -910,7 +905,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
> }
> }
>
> -profile->enabled = profile_impl;
> +profile->present = profile_impl;
>
> riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent);
> riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent);
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
On Tue, May 20, 2025 at 01:58:45PM +0200, Andrew Jones wrote:
> On Tue, May 20, 2025 at 06:41:03PM +0800, Meng Zhuo wrote:
> > This patch adds host satp mode while kvm/host cpu satp mode is not
> > set.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2
bject *cpu_obj)
> kvm_riscv_init_machine_ids(cpu, &kvmcpu);
> kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
> kvm_riscv_init_cfg(cpu, &kvmcpu);
> +kvm_riscv_init_satp_mode(cpu, &kvmcpu);
>
> kvm_riscv_destroy_scratch_vcpu(&kvmcpu);
> }
> @@ -1980,7 +1998,7 @@ static bool kvm_cpu_realize(CPUState *cs, Error **errp)
> }
> }
>
> - return true;
> +return true;
> }
>
> void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> --
> 2.39.5
>
>
Otherwise,
Reviewed-by: Andrew Jones
On Tue, May 20, 2025 at 07:50:15AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 5/20/25 4:50 AM, Andrew Jones wrote:
> > On Mon, May 19, 2025 at 02:15:05PM -0300, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 5/19/25 1:35 PM, Andrew Jones wr
On Mon, May 19, 2025 at 02:15:05PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 5/19/25 1:35 PM, Andrew Jones wrote:
> > On Mon, May 19, 2025 at 09:48:14AM -0300, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 5/16/25 9:23 AM, Alexandre Ghiti
On Mon, May 19, 2025 at 09:48:14AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 5/16/25 9:23 AM, Alexandre Ghiti wrote:
> > The satp mode is set using the svXX properties, but that actually
> > restricts the satp mode to the minimum required by the profile and
> > prevents the use of higher sat
bit CSR in a
> 32 bit field when running in a 64 bit CPU.
>
> To prevent that, change the current logic to honor the size of the QEMU
> storage instead of the KVM CSR reg.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/ris
bit CSR in a
> 32 bit field when running in a 64 bit CPU.
>
> To prevent that, change the current logic to honor the size of the QEMU
> storage instead of the KVM CSR reg.
>
> Signed-off-by: Daniel Henrique Barboza
> Suggested-by: Andrew Jones
> ---
> target/riscv
On Mon, Apr 28, 2025 at 04:23:14PM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> In this new version a change was made in patch 8. Instead of changing
> scounteren to target_ulong, change the current logic to honor the QEMU
> env storage instead of the KVM reg size.
>
> This will make QEMU the
On Mon, Apr 28, 2025 at 03:37:26PM +0200, Radim Krčmář wrote:
> 2025-04-28T14:08:59+02:00, Andrew Jones :
> > On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote:
> >> 2025-04-28T09:00:55+02:00, Andrew Jones :
> >> > On Sun, Apr 27, 2025 at 09:25:57PM +0800,
On Mon, Apr 28, 2025 at 11:30:36AM +0200, Radim Krčmář wrote:
> 2025-04-28T09:00:55+02:00, Andrew Jones :
> > On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote:
> >> This patch adds host satp mode while kvm/host cpu satp mode is not
> >> set.
> >
> &g
On Sun, Apr 27, 2025 at 09:25:57PM +0800, Meng Zhuo wrote:
> This patch adds host satp mode while kvm/host cpu satp mode is not
> set.
Huh, the KVM side[1] was written for this purpose, but it appears we never
got a QEMU side merged.
[1] commit 2776421e6839 ("RISC-V: KVM: provide UAPI for host SA
On Fri, Apr 25, 2025 at 01:02:02PM -0300, Daniel Henrique Barboza wrote:
> We want to support scounteren as a KVM CSR. The KVM UAPI defines every
> CSR size as target_ulong, and our env->scounteren is fixed at 32 bits.
>
> The other existing cases where the property size does not match the KVM
> r
KVM to read/write the
> scounteren CSR without any surprises.
>
> Aside from bumping the version of the RISCVCPU vmstate no other
> behavioral changes are expected.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.h | 9 ++++-
> target/riscv/machine.c | 6 +++---
> 2 files changed, 11 insertions(+), 4 deletions(-)
>
Reviewed-by: Andrew Jones
On Fri, Apr 25, 2025 at 08:37:05AM -0300, Daniel Henrique Barboza wrote:
> Now that CPURISCVState::scounteren is a target_ulong, add support for
> the scounteren KVM CSR.
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-c
On Fri, Apr 25, 2025 at 08:37:04AM -0300, Daniel Henrique Barboza wrote:
> We want to support scounteren as a KVM CSR. The KVM UAPI defines every
> CSR size as target_ulong, and our env->scounteren is fixed at 32 bits.
>
> The other existing cases where the property size does not match the KVM
> r
On Fri, Apr 25, 2025 at 08:37:03AM -0300, Daniel Henrique Barboza wrote:
> We're missing the senvcfg CSRs which is already present in the
> KVM UAPI.
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
>
since we
> @@ -1226,6 +1281,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu,
> KVMScratchCPU *kvmcpu)
> }
>
> kvm_riscv_check_sbi_dbcn_support(cpu, reglist);
> +kvm_riscv_read_csr_cfg(reglist);
> }
>
> static void riscv_init_kvm_registers(Object *cpu_obj)
> @@ -1239,7 +1295,7 @@ static void riscv_init_kvm_registers(Object *cpu_obj)
>
> kvm_riscv_init_machine_ids(cpu, &kvmcpu);
> kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
> -kvm_riscv_init_multiext_cfg(cpu, &kvmcpu);
> +kvm_riscv_init_cfg(cpu, &kvmcpu);
>
> kvm_riscv_destroy_scratch_vcpu(&kvmcpu);
> }
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
r_cfg);
> +} else {
> +g_assert_not_reached();
> +}
>
> -KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
> -KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
> -KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
> -KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
> -KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
> -KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
> -KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
> -KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
> -KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
> +ret = kvm_set_one_reg(cs, csr_cfg->kvm_reg_id, ®);
> +if (ret) {
> +return ret;
> +}
> +}
>
> return 0;
> }
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
s)
> return ret;
> }
>
> -id = RISCV_CONFIG_REG(env, marchid);
> +id = RISCV_CONFIG_REG(marchid);
> ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid);
> if (ret != 0) {
> return ret;
> }
>
> -id = RISCV_CONFIG_REG(env, mimpid);
> +id = RISCV_CONFIG_REG(mimpid);
> ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid);
>
> return ret;
> @@ -1911,7 +1894,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu,
> Error **errp)
> if (cpu->cfg.ext_zicbom &&
> riscv_cpu_option_set(kvm_cbom_blocksize.name)) {
>
> -reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG,
> +reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG,
> kvm_cbom_blocksize.kvm_reg_id);
> reg.addr = (uint64_t)&val;
> ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®);
> @@ -1930,7 +1913,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu,
> Error **errp)
> if (cpu->cfg.ext_zicboz &&
> riscv_cpu_option_set(kvm_cboz_blocksize.name)) {
>
> -reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG,
> +reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG,
> kvm_cboz_blocksize.kvm_reg_id);
> reg.addr = (uint64_t)&val;
> ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®);
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx)
>
> -#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx)
> +#define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx)
>
> #define RISCV_VECTOR_CSR_REG(env, name) \
> kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \
> --
> 2.49.0
>
Otherwise,
Reviewed-by: Andrew Jones
| 29 ++---
> 1 file changed, 14 insertions(+), 15 deletions(-)
>
Reviewed-by: Andrew Jones
On Fri, Apr 25, 2025 at 08:36:58AM -0300, Daniel Henrique Barboza wrote:
> 'reglist' is being g+malloc'ed but never freed.
g_malloc'ed
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm
+1920,7 @@ static void virt_machine_class_init(ObjectClass *oc,
> void *data)
> mc->desc = "RISC-V VirtIO board";
> mc->init = virt_machine_init;
> mc->max_cpus = VIRT_CPUS_MAX;
> -mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +mc->default_cpu_type = TYPE_RISCV_CPU_MAX;
> mc->block_default_type = IF_VIRTIO;
> mc->no_cdrom = 1;
> mc->pci_allow_0_address = true;
> --
> 2.49.0
>
Reviewed-by: Andrew Jones
On Wed, Apr 23, 2025 at 04:45:29PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 4/23/25 12:15 PM, Andrew Jones wrote:
...
> > if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) {
> > kvm_cpu_csr_set_u32(cpu, csr_cfg, reg);
> > } else if (KV
On Thu, Apr 17, 2025 at 09:48:39AM -0300, Daniel Henrique Barboza wrote:
> The Linux kernel, up until at least version 6.12, has issues with a KVM
> guest setting scounteren to 0 during reset. No error will be thrown
> during boot, but trying to use rdtime in the guest (by executing 'ping'
> for ex
On Thu, Apr 17, 2025 at 09:48:38AM -0300, Daniel Henrique Barboza wrote:
> We're missing scounteren and senvcfg CSRs, both already present in the
> KVM UAPI.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
The patch changed enough that it's n
On Thu, Apr 17, 2025 at 09:48:37AM -0300, Daniel Henrique Barboza wrote:
> [1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6.
> This happens because the kernel does not know 'senvcfg', making it
> unable to boot because QEMU is reading/wriiting it without any checks.
>
> Afte
On Thu, Apr 17, 2025 at 09:48:36AM -0300, Daniel Henrique Barboza wrote:
> At this moment we're not checking if the host has support for any
> specific CSR before doing get/put regs. This will cause problems if the
> host KVM doesn't support it (see [1] as an example).
>
> We'll use the same appro
On Fri, Apr 04, 2025 at 02:37:32PM +0200, Philippe Mathieu-Daudé wrote:
> On 4/4/25 13:30, Daniel Henrique Barboza wrote:
> >
> >
> > On 4/4/25 2:50 AM, Alistair Francis wrote:
> > > On Fri, Mar 28, 2025 at 2:16 AM Philippe Mathieu-Daudé
> > > wrote:
> > > >
> > > > On 27/3/25 14:02, Daniel Hen
eady present in the
> > > KVM UAPI.
> > >
> > > Signed-off-by: Daniel Henrique Barboza
> > > Reviewed-by: Andrew Jones
> >
> > Acked-by: Alistair Francis
>
> This patch seems to have broken KVM acceleration for me:
>
> $ ./build/qemu-sy
On Mon, Feb 24, 2025 at 04:24:13PM +0800, Yong-Xuan Wang wrote:
> Support user-space emulation of SIREG and STOPEI CSR with KVM
> acceleration. For SIREG emulation, the SISELECT CSR value and iprio
> array must be loaded before handling, and since the iprio array might
> be modified, it must be wri
On Mon, Feb 24, 2025 at 04:24:12PM +0800, Yong-Xuan Wang wrote:
> Rewrite the kvm_riscv_handle_csr() to support additional CSR emulation
> in user space with KVM acceleration. This update reuses the TCG CSR
> emulation function to simplify the implementation and reduce the
> redundant work. Also it
se {
> +rcpu->cfg.ext_smaia = true;
> +}
> }
> +
> riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
>riscv_imsic_rmw, imsic);
> }
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
controller
> from
> - the irqchip. See :ref:`riscv-aia` for more details on all available AIA
> - modes.
> + the in-kernel irqchip. Or the kernel irqchip can be disabled by using
> + "-accel kvm,kernel-irqchip=off". In this case the ``virt`` machine will
> + emulate the APLIC and IMSIC controller in user-space instead of using
> in-kernel
> + irqchip. See :ref:`riscv-aia` for more details on all available AIA modes.
>
> - aia-guests=nnn
>
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
On Mon, Feb 24, 2025 at 04:24:09PM +0800, Yong-Xuan Wang wrote:
> Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA
> extension in VS mode.
>
> Signed-off-by: Yong-Xuan Wang
> ---
> target/riscv/kvm/kvm-cpu.c | 45 ++
> 1 file changed, 45 inserti
R_TABLE_SIZE);
>
> +return csr_ops[csr_no].name;
> +}
> +
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
> target_ulong riscv_new_csr_seed(target_ulong new_value,
> target_ulong write_mask);
>
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
On Mon, Feb 24, 2025 at 04:24:10PM +0800, Yong-Xuan Wang wrote:
> Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of
> Smstateen extension in VS mode.
>
> Signed-off-by: Yong-Xuan Wang
> ---
> target/riscv/kvm/kvm-cpu.c | 25 +
> 1 file changed, 25 insertio
REG(scause), env->scause);
> +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval);
> +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip);
> +KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp);
>
a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index ea8d77d06a..c93612b1da 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -360,6 +360,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
>
> cpu->cfg.ext_sha = r
FG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
> KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT),
> KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT),
> +KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC),
> };
>
> static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg)
> --
> 2.48.1
>
>
Reviewed-by: Andrew Jones
SCV_SET_CSR(cs, env, scounteren, env->scounteren);
> +KVM_RISCV_SET_CSR(cs, env, senvcfg, env->senvcfg);
>
> return 0;
> }
> --
> 2.48.1
>
Reviewed-by: Andrew Jones
pu->env.fdt_addr; /* a1 */
> -env->satp = 0;
> -env->mie = 0;
> -env->stvec = 0;
> -env->sscratch = 0;
> -env->sepc = 0;
> -env->scause = 0;
> -env->stval = 0;
> -env->mip = 0;
> +
> +kvm_riscv_reset_regs_csr(env);
> }
>
> void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> --
> 2.48.1
>
Reviewed-by: Andrew Jones
On Tue, Feb 18, 2025 at 01:38:53PM -0300, Daniel Henrique Barboza wrote:
> At this moment ziccrse is a TCG always enable ext that has no flag. KVM
> will expose ziccrse to users, allowing them to turn it on/off.
KVM won't allow this to be disabled, since it can't be (there's no way
to turn off the
On Fri, Feb 21, 2025 at 09:45:35AM +0100, Andrew Jones wrote:
> On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote:
> > Explictly reset env->mstatus and env->sie.
>
> mie was already getting set to zero, so that should have just been renamed
> in the
On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote:
> Explictly reset env->mstatus and env->sie.
mie was already getting set to zero, so that should have just been renamed
in the last patch, but I still think we should drop the last patch.
> Add a comment about env->mip
> bei
On Thu, Feb 20, 2025 at 01:13:12PM -0300, Daniel Henrique Barboza wrote:
> Using env->sie is clearer than using env->mie.
Maybe? Just as sstatus is a subset of mstatus, sip and sie can be
subsets of mip and mie. However, the AIA can change sip/sie so they
no longer alias mip/mie, which is why we h
m/kvm-cpu.c
> index 23ce779359..484b6afe7c 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1603,9 +1603,6 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> CPURISCVState *env = &cpu->env;
> int i;
>
> -if (!kvm_enabled()) {
> -return;
> -}
> for (i = 0; i < 32; i++) {
> env->gpr[i] = 0;
> }
> --
> 2.48.1
>
>
Reviewed-by: Andrew Jones
On Mon, Feb 17, 2025 at 04:17:24PM +0800, Yong-Xuan Wang wrote:
> Add a helper function to get CSR name from CSR number.
>
> Signed-off-by: Yong-Xuan Wang
> ---
> target/riscv/cpu.h | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/c
On Mon, Feb 17, 2025 at 04:17:27PM +0800, Yong-Xuan Wang wrote:
> The riscv-aia property only controls the in-kernel IMSIC mode, the
> emulation of AIA MSI mode is controlled by the kernel-irqchip property.
> Rename the riscv-aia property to riscv-imsic to prevent the confusion.
>
> Signed-off-by:
On Thu, Jan 16, 2025 at 03:59:34PM +0100, Philippe Mathieu-Daudé wrote:
> The VirtMachineClass::disallow_affinity_adjustment
> field was only used by virt-2.6 machine, which got
> removed. Remove it and simplify virt_cpu_mp_affinity().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw
rng_seed, sizeof(rng_seed));
>
> +qemu_fdt_add_subnode(ms->fdt, "/aliases");
> +
> create_fdt_flash(s, memmap);
> create_fdt_fw_cfg(s, memmap);
> create_fdt_pmu(s);
> --
> 2.46.0
>
Only fix the minor commit message issues if you need to respin for other
reasons.
Reviewed-by: Andrew Jones
On Thu, Jan 16, 2025 at 09:46:29AM +0100, Vasilis Liaskovitis wrote:
> This patch adds an "aliases" node with a "serial0" entry for the
> single UART in the riscv64 virt machine.
>
> This was requested in Gitlab #2774. However, since the machine only
> has one UART at the moment, it's not clear th
@@ -3198,6 +3236,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64,
> rva22u64_profile_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64,
> rva22s64_profile_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64,
> rva23u64_profile_cpu_init),
> +DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, MXL_RV64,
> rva23s64_profile_cpu_init),
> #endif /* TARGET_RISCV64 */
> };
>
> --
> 2.47.1
>
Otherwise,
Reviewed-by: Andrew Jones
; #endif
>
> if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED &&
> -profile->priv_spec != env->priv_ver) {
> +profile->priv_spec > env->priv_ver) {
> profile_impl = false;
>
> if (send_warn) {
> --
> 2.47.1
>
Reviewed-by: Andrew Jones
s change
...like we were doing with the previous 'parent'...
> does nothing for the existing profiles but will make RVA23S64 simpler.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 6 --
> targ
group_idx = hart_idx >> lhxw;
> -hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);
>
> addr = msicfgaddr;
> addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32;
> --
> 2.34.1
>
>
Reviewed-by: Andrew Jones
+
> 2 files changed, 33 insertions(+)
>
Reviewed-by: Andrew Jones
fsets = {
> diff --git a/tests/data/acpi/riscv64/virt/RHCT
> b/tests/data/acpi/riscv64/virt/RHCT
> index
> b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a
> 100644
> GIT binary patch
> delta 53
> zcmeBUp1{l%JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S
> I3K$s}0ARKZK>z>%
>
> delta 52
> zcmbQh+{ern6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF
> HMg|4|IwT82
>
> --
> 2.47.1
>
Reviewed-by: Andrew Jones
> delta 48
> zcmZo;?qlW(@^B96V`N}pOqj@Jz^cQ@$e^;(o|BQSxYW#~B4@H2qXkC_BLhPoBLf2f
> D`wIz-
>
> delta 41
> wcmeBUZe!*O@^B7mV`N}poG_8gfK`Q&kwIpoJtyPj07f&87)Az$G)4vn0JA^`U;qFB
>
> --
> 2.47.1
>
Reviewed-by: Andrew Jones
On Tue, Jan 14, 2025 at 04:00:01PM -0300, Daniel Henrique Barboza wrote:
> Add RVA23S64 as described in [1]. This profile inherits all mandatory
> extensions of RVA23U64, making it a child of the U64 profile.
>
> A new "rva23s64" profile CPU is also added. This is the generated
> riscv,isa for it
On Tue, Jan 14, 2025 at 01:08:46PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 1/14/25 11:52 AM, Andrew Jones wrote:
> > On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote:
> > > From the time we added RVA22U64 until now the spec didn&#x
Drop "in riscv_aplic_msi_send()" from the patch summary to make it more
concise.
On Tue, Jan 14, 2025 at 10:53:19AM +0800, Huang Borong wrote:
> The line "hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);" was removed
This just states what we can easily read from the patch.
> because the same
Background processing wake up signal */
> -unsigned core_exec; /* Processing thread execution actions */
> -
> /* IOMMU target address space */
> AddressSpace *target_as;
> MemoryRegion *target_mr;
> --
> 2.43.2
>
>
Otherwise,
Reviewed-by: Andrew Jones
ne RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2)
> -#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
> -#define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3)
> -#define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12)
> -
> -
> /*
> * struct riscv_iommu_msi_pte - MSI Page Table Entry
> */
> --
> 2.43.2
>
>
Reviewed-by: Andrew Jones
On Tue, Jan 14, 2025 at 10:20:12AM -0300, Daniel Henrique Barboza wrote:
> Add RVA23S64 as described in [1]. This profile inherits all mandatory
> extensions of RVA23U64, making it a child of the U64 profile.
>
> A new "rva23s64" profile CPU is also added. This is the generated
> riscv,isa for it
On Tue, Jan 14, 2025 at 10:20:12AM -0300, Daniel Henrique Barboza wrote:
> Add RVA23S64 as described in [1]. This profile inherits all mandatory
> extensions of RVA23U64, making it a child of the U64 profile.
>
> A new "rva23s64" profile CPU is also added. This is the generated
> riscv,isa for it
On Tue, Jan 14, 2025 at 10:20:11AM -0300, Daniel Henrique Barboza wrote:
> Add RVA23U64 as described in [1]. This profile does not share all
> mandatory RVA22U64 extensions so we can't use RVA22U64 as a parent. We
> need to declare all mandatory extensions from scratch.
But it does share all manda
On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote:
> From the time we added RVA22U64 until now the spec didn't declare 'RVB'
> as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
> [1] added the following in the 'RVA22U64 Mandatory Extensions' section:
>
> "
tateen should be sufficient), it's
already ratified, so into the alphabet soup it must go.
Reviewed-by: Andrew Jones
Thanks,
drew
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/tcg/tcg-cp
On Wed, Nov 06, 2024 at 10:34:00AM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> Now that we have merged the base IOMMU support we can re-introduce
> the riscv-iommu-sys platform device that was taken away from the initial
> posting.
>
> Aside from adding support for the device in the 'virt' ma
ease add this info in the commit message? This makes it clearer
> > that there's not much we can do in QEMU aside from erroring out.
> >
> > Also, please add a:
> >
> > Fixes: 48c2c33c52 ("target/riscv: select KVM AIA in riscv virt machine")
> &
Free the temporary register list.
Fixes: 608bdebb6075 ("target/riscv/kvm: support KVM_GET_REG_LIST")
Signed-off-by: Andrew Jones
---
target/riscv/kvm/kvm-cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index cb
uld be helpful.
Thanks,
drew
>
> Regards,
> Yong-Xuan
>
> On Fri, Nov 1, 2024 at 11:09 PM Andrew Jones wrote:
> >
> > On Fri, Nov 01, 2024 at 08:45:13AM -0300, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 11/1/24 5:36 AM, Yong-Xuan Wang w
On Fri, Nov 01, 2024 at 08:45:13AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 11/1/24 5:36 AM, Yong-Xuan Wang wrote:
> > Currently QEMU will continue to emulate the AIA MSI devices and enable the
> > AIA extension for guest OS when the host kernel doesn't support the
> > in-kernel AIA irqchip
On Wed, Oct 30, 2024 at 11:40:57AM +1000, Alistair Francis wrote:
> On Fri, Oct 11, 2024 at 9:19 PM Daniel Henrique Barboza
...
> > In case someone tries it out with multiple -accel options, this doesn't
> > work. Only
> > the first '-accel ' are parsed. This happens due to a known command
> > li
On Wed, Oct 30, 2024 at 11:44:19AM +1000, Alistair Francis wrote:
> On Tue, Oct 29, 2024 at 4:01 AM Daniel Henrique Barboza
> wrote:
> >
> > Hi,
> >
> > I had a change of heart w.r.t this work. I still believe that the boolean
> > properties
> > are better to deal with since we don't have to deal
On Thu, Oct 03, 2024 at 11:36:00AM GMT, Tomasz Jeznach wrote:
> On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 10/3/24 6:26 AM, Andrew Jones wrote:
> > > On Tue, Oct 01, 2024 at 10:02:
On Thu, Oct 03, 2024 at 10:06:11AM GMT, Daniel Henrique Barboza wrote:
>
>
> On 10/3/24 6:26 AM, Andrew Jones wrote:
> > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
> > ...
> > > +/*
> > > + * RISCV IOMMU Addre
On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
...
> +/*
> + * RISCV IOMMU Address Translation Lookup - Page Table Walk
> + *
> + * Note: Code is based on get_physical_address() from
> target/riscv/cpu_helper.c
> + * Both implementation can be merged into single helper func
On Tue, Oct 01, 2024 at 09:05:52PM GMT, Daniel Henrique Barboza wrote:
>
>
> On 10/1/24 8:28 PM, Tomasz Jeznach wrote:
> > On Tue, Sep 3, 2024 at 4:46 AM Daniel Henrique Barboza
> > wrote:
> > >
> > >
> > >
> > > On 8/26/24 11:18 PM, Tomasz Jeznach wrote:
> > > > On Fri, Aug 23, 2024 at 5:42
commit 6df664f87c73 ("Revert "hw/riscv/virt.c: imsics DT: add
'#msi-cells'"") removed #msi-cells. Now that we have a Linux
commit to reference add a comment explaining why it was removed
to avoid it getting added back due to DT validation failures.
Signed-off-b
FS, env->misa_mxl);
> +for (int regnr = 0; regnr < 32; ++regnr) {
> +env->fpr[regnr] = 0;
> +}
> +riscv_csrrw(env, CSR_FCSR, NULL, 0, -1);
> +}
> #ifndef CONFIG_USER_ONLY
> env->misa_mxl = mcc->misa_mxl_max;
> env->priv = PRV_M;
> --
> 2.45.2
>
Reviewed-by: Andrew Jones
cb, KVM_RISCV_ISA_EXT_ZCB),
> +KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD),
> +KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF),
> KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND),
> KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE),
> KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH),
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Wed, Sep 18, 2024 at 03:49:39PM GMT, Heinrich Schuchardt wrote:
> On 18.09.24 15:12, Peter Maydell wrote:
> > On Wed, 18 Sept 2024 at 14:06, Heinrich Schuchardt
> > wrote:
> > > Thanks Peter for looking into this.
> > >
> > > QEMU's cpu_synchronize_all_post_init() and
> > > do_kvm_cpu_synchron
On Wed, Sep 18, 2024 at 04:37:12PM GMT, Aleksei Filippov wrote:
>
>
> On 17.09.2024 16:10, Andrew Jones wrote:
> > On Tue, Sep 17, 2024 at 02:29:41PM GMT, Andrew Jones wrote:
> > > On Tue, Sep 17, 2024 at 02:54:33PM GMT, Alexei Filippov wrote:
> > > > k
On Tue, Sep 17, 2024 at 06:45:21PM GMT, Heinrich Schuchardt wrote:
...
> When thinking about the migration of virtual machines shouldn't QEMU be in
> control of the initial state of vcpus instead of KVM?
>
Thinking about this more, I'm inclined to agree. Initial state and reset
state should be tra
On Tue, Sep 17, 2024 at 03:28:42PM GMT, Heinrich Schuchardt wrote:
> On 17.09.24 14:13, Andrew Jones wrote:
> > On Mon, Sep 16, 2024 at 08:16:33PM GMT, Heinrich Schuchardt wrote:
> > > OpenSBI enables the floating point in mstatus. For consistency QEMU/KVM
> &
On Tue, Sep 17, 2024 at 02:29:41PM GMT, Andrew Jones wrote:
> On Tue, Sep 17, 2024 at 02:54:33PM GMT, Alexei Filippov wrote:
> > kvm_riscv_handle_sbi() may return not supported return code to not
> > trigger qemu abort with vendor-specific sbi.
> >
> > Add new error p
On Mon, Sep 09, 2024 at 01:27:05PM GMT, Alistair Francis wrote:
> On Tue, Aug 6, 2024 at 7:05 AM Gregor Haas wrote:
> >
> > This patch series adds support for specifying OpenSBI domains on the QEMU
> > command line. A simple example of what this looks like is below, including
> > mapping the board
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