On Thu, 2025-06-19 at 11:23 +0200, Cédric Le Goater wrote:
> Hi,
>
> This is a follow up of a private discussion with Patrick.
>
> Aspeed modeling started nearly 10y ago with the palmetto-bmc machine.
> We now have 5 SoCs and 25 machines which are mostly defined in
> in a single aspeed.c file. Mu
entations are 32-bit.
> Set min/max access_size accordingly.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Andrew Jeffery
ast2500 and
> ast2600 datasheets.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2636
> Signed-off-by: Joel Stanley
> Reviewed-by: Troy Lee
> Message-ID: <20241118021820.4928-1-j...@jms.id.au>
> [PMD: Rebased, only including SCU changes]
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Andrew Jeffery
Hi Patrick,
On Thu, 2025-02-27 at 15:42 +, Patrick Venture wrote:
> eth_hdr requires 2 byte alignment
>
> Signed-off-by: Patrick Venture
> ---
> hw/net/ftgmac100.c | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac10
On Tue, 2025-02-18 at 08:35 +0100, Cédric Le Goater wrote:
> The SoC type name is stored under AspeedSoCClass which is
> redundant. Use object_get_typename() instead where needed.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
Hi Jamin,
> > >
> > > The design of the OR gates for GICINT 196 is as follows:
> >
> > 196? You discuss 192 below.
> >
> Sorry typo. I update my comments.
>
> The design of the OR gates for GICINT 196 is as follows:
> It has interrupt sources ranging from 0 to 31, with its output pin connected
On Tue, 2025-02-04 at 09:43 +, Jamin Lin wrote:
> Hi Andrew,
>
> > -Original Message-
> > From: Andrew Jeffery
> > Sent: Thursday, January 30, 2025 12:20 PM
> > To: Jamin Lin ; Cédric Le Goater ;
> > Peter Maydell ; Steven Lee
> > ; Troy Lee
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The HACE controller between AST2600 and AST2700 are almost identical.
> The HACE controller registers base address starts at 0x1207_ and
> its alarm interrupt is connected to GICINT4.
>
> Signed-off-by: Jamin Lin
Revi
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> Introduce a new ast2700 class to support AST2700.
>
> Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The memory map for AST2700 A1 remains compatible with AST2700 A0.
> However, the IRQ mapping has been updated for AST2700 A1, with GIC
> interrupts
> now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1.
>
> Introduce "aspeed_mac
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The design of INTC controllers has significantly changed in AST2700 A1.
>
> There are a total of 480 interrupt sources in AST2700 A1. For interrupt
> numbers
> from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
> limitatio
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> Added new definitions for AST2700_A1_SILICON_REV and
> AST2750_A1_SILICON_REV to
> identify the A1 silicon revisions.
>
> Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the
> SCU
> registers.
>
> Signed-off-by: Jamin Lin
>
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to
> input and
> output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was
> used to
> derive the IRQ index numbers.
>
> However, the INTC0 controller also supports GICI
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The previous implementation set the "aspeed_intc_ops" struct,
> containing read
> and write callbacks, to be used when I/O is performed on the INTC
> region.
> Both "aspeed_intc_read" and "aspeed_intc_write" callback functions
> were used
> for
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The design of the INTC has significant changes in the AST2700 A1. In
> the
> AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
> there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
>
> The previous INTC mod
On Wed, 2025-01-29 at 18:03 +0100, Cédric Le Goater wrote:
> On 1/21/25 08:04, Jamin Lin wrote:
> > The design of the INTC has significant changes in the AST2700 A1.
> > In the
> > AST2700 A0, there was one INTC controller, whereas in the AST2700
> > A1,
> > there were two INTC controllers: INTC0 (
On Wed, 2025-01-29 at 08:19 +0100, Cédric Le Goater wrote:
> On 1/29/25 00:29, Andrew Jeffery wrote:
> > Hi Cédric,
> >
> > On Tue, 2025-01-28 at 22:41 +0100, Cédric Le Goater wrote:
> > > Hello,
> > >
> > > This series updates the OpenBMC firmw
Hi Cédric,
On Tue, 2025-01-28 at 22:41 +0100, Cédric Le Goater wrote:
> Hello,
>
> This series updates the OpenBMC firmware images to the latest version
> for existing tests and also adds 2 new tests for Aspeed machines
> which
> were not tested before : witherspoon and bletchley.
>
> Thanks,
>
On Mon, 2024-12-16 at 15:53 +0800, Jamin Lin wrote:
> It set "aspeed_timer_ops" struct which containing read and write
> callbacks
> to be used when I/O is performed on the TIMER region.
>
> Besides, in the previous design of ASPEED SOCs, the timer registers
> address
> space are contiguous.
>
>
On Wed, 2024-12-04 at 12:39 -0800, Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier
> ---
> docs/system/arm/fby35.rst | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
> index bf6da6baa2a..ed9faef363c 100644
> --- a/docs/sy
On Fri, 2024-11-22 at 14:50 -0800, Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier
Reviewed-by: Andrew Jeffery
e Goater
Nice!
Reviewed-by: Andrew Jeffery
e/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> index cbeacb214c..879bdb96ee 100644
> --- a/include/hw/arm/aspeed.h
> +++ b/include/hw/arm/aspeed.h
> @@ -39,6 +39,7 @@ struct AspeedMachineClass {
> uint32_t macs_mask;
> void (*i2c_init)(AspeedMachineState *bmc);
> uint32_t uart_default;
> + bool sdhci_wp_invert;
Other than also calling this `sdhci_wp_inverted` to match my comment on
the earlier patch about the model property and devicetree bindings,
Reviewed-by: Andrew Jeffery
x27;re W1C bits.
Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on the
AST2600")
Reviewed-by: Andrew Jeffery
Thanks,
Andrew
On Tue, 2024-10-29 at 17:17 +0800, Jamin Lin wrote:
> The Write Protect pin of SDHCI model is default active low to match
> the SDHCI
> spec. So, write enable the bit 19 should be 1 and write protected the
> bit 19
> should be 0 at the Present State Register (0x24). However, some board
> are
> desi
-softmmu build we get:
# config AT24C depends on I2C
# select AT24C if NPCM7XX
# => AT24C is now True
# config AT24C default y if E500
# config AT24C default n
Seems reasonable that the Aspeed models should select it themselves
given they depend on the symbols.
Reviewed-by: Andrew Jeffery
On Mon, 2024-10-21 at 14:39 +0200, Cédric Le Goater wrote:
> On 10/18/24 07:31, Jamin Lin wrote:
> > Currently, these test cases used the hardcode offset 0x140 (0x14000 *
> > 256)
> > which was beyond the 16MB flash size for flash page read/write command
> > testing.
> > However, the default
On Sat, 2024-10-12 at 08:20 +0200, Cédric Le Goater wrote:
> + Aspeed reviewers. Sorry about that.
All good. Seems sensible in concept and from a cursory glance, so if
you want to tack it on:
Acked-by: Andrew Jeffery
> It should only clear bit 0 in index mode and the correct result
> should be as following.
>
>set->int_status == 0b11
>s->pending == 2
>
>pending == 1
>s->pending == 1
>set->int_status == 0b10
>
Maybe this is a bit forward, but:
Sug
patible AST2700.
> Introduce new aspeed_gpio_2700_read/aspeed_gpio_2700_write callback functions
> and aspeed_gpio_2700_ops memory region operation for AST2700.
> Introduce a new ast2700 class to support AST2700.
>
> Signed-off-by: Jamin Lin
Some of the wrapping in the commit message could be improved, but
otherwise:
Reviewed-by: Andrew Jeffery
On Wed, 2024-09-25 at 11:34 +0800, Jamin Lin wrote:
>
> +/* interrupt status */
> +if (SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS)) {
> +pending = extract32(set->int_status, pin_idx, 1);
> +if (pending) {
> +if (s->pending) {
> +assert(s->pe
Hi Jamin,
On Wed, 2024-09-25 at 11:34 +0800, Jamin Lin wrote:
> The interrupt status field is W1C, where a set bit on read indicates an
> interrupt is pending. If the bit extracted from data is set it should
> clear the corresponding bit in group_value. However, if the extracted
> bit is clear the
On Tue, 2024-09-24 at 06:48 +, Jamin Lin wrote:
> Hi Andrew,
>
> > Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> >
> > Hi Andrew,
> >
> > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> > >
> > > Hi Jamin,
> > >
> > >
> > > > +}
> > > > +set->int_
On Tue, 2024-09-24 at 03:03 +, Jamin Lin wrote:
> Hi Andrew,
>
> > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support
> >
> > Hi Jamin,
> >
> > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote:
> >
> > > +
> > > +/* interrupt status */
> > > +group_value = set->int_statu
Hi Jamin,
On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote:
> AST2700 integrates two set of Parallel GPIO Controller
> with maximum 212 control pins, which are 27 groups.
> (H, exclude pin: H7 H6 H5 H4)
>
> In the previous design of ASPEED SOCs,
> one register is used for setting one function f
t;
> hw/char/serial-isa.c:#include "hw/char/serial.h"
> hw/char/serial-pci.c:#include "hw/char/serial.h"
>
> Signed-off-by: Bernhard Beschow
> ---
> include/hw/arm/aspeed_soc.h | 2 +-
...
> hw/arm/aspeed_ast2400.c | 2 +-
> hw/arm/aspeed_soc_common.c | 2 +-
For the Aspeed bits:
Tested-by: Andrew Jeffery
its/aspeed-9.1
I built the series using the tree you linked above. It works well!
In that context:
Tested-by: Andrew Jeffery
was set. Add a
> property to set or unset this bit. This is useful to test boot images.
>
> For now, only activate this property on the ast2600-evb and rainier-bmc
> machines for which eMMC images are available or can be built.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
attribute first.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> This value is taken from a running Rainier machine.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
v_new(emmc ? TYPE_EMMC : TYPE_SD_CARD);
> +if (emmc) {
> +qdev_prop_set_uint8(card, "boot-config", boot_emmc ? 0x48 : 0x0);
0x48 feels a little bit magic. I poked around a bit and there are some
boot-config macros, but not the ones you need and they're all in an
"internal" header anyway. I guess this is fine for now?
Reviewed-by: Andrew Jeffery
port, so return false
> always for these.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
(0x1 << 23)
>
> +/* STRAP1 SCU500 */
> +#define AST2600_HW_STRAP_BOOT_SRC_EMMC(0x1 << 2)
> +#define AST2600_HW_STRAP_BOOT_SRC_SPI (0x0 << 2)
Maybe these should have a `SCU_` prefix for consistency?
Anyway:
Reviewed-by: Andrew Jeffery
flash device is.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Andrew Jeffery
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
> From: Cédric Le Goater
>
> The QEMU device representing the eMMC device of machine is currently
> created with type SD_CARD. Change the type to EMMC now that it is
> available.
>
> Signed-off-by: Cédric Le Goater
On Tue, 2024-07-02 at 18:15 +0200, Philippe Mathieu-Daudé wrote:
> On 2/7/24 07:06, Andrew Jeffery wrote:
> > On Fri, 2024-06-28 at 11:16 +0200, Cédric Le Goater wrote:
> > > On 6/28/24 9:02 AM, Philippe Mathieu-Daudé wrote:
> > > > When booting U-boot/Linux on Aspeed
On Fri, 2024-06-28 at 11:16 +0200, Cédric Le Goater wrote:
> On 6/28/24 9:02 AM, Philippe Mathieu-Daudé wrote:
> > When booting U-boot/Linux on Aspeed boards via eMMC,
> > some commands don't behave as expected from the spec.
> >
> > Add the 'x-aspeed-emmc-kludge' property to allow non
> > standar
> #6 0x55a5d9376399 in flatview_read_continue system/physmem.c:2877:19
> #7 0x55a5d93775b8 in flatview_read system/physmem.c:2907:12
>
> Signed-off-by: Zheyu Ma
Reviewed-by: Andrew Jeffery
> #6 0x55a5d9376399 in flatview_read_continue system/physmem.c:2877:19
> #7 0x55a5d93775b8 in flatview_read system/physmem.c:2907:12
>
> Signed-off-by: Zheyu Ma
Reviewed-by: Andrew Jeffery
> ---
> Changes in v3:
> - Add the reproducer
>
> Changes in v2:
> - Introduce
Hello Zheyu Ma,
On Tue, 2024-06-18 at 15:09 +0200, Zheyu Ma wrote:
> Added bounds checking in the aspeed_gpio_read() and aspeed_gpio_write()
> functions to ensure the index idx is within the valid range of the
> reg_table array.
>
> The correct size of reg_table is determined dynamically based on
27;m not very active wrt qemu these days but am still interested in
Aspeed-related patches. For what it's worth:
Reviewed-by: Andrew Jeffery
> ---
> MAINTAINERS | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 951556224a..0f63bcd
Goater
Acked-by: Andrew Jeffery
On Tue, 2023-12-12 at 17:29 +0100, Philippe Mathieu-Daudé wrote:
> Set the properties on the a7mpcore object to let it create and
> wire the CPU cores. Remove the redundant code.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Andrew Jeffery
st2600.c | 6 ++
For my own benefit it looks like the motivating thread for this series
is:
https://lore.kernel.org/qemu-devel/936e1ac4-cef8-08b4-c688-e5b1e0572...@linaro.org/
Anyway,
Reviewed-by: Andrew Jeffery # aspeed
ow |
> Device--+--+-+
> State Low | Low | Low |
> --+--+-+
>
> Signed-off-by: Glenn Miles
Reviewed-by: Andrew Jeffery
;
> Signed-off-by: Glenn Miles
Reviewed-by: Andrew Jeffery
On Thu, 2023-10-26 at 10:27 -0500, Ninad Palsule wrote:
> Hello Cedric,
>
>
> On 10/24/23 10:21, Cédric Le Goater wrote:
> > On 10/24/23 17:00, Ninad Palsule wrote:
> > > Hello Cedric,
> > >
> > > On 10/24/23 02:46, Cédric Le Goater wrote:
> > > > and the fsi_opb_* routines are useless to me.
>
On Wed, 2023-10-25 at 10:57 +0200, Cédric Le Goater wrote:
> On 10/24/23 11:36, Cédric Le Goater wrote:
> > On 9/25/23 08:22, Andrew Jeffery wrote:
> > > I've changed employers, have company email that deals with patch-based
> > > workflows without too much of a
On Wed, 2023-10-25 at 11:22 +0200, Klaus Jensen wrote:
> On Oct 25 11:14, Cédric Le Goater wrote:
> > It seems that the "at24c-eeprom" model doesn't have a maintainer. Until
> > this is sorted out, may be this change could go through the NVMe queue
> > since it is related.
> >
>
> I can, but I'm
7;t forget to collect those on your
patches before sending out a new set. Something for next time :)
Anyway,
Reviewed-by: Andrew Jeffery
On Fri, 2023-10-20 at 13:23 -0500, Glenn Miles wrote:
> The pca9552 code was updating output GPIO states whenever
> the pin state was updated even if the state did not change.
> This commit adds a check so that we only update the GPIO
> output when the pin state actually changes.
Given this is int
On Fri, 2023-10-20 at 11:32 -0500, Miles Glenn wrote:
> On Fri, 2023-10-20 at 11:42 +0200, Philippe Mathieu-Daudé wrote:
> > On 20/10/23 04:51, Andrew Jeffery wrote:
> > > On Thu, 2023-10-19 at 15:40 -0500, Glenn Miles wrote:
> > > > > The pca9552 INPUT0 and
On Thu, 2023-10-19 at 15:40 -0500, Glenn Miles wrote:
> Allow external devices to drive pca9552 input pins by adding
> input GPIO's to the model. This allows a device to connect
> its output GPIO's to the pca9552 input GPIO's.
>
> In order for an external device to set the state of a pca9552
> pi
it to a logical 1.
> > + */
> > + qemu_set_irq(s->gpio[i], 1);
> > +s->regs[input_reg] |= 1 << input_shift;
> > +break;
So the witherspoon-bmc machine was a user of the PCA9552 outputs as
LEDs. I guess its LEDs were in the w
On Mon, 25 Sep 2023, at 18:50, Cédric Le Goater wrote:
> On 9/25/23 09:54, Andrew Jeffery wrote:
>>
>>
>> On Fri, 22 Sep 2023, at 22:51, Cédric Le Goater wrote:
>>> Joel, Andrew,
>>>
>>> On 5/25/19 17:12, Cédric Le Goater wrote:
>>>&g
On Mon, 25 Sep 2023, at 17:28, Cédric Le Goater wrote:
> On 9/25/23 08:22, Andrew Jeffery wrote:
>> I've changed employers, have company email that deals with patch-based
>> workflows without too much of a headache, and am trying to steer some
>> content out of my pe
to schedule the timer
>> expiry as the guest requests, but if we have missed the deadline we
>> re interrupt and try again, which allows the guest to catch up.
>>
>> Provides expected behaviour with old and new guest code.
>>
>> Fixes: c04bd47db6b9 (&q
ontainer, 0x0, &s->iomem);
>>
>> for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) {
>> -Object *dev = OBJECT(&s->devices[i]);
>> +Object *i3c_dev = OBJECT(&s->devices[i]);
Maybe `s/i3c_dev/subdev`? I du
I've changed employers, have company email that deals with patch-based
workflows without too much of a headache, and am trying to steer some
content out of my personal mail.
Signed-off-by: Andrew Jeffery
---
Hi Cédric, do you mind including this in your Aspeed queue?
MAINTAINERS | 2
ation :)
Reviewed-by: Andrew Jeffery
> ---
> hw/i2c/smbus_master.c | 26 ++
> include/hw/i2c/smbus_master.h | 2 ++
> 2 files changed, 28 insertions(+)
>
> diff --git a/hw/i2c/smbus_master.c b/hw/i2c/smbus_master.c
> index 6a53c3
@huawei.com/
> [2]:
> https://lore.kernel.org/qemu-devel/20221121080445.ga29...@codeconstruct.com.au/
>
> Tested-by: Jonathan Cameron
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Klaus Jensen
Nice!
Reviewed-by: Andrew Jeffery
fprintf(stderr, "nmi command 0x%x not handled\n", request->opc);
> +
> +break;
> +}
> +}
> +
> +static void nmi_reset(MCTPI2CEndpoint *mctp)
> +{
> +NMIDevice *nmi = NMI_I2C_DEVICE(mctp);
> +nmi->len = 0;
> +}
> +
>
to 0h
https://nvmexpress.org/wp-content/uploads/NVM-Express-Management-Interface-Specification-1.2c-2022.10.06-Ratified.pdf
This change makes it possible to expose NVMe VPD in a manner that can be
dynamically detected by OpenBMC.
Signed-off-by: Andrew Jeffery
---
hw/nvram/eeprom_at24c.c | 18 +
Hi Klaus,
On Thu, 2023-09-14 at 08:51 +0200, Klaus Jensen wrote:
> On Sep 12 13:50, Andrew Jeffery wrote:
> > Hi Klaus,
> >
> > On Tue, 2023-09-05 at 10:38 +0200, Klaus Jensen wrote:
> > > >
> > > > +static void nmi_handle_mi_config_ge
Hi Klaus,
On Tue, 2023-09-05 at 10:38 +0200, Klaus Jensen wrote:
> >
> > +static void nmi_handle_mi_config_get(NMIDevice *nmi, NMIRequest
> > *request)
> > +{
> > + uint32_t dw0 = le32_to_cpu(request->dw0);
> > + uint8_t identifier = FIELD_EX32(dw0,
> > NMI_CMD_CONFIGURATION_GET_DW0,
> > +
On Wed, 24 May 2023, at 17:14, Joel Stanley wrote:
> On Wed, 24 May 2023 at 06:38, Cédric Le Goater wrote:
>>
>> But, I also got this :
>>
>>root@p10bmc:~# [ 91.656331] watchdog: watchdog0: watchdog did not stop!
>>[ 91.734858] systemd-shutdown[1]: Using hardware watchdog 'aspeed_wd
/447
I've build tested the two as a sanity check.
Cheers,
Andrew
Andrew Jeffery (2):
linux-user: elfload: s/min_mmap_addr/mmap_min_addr/
linux-user: elfload: Specify -R is an option for qemu-user binaries
linux-user/elfload.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--
2.39.2
As-is the error message can cause some confusion as the mentioned sysctl
attribute name is wrong:
https://www.kernel.org/doc/html/latest/admin-guide/sysctl/vm.html#mmap-min-addr
Signed-off-by: Andrew Jeffery
---
linux-user/elfload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Given several different concepts are suggested for investigation, let's
not confuse e.g. ulimit's -R with what was actually intended.
Signed-off-by: Andrew Jeffery
---
linux-user/elfload.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/elfload.c b/
On Thu, 19 Jan 2023, at 23:14, Joel Stanley wrote:
> Enough model to capture the pinmux writes to enable correct operation of
> the parts of pinmux that depend on GFX registers.
>
> Signed-off-by: Joel Stanley
> ---
> include/hw/arm/aspeed_soc.h | 3 +
> include/hw/misc/aspeed_gfx.h | 31 +
On Sun, 31 Jul 2022, at 06:48, Cédric Le Goater wrote:
> On 7/29/22 19:30, Peter Delevoryas wrote:
>> Certainly we'd like to use IRQ's instead, but she ran into correctness
>> problems. Maybe we can investigate that further and fix it.
Yes, let's not work around problems that we have the abilit
On Mon, 25 Jul 2022, at 16:02, Cédric Le Goater wrote:
> On 7/25/22 04:08, Andrew Jeffery wrote:
>>
>>
>> On Fri, 22 Jul 2022, at 16:06, Cédric Le Goater wrote:
>>> aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
>>> mc-&
On Fri, 22 Jul 2022, at 16:06, Cédric Le Goater wrote:
> A mx25l25635f chip model is generally found on these machines. It's
> newer and uses 4B opcodes which is better to exercise the support in
> the Linux kernel.
>
> Signed-off-by: Cédric Le Goater
> ---
> hw/arm/aspeed.c | 6 +++---
> 1 fi
I think we've sorted this out, but replying to finalise the conversation
On Tue, 12 Jul 2022, at 11:27, Peter Delevoryas wrote:
> On Mon, Jul 11, 2022 at 10:56:08PM +0930, Andrew Jeffery wrote:
>>
>> /*
>> @@ -607,7 +608,7 @@ static void aspeed_gpio_write(void
On Fri, 8 Jul 2022, at 04:34, Peter Delevoryas wrote:
> On Thu, Jul 07, 2022 at 10:53:57AM -0700, Peter Delevoryas wrote:
>> On Thu, Jul 07, 2022 at 10:56:02AM +0200, Cédric Le Goater wrote:
>> > On 7/7/22 09:17, Peter Delevoryas wrote:
>> > > It seems that aspeed_gpio_update is allowing the val
On Thu, 7 Jul 2022, at 17:50, Joel Stanley wrote:
> On Thu, 7 Jul 2022 at 07:17, Peter Delevoryas wrote:
>>
>> It seems that aspeed_gpio_update is allowing the value for input pins to be
>> modified through register writes and QOM property modification.
>>
>> The QOM property modification is fi
On Mon, 16 May 2022, at 16:48, Cédric Le Goater wrote:
> On 5/16/22 08:23, Peter Delevoryas wrote:
>> v2:
>> - Rebased on Cedric's irq proposal. [1]
>> - Added "Introduce common UART init function" patch
>> - Added "Add uarts_num SoC attribute" patch
>> - Rewrote last commit's message for clarit
On Tue, 8 Feb 2022, at 01:34, Andrew Jeffery wrote:
> Hello,
>
> This series adds support for a new register interface supported by the
> Aspeed GPIO controller, present in at least the AST2600.
>
> The new interface is a single register implementing an indirect command
>
Not sure how that got there.
Signed-off-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 911d21c8cfbe..c63634d3d3e2 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
ested one way by poking the driver using the
libgpiod tools and then the other using devmem to drive the new
interface.
Please review!
Andrew
Andrew Jeffery (3):
hw: aspeed_gpio: Cleanup stray semicolon after switch
hw: aspeed_gpio: Split GPIOSet handling from accessors
hw: aspeed_gpio: Su
tedious data model, but allowed efficient multi-line
bit-banging.
Either way, the hardware model in qemu becomes quite complex, though it
would have been less so had the new interface been the only one
available.
Signed-off-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 202
Pave the way for implementing the new register interface for GPIO
control provided by the AST2600. We need a consistent data model, so
do some work to enable use of the AspeedGPIOReg / GPIOSets data
structures for both.
Signed-off-by: Andrew Jeffery
---
hw/gpio/aspeed_gpio.c | 105
On Wed, 3 Nov 2021, at 02:48, Peter Maydell wrote:
> On Mon, 1 Nov 2021 at 18:31, Cédric Le Goater wrote:
>>
>> I haven't done any Aspeed development for a couple of years now and
>> maintaining the Aspeed QEMU machines has been a side project since.
>> I don't have time anymore.
>
> Thanks for
Hi Cédric, Peter,
On Tue, 31 Aug 2021, at 20:09, Cédric Le Goater wrote:
> On 8/28/21 5:58 PM, Peter Delevoryas wrote:
> > I think I’m a little confused on this part. What I meant by “most machines
> > just use UART5” was that most DTS’s use “stdout-path=&uart5”, but fuji uses
> > “stdout-path=&
t and get")
Signed-off-by: Andrew Jeffery
---
hw/misc/pca9552.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
index b7686e27d7fa..fff19e369a39 100644
--- a/hw/misc/pca9552.c
+++ b/hw/misc/pca9552.c
@@ -272,7 +272,7 @@ static void pca955
On Fri, 9 Jul 2021, at 16:59, Philippe Mathieu-Daudé wrote:
> On 7/9/21 7:31 AM, Andrew Jeffery wrote:
> > The logic in the handling for the control register required toggling the
> > enable state for writes to stick. Rework the condition chain to allow
> > sequential writ
ensure model
behaviour reflects the hardware.
Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery
---
hw/watchdog/wdt_aspeed.c | 24 ++--
include/hw/watchdog/wdt_aspeed.h | 1 +
2 files changed, 23 insertions(+), 2
The logic in the handling for the control register required toggling the
enable state for writes to stick. Rework the condition chain to allow
sequential writes that do not update the enable state.
Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andr
n was that sequential writes to
control weren't sticking if the enable bit wasn't toggled, which is fixed in the
second patch.
Please review.
Andrew
Andrew Jeffery (2):
watchdog: aspeed: Sanitize control register values
watchdog: aspeed: Fix sequential control writes
hw/watchd
On Fri, 25 Jun 2021, at 14:36, Joel Stanley wrote:
> These are the devices documented by the Rainier device tree. With this
> we can see the guest discovering the multiplexers and probing the eeprom
> devices:
>
> i2c i2c-2: Added multiplexed i2c bus 16
> i2c i2c-2: Added multiplexed i2c bus
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