[PATCH 2/2] target/riscv: remove fixed numbering from GDB xml feature files

g. ARM, AArch64, Loongarch, m68k, rx, and s390. Signed-off-by: Andrew Burgess --- gdb-xml/riscv-32bit-cpu.xml | 6 +- gdb-xml/riscv-32bit-fpu.xml | 6 +- gdb-xml/riscv-64bit-cpu.xml | 6 +- gdb-xml/riscv-64bit-fpu.xml | 6 +- 4 files changed, 4 insertions(+), 20 deletions(-) d

[PATCH 1/2] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml

I will simplify riscv_gdb_get_fpu and riscv_gdb_set_fpu, removing the extra handling for the 3 status registers. Signed-off-by: Andrew Burgess --- gdb-xml/riscv-32bit-fpu.xml | 4 gdb-xml/riscv-64bit-fpu.xml | 4 target/riscv/gdbstub.c | 32 ++-- 3 f

[PATCH 0/2] target/riscv: improvements to GDB target descriptions

I was running some GDB tests against QEMU, and noticed some oddities with the target description QEMU sends, the following two patches address these issues. Thanks, Andrew --- Andrew Burgess (2): target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml target/riscv: remove fixed