[PATCH 1/2] target/riscv: Fix up masking of vsip/vsie accesses

arget/riscv: Implement AIA CSRs for 64 local interrupts on RV32") Signed-off-by: Andrew Bresticker --- target/riscv/csr.c | 35 +++ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c9a7ee287..984548b

[PATCH 2/2] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1

Per the AIA specification, writes to stimecmp from VS level should trap when hvictl.VTI is set since the write may cause vsip.STIP to become unset. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support") Signed-off-by: Andrew Bresticker --- target/riscv/csr.c | 6 ++ 1 file

[PATCH] target/riscv: Wake on VS-level external interrupts

which already accounts for VSEIP. Signed-off-by: Andrew Bresticker --- target/riscv/cpu.c| 2 +- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a91253d4bd..c6cc08c355

Re: [PATCH v2 1/6] hw/riscv: virt: Add a machine done notifier

Hi Alistair, On Wed, Apr 6, 2022 at 10:05 PM Alistair Francis wrote: > > From: Alistair Francis > > Move the binary and device tree loading code to the machine done > notifier. This allows us to prepare for editing the device tree as part > of the notifier. > > This is based on similar code in t