Hi Alistair,
> > @@ -936,6 +936,11 @@ restart:
> > return TRANSLATE_FAIL;
> > }
> >
> > +/* PTE reserved bits must be cleared otherwise an exception is
> > raised */
> > +if (riscv_cpu_mxl(env) == MXL_RV64 && (pte & PTE_RESERVED)) {
> > +return TR
> > AFAICT, Ztso allows the forwarding in question too. Simulations with
> > the axiomatic formalization confirm such expectation:
>
> OK that seems to be what it says in:
> https://five-embeddev.com/riscv-isa-manual/latest/ztso.html
> 'In both of these memory models, it is the that allows a ha
> > > Is x86's brand of memory ordering strong enough for Ztso?
> > > I thought x86 had an optimisation where it was allowed to store forward
> > > within the current CPU causing stores not to be quite strictly ordered.
[...]
> then a bit further down, '8.2.3.5 Intra-Processor Forwarding Is Allow
