igned-off-by: Jerome Forissier
Good catch!
So I can confirm that this fixes the issue, given a TF-A patch to actually
enable SME (and SVE).
Checked against the ARM ARM, also verified that the
defines don't accidentally changed their values.
Revie
On Sun, 30 Jan 2022 23:35:37 +0100
Niek Linnenbank wrote:
Hi,
(CC:ing Samuel for his intimate Allwinner BootROM knowledge)
> Hi Peter,
>
>
>
> On Thu, Jan 27, 2022 at 4:46 PM Peter Maydell
> wrote:
>
> > Change the allwinner-h3 based board to use the new boot.c
> > functionality to allow u
On Wed, 19 Jan 2022 10:15:52 +
Peter Maydell wrote:
Hi Peter,
> On Tue, 18 Jan 2022 at 23:30, Andre Przywara wrote:
> > Looking at k-u-t's arm/gic.c and QEMU's hw/intc/arm_gic.c I see two
> > problems here: QEMU implements word accesses as four successive ca
On Tue, 18 Jan 2022 19:41:56 +
Peter Maydell wrote:
Hi Peter, Alex,
thanks for the heads up!
> On Tue, 18 Jan 2022 at 17:42, Alex Bennée wrote:
> >
> >
> > Peter Maydell writes:
> >
> > > I've been working on the ITS to add support for the GICv4 functionality.
> > > In the course of tha
On Thu, 14 Oct 2021 09:17:52 -0600
Simon Glass wrote:
> Hi Tom,
>
> On Thu, 14 Oct 2021 at 08:56, Tom Rini wrote:
> >
> > On Wed, Oct 13, 2021 at 12:06:02PM -0600, Simon Glass wrote:
> > > Hi François,
> > >
> > > On Wed, 13 Oct 2021 at 11:35, François Ozog
> > > wrote:
> > > >
> > > > Hi
On Tue, 12 Oct 2021 19:01:04 -0600
Simon Glass wrote:
Hi,
> With Ilias' efforts we have dropped OF_PRIOR_STAGE and OF_HOSTFILE so
> there are only three ways to obtain a devicetree:
>
>- OF_SEPARATE - the normal way, where the devicetree is built and
> appended to U-Boot
>- OF_EMB
On Wed, 8 Sep 2021 01:25:04 +0200
Adam Lackorzynski wrote:
Hi Adam,
> On Mon Sep 06, 2021 at 16:34:03 +0100, Andre Przywara wrote:
> > On Sat, 4 Sep 2021 21:26:45 +0200
> > Adam Lackorzynski wrote:
> >
> > Hi Adam,
> >
> > > while trying to launch
On Sat, 4 Sep 2021 21:26:45 +0200
Adam Lackorzynski wrote:
Hi Adam,
> while trying to launch an EFI-enabled arm32 Linux binary (zImage) I
> noticed I get an undefined instruction exception on the first
> instruction. Now this is a bit special because Linux uses a nop
> instruction there that als
ine ID_AA64DFR0_PERFMON_SHIFT 8
> @@ -145,6 +154,33 @@ static inline void precise_instrs_loop(int loop,
> uint32_t pmcr)
> }
>
> #define PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
> +#define PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
> +#define PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12,
rs) {
> + report_skip("No event counter, skip ...");
> + return;
> + }
> +
> + /* PMUv3 requires an implementation includes some common events */
> + required_events = is_event_supported(0x0, true) /* SW_INCR */ &&
> +
g? Or just forgot to add my previous R-b?
Anyway,
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arm/pmu.c | 24 +++-
> arm/unittests.cfg | 7 ---
> 2 files changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/arm/pmu.c b/arm/pmu.c
&
d already in v1:
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arm/pmu.c | 30 +-
> 1 file changed, 25 insertions(+), 5 deletions(-)
>
> diff --git a/arm/pmu.c b/arm/pmu.c
> index e5e012d..d24857e 100644
> --- a/arm/pmu.c
> +++ b/arm/pm
On Mon, 16 Dec 2019 21:47:52 +0100
Eric Auger wrote:
Hi Eric,
thanks a lot for your work on these elaborate tests! I have some PMU test
extensions as well, but they are nowhere as sophisticated as yours!
Just ran this on my ThunderX2 desktop (4.15.0-65-generic #74-Ubuntu kernel,
QEMU emulator
On Mon, 16 Dec 2019 21:47:51 +0100
Eric Auger wrote:
Hi Eric,
> If event counters are implemented check the common events
> required by the PMUv3 are implemented.
>
> Some are unconditionally required (SW_INCR, CPU_CYCLES,
> either INST_RETIRED or INST_SPEC). Some others only are
> required if
On Mon, 16 Dec 2019 21:47:50 +0100
Eric Auger wrote:
> This struct aims at storing information potentially used by
> all tests such as the pmu version, the read-only part of the
> PMCR, the number of implemented event counters, ...
>
> Signed-off-by: Eric Auger
Reviewed-by:
On Mon, 16 Dec 2019 21:47:49 +0100
Eric Auger wrote:
> As we intend to introduce more PMU tests, let's add
> a sub-test parameter that will allow to categorize
> them. Existing tests are in the cycle-counter category.
>
> Signed-off-by: Eric Auger
Reviewed-by: Andre Przy
for me.
> Signed-off-by: Stewart Hildebrand
Tested-by: Andre Przywara
Cheers,
Andre.
On Tue, 16 Oct 2018 01:19:35 +
Stewart Hildebrand wrote:
Hi,
Stewart, thanks a lot for picking this up!
> On Monday, October 15, 2018 6:05 PM, Philippe Mathieu-Daudé wrote:
> > Hi Stewart,
> >
> > On 15/10/2018 23:26, Stewart Hildebrand wrote:
> > > +/* For the virt board, we
Some tests for the IPRIORITY registers. The significant number of bits
is IMPLEMENTATION DEFINED, but should be the same for every IRQ.
Also these registers must be byte-accessible.
Check that accesses beyond the implemented IRQ limit are actually
read-as-zero/write-ignore.
Signed-off-by: Andre
Some tests for the ITARGETS registers.
Bits corresponding to non-existent CPUs must be RAZ/WI.
These registers must be byte-accessible, also check that accesses beyond
the implemented IRQ limit are actually read-as-zero/write-ignore.
Signed-off-by: Andre Przywara
---
arm/gic.c | 43
tion is in (inline) assembly, the
compiler does not recognize its fatal nature, so help it with the
__builtin_unreachable() hint.
Flag the prototypes of our fatal functions accordingly.
Signed-off-by: Andre Przywara
---
lib/arm/io.c | 1 +
lib/libcflat.h | 7 ---
lib/powerpc/io.c | 1 +
li
isters
of GICv2. GICv3 is not covered yet.
This actually revealed genuine bugs in the KVM emulation in the past. KVM
passes these tests now, but QEMU fails some UP and 3-way-SMP tests.
Cheers,
Andre.
Andre Przywara (4):
mark exit() and abort() as non-returning functions
arm/arm64: GIC: basic G
This adds an MMIO subtest to the GIC test.
It accesses some generic GICv2 registers and does some sanity tests,
like checking for some of them being read-only.
Signed-off-by: Andre Przywara
---
arm/gic.c | 91 +++
arm/unittests.cfg
does not, starting with 4.15-rc, I am on it).
Cheers,
Andre.
Andre Przywara (2):
arm64: timer: add TVAL accessors
arm64: timer: Add TVAL timeout test and test IRQ trigger
arm/timer.c | 36
1 file changed, 36 insertions(+)
--
2.14.4
to read and write them
easily later.
Signed-off-by: Andre Przywara
---
arm/timer.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arm/timer.c b/arm/timer.c
index 5f3135f..1c9ef44 100644
--- a/arm/timer.c
+++ b/arm/timer.c
@@ -40,6 +40,16 @@ static void
coming back would be covered.
Signed-off-by: Andre Przywara
---
arm/timer.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arm/timer.c b/arm/timer.c
index 1c9ef44..275d049 100644
--- a/arm/timer.c
+++ b/arm/timer.c
@@ -211,6 +211,7 @@ static void test_timer(struct timer_info *info
ter_id, 1) |
> + tlist);
> +
> + gicv3_write_sgi1r(sgi1r);
> + }
> +
> + /* Force the above writes to ICC_SGI1R_EL1 to be executed */
> + isb();
> +}
Wow, this is really heavy stuff, especially for a Friday after
Cycles might be a bit
misleading, especially since this prototype is the only documentation on
this. You might just want to fix this when applying the patches.
That notwithstanding:
Reviewed-by: Andre Przywara
Cheers,
Andre.
> +extern void udelay(unsigned long usecs);
> +extern void mdelay(
Hi,
On 06/12/16 09:48, Andrew Jones wrote:
> On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote:
>> This series proposes a framework to test the virtual ITS.
>> This is based on Drew's v7 series [1]. The last patch tests
>> several ITS commands (collection/device mapping, interrupt
>> tran
Hi,
On 06/12/16 09:29, Andrew Jones wrote:
> On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote:
>> Add a new cpu_count field in gicv3_data indicating the
>> number of redistributors. This will be useful for enumeration
>> of their resources such as LPI pending tables.
>
> I'm fine with t
Hi,
On 01/12/16 05:16, Wei Huang wrote:
> From: Christopher Covington
>
> Calculate the numbers of cycles per instruction (CPI) implied by ARM
> PMU cycle counter values. The code includes a strict checking facility
> intended for the -icount option in TCG mode in the configuration file.
>
> Si
Hi,
On 01/12/16 12:02, Peter Maydell wrote:
> On 1 December 2016 at 11:28, Andre Przywara wrote:
>> I don't think so. At least here as a _variable_ type uint32_t is
>> probably the right one, as the ARMv8 ARM explicitly says that PMCR is a
>> 32-bit register, for both
Hi,
On 01/12/16 09:03, Andrew Jones wrote:
> On Wed, Nov 30, 2016 at 11:16:40PM -0600, Wei Huang wrote:
>> From: Christopher Covington
>>
>> Beginning with a simple sanity check of the control register, add
>> a unit test for the ARM Performance Monitors Unit (PMU). PMU register
>> was read using
Hi,
On 01/12/16 05:16, Wei Huang wrote:
> From: Christopher Covington
>
> Ensure that reads of the PMCCNTR_EL0 are monotonically increasing,
> even for the smallest delta of two subsequent reads.
>
> Signed-off-by: Christopher Covington
> Signed-off-by: Wei Huang
> Reviewed-by: Andrew Jones
naming,
>> get_##name() and set_##name(), which can be used by C code directly.
>>
>> Signed-off-by: Andre Przywara
>> Signed-off-by: Wei Huang
>> ---
>> lib/arm/asm/processor.h | 37 -
>> lib/arm64/asm/processor.h
Hi Drew,
actually unrelated to this actual patch, but since you mentioned it:
> As we work out how best to handle tcg-only tests in order to get Alex
> Bennee's MTTCG tests merged, we'll probably revisit this file,
So when I was experimenting with kvmtool, I realized that some tests
would need t
Hi,
On 25/11/16 14:26, Andrew Jones wrote:
> On Fri, Nov 25, 2016 at 12:32:24PM +0000, Andre Przywara wrote:
>> Hi Drew,
>>
>>
>>
>> On 23/11/16 17:15, Andrew Jones wrote:
>>>>> +
>>>>> +#if defined(__arm__)
>>>>
Hi Drew,
On 23/11/16 17:15, Andrew Jones wrote:
>>> +
>>> +#if defined(__arm__)
>>
>> I guess you should use the arch specific header files we have in place
>> for that (lib/arm{.64}/asm/processor.h). Also there are sysreg read
>> wrappers (at least for arm64) in there already, can't we base
Hi,
On 22/11/16 18:29, Wei Huang wrote:
> From: Christopher Covington
>
> Beginning with a simple sanity check of the control register, add
> a unit test for the ARM Performance Monitors Unit (PMU).
Mmh, the output of this is a bit confusing. How about to join some
information? I changed it to
Hi Eric,
thanks for having such a close look (as always!).
On 23/11/16 13:51, Auger Eric wrote:
> Hi Andre,
>
> On 23/11/2016 14:24, Auger Eric wrote:
>> Hi,
>>
>> On 18/11/2016 15:20, Andrew Jones wrote:
>>> On Thu, Nov 17, 2016 at 05:57:51PM +, Andre
Hi,
On 22/11/16 18:45, Andrew Jones wrote:
>
> Andre, Alex, Eric, anybody,
>
> Any more comments on this? If not, I'll send a pull request
> to Radim and Paolo to finally get this merged.
I didn't manage to look in detail at the IPI test, but I am OK with the
rest of the GIC framework.
So I'd s
expected.
Signed-off-by: Andre Przywara
---
Hi,
this maybe a personal itch to scratch here, since I set these two
variables in my environment via a (sourced) script here and never have
to care about the particular cross-compiler prefix, for instance.
It looks rather generic, though, so I was
Hi Drew,
On 18/11/16 13:06, Andrew Jones wrote:
> Hi Andre,
>
> I'm so pleased to see this series. Thank you!
>
> On Thu, Nov 17, 2016 at 05:57:49PM +, Andre Przywara wrote:
>> This adds an MMIO subtest to the GIC test.
>> It accesses some generic GICv2 regi
ly be
extended on that base.
Applies on top of master + Drew's v6 series.
Cheers,
Andre.
Andre Przywara (4):
arm/arm64: GIC: basic GICv2 MMIO tests
arm/arm64: GICv2: add GICD_IPRIORITYR testing
arm/arm64: GICv2: add GICD_ITARGETSR testing
arm/arm64: GICv3: add TYPER test
arm/gic.c
Some tests for the ITARGETS registers.
Bits corresponding to non-existent CPUs must be RAZ/WI.
These registers must be byte-accessible, also check that accesses beyond
the implemented IRQ limit are actually read-as-zero/write-ignore.
Signed-off-by: Andre Przywara
---
arm/gic.c | 54
Some tests for the IPRIORITY registers. The significant number of bits
is IMPLEMENTATION DEFINED, but should be the same for every IRQ.
Also these registers must be byte-accessible.
Check that accesses beyond the implemented IRQ limit are actually
read-as-zero/write-ignore.
Signed-off-by: Andre
Add a simple test for the GICv3 TYPER test, which does only one basic
check to ensure we have actually enough interrupt IDs if we support
LPIs.
Allow a GICv3 guest to do the common MMIO checks as well, where the
register semantics are shared with a GICv2.
Signed-off-by: Andre Przywara
---
arm
This adds an MMIO subtest to the GIC test.
It accesses some generic GICv2 registers and does some sanity tests,
like checking for some of them being read-only.
Signed-off-by: Andre Przywara
---
arm/gic.c | 99 +++
arm/unittests.cfg
Hi,
On 10/11/16 17:21, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v5: use modern register names [Andre]
> v4:
> - only take defines from kernel we need now [Andre]
> - simplify enable by not caring if we reinit the distributor [drew]
> v2:
> - configure irqs as NS GRP1
> ---
looks much better now.
Reviewed-by: Andre Przywara
> v4:
> - only take defines from kernel we need now [Andre]
> - moved defines to asm/gic.h so they'll be shared with v3 [drew]
> - simplify enable by not caring if we reinit the distributor [drew]
> - init all GICD_INT
-machine gic-version=3 to
> extra_params.
>
> Reviewed-by: Alex Bennée
> Signed-off-by: Andrew Jones
>
> ---
> v5: left cpus a u32 for now. Changing to u64 requires a change to
> devicetree. Will do it later. [Andre]
Given that we address this in the future:
Reviewed-by: Andre Przywara
Hi,
On 11/11/16 14:53, Alex Bennée wrote:
>
> Andrew Jones writes:
>
>> On Fri, Nov 11, 2016 at 10:02:59AM +, Alex Bennée wrote:
>>>
>>> Andrew Jones writes:
>>>
On Thu, Nov 10, 2016 at 07:53:58PM +, Alex Bennée wrote:
[...]
>> +struct gic gicv2 = {
>> +.ipi =
Hi,
On 11/11/16 14:52, Alex Bennée wrote:
>
> Andrew Jones writes:
>
>> Add some gicv2 support. This just adds init and enable
>> functions, allowing unit tests to start messing with it.
>>
>> Signed-off-by: Andrew Jones
>>
>> ---
>> v5: share/use only the modern register names [Andre]
>> v4:
Hi,
more a comment loosely related to this patch ...
> diff --git a/arm/unittests.cfg b/arm/unittests.cfg
> index 3f6fa45c587e..68bf5cd6008f 100644
> --- a/arm/unittests.cfg
> +++ b/arm/unittests.cfg
> @@ -54,3 +54,10 @@ file = selftest.flat
> smp = $MAX_SMP
> extra_params = -append 'smp'
> gr
Hi,
On 10/11/16 19:53, Alex Bennée wrote:
> So I was re-basing my kvm-unit-tests against your GIC rework and found
> myself copy and pasting a bunch of this into my tests that fire IRQs.
So I take it you are working on (or already have) code to test SPIs,
probably via GICD_ISPENDR?
Just ask
Hi,
so is this actually v4 just resent?
Or is this is a new version with s/5/4/?
I can't spot any of the key changes quickly ...
Cheers,
Andre.
On 10/11/16 16:07, Andrew Jones wrote:
> v4:
> - Eric's r-b's
> - Andre's suggestion to only take defines we need
> - several other changes listed in
Hi,
On 08/11/16 20:21, Andrew Jones wrote:
> From: Peter Xu
>
> These macros will be useful to do page alignment checks.
Reviewed-by: Andre Przywara
Cheers,
Andre.
> Signed-off-by: Peter Xu
> [drew: also added SZ_64K]
> Signed-off-by: Andrew Jones
> ---
> lib/li
Hi,
On 09/11/16 13:08, Andrew Jones wrote:
> On Wed, Nov 09, 2016 at 12:35:48PM +0000, Andre Przywara wrote:
> [...]
>>> diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
>>> new file mode 100644
>>> index ..03321f8c860f
>>> --
Hi,
On 08/11/16 20:21, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v4:
> - only take defines from kernel we need now [Andre]
> - simplify enable by not caring if we reinit the distributor [drew]
> v2:
> - configure irqs as NS GRP1
> ---
> lib/arm/asm/arch_gicv3.h | 42 +
Hi,
On 09/11/16 11:57, Andrew Jones wrote:
> On Wed, Nov 09, 2016 at 11:12:03AM +0000, Andre Przywara wrote:
> [...]
>>> diff --git a/lib/arm/setup.c b/lib/arm/setup.c
>>> index 7e7b39f11dde..b6e2d5815e72 100644
>>> --- a/lib/arm/setup.c
>>> +++ b/lib/
Hi,
On 08/11/16 20:21, Andrew Jones wrote:
> Add some gicv2 support. This just adds init and enable
> functions, allowing unit tests to start messing with it.
>
> Signed-off-by: Andrew Jones
>
> ---
> v4:
> - only take defines from kernel we need now [Andre]
> - moved defines to asm/gic.h so
Hi,
On 08/11/16 20:21, Andrew Jones wrote:
> By adding support for launching with gicv3 we can break the 8 vcpu
> limit. This patch adds support to smp code and also selects the
> vgic model corresponding to the host. The vgic model may also be
> manually selected by adding e.g. -machine gic-versi
x27;s v3 GIC series (as in his github branch).
Signed-off-by: Andre Przywara
---
lib/arm/asm/arch_gicv3.h | 62 -
lib/arm/asm/gic-v2.h | 22 -
lib/arm/asm/gic-v3.h | 227 -
lib/arm64/asm/arch_gicv3.h | 43 -
4
Hi Drew,
On 15/07/16 14:00, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v2: configure irqs as NS GRP1
> ---
> lib/arm/asm/arch_gicv3.h | 184 ++
> lib/arm/asm/gic-v3.h | 321
> +
> lib/arm/asm/gic.h
On 11/28/2013 08:41 PM, Peter Maydell wrote:
(CCing Rob)
On 28 November 2013 03:31, Peter Crosthwaite
wrote:
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
"MPCore" is one of tho
Peter, the config option is called: CONFIG_STRICT_DEVMEM
And /dev/mem behaves differently between doing read() and doing mmap().
As Peter already hinted, the memory layout is different on native Midway (which
has DRAM starting at 0) and mach-virt/vexpress (which start at 128MB / 2GB
respectively
e Highbank specific part,
since Midway does not have (and need) it.
Signed-off-by: Andre Przywara
---
hw/arm/highbank.c | 32 +++-
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 2c32a2b..3c99a81 100644
--
To allow the modelling of machines similar to Calxeda Highbank,
introduce a parameter to the init function and call it from a
wrapper. This allows to tweak the definition for individual machines
later on.
Signed-off-by: Andre Przywara
---
hw/arm/highbank.c | 29 +++--
1
This is based on work by Rob Herring .
Signed-off-by: Andre Przywara
Andre Przywara (2):
ARM/highbank: prepare for adding similar machines
ARM/highbank: add support for Calxeda ECX-2000 / Midway
hw/arm/highbank.c | 61 +--
1 file chan
ion. The use of:
"-M highbank -cpu cortex-a15" simply gives the new chip without the
need for a new model.
Signed-off-by: Rob Herring
Signed-off-by: Andre Przywara
---
hw/arm/highbank.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/hw/arm/highba
On 05/07/2013 03:24 PM, Peter Maydell wrote:
On 7 May 2013 13:52, Andre Przywara wrote:
On 05/07/2013 02:44 PM, Peter Maydell wrote:
I'm not entirely sure I understand why we need change.
Have upstream really introduced a breaking change for
everybody who uses libfdt, or are we usi
On 05/07/2013 02:44 PM, Peter Maydell wrote:
On 7 May 2013 13:36, Andre Przywara wrote:
Upstream dtc.git introduced a change in libfdt_env.h, which breaks
compilation with QEMU's version of it:
CC arm-softmmu/device_tree.o
In file included from /usr/include/libfdt.h
is change
also works with older installed versions of dtc.
The upstream version got a "GPL or BSD" dual license header meanwhile.
I retained the original GPL license header from QEMU, only added
the original copyrights.
Signed-off-by: Andre Przywara
---
include/libfdt_env.h | 25 +++
On 10/18/12 18:33, Eduardo Habkost wrote:
On Wed, Oct 17, 2012 at 11:17:26PM +0200, Andre Przywara wrote:
Update QEMU's knowledge of CPUID bit names. This allows to
enable/disable those new features on QEMU's command line when
using KVM and prepares future feature enableme
least the header file in RHEL 5.0 (v1.4.1) seems to have
it already. If someone finds a broken distribution, tell me and I
insert some compat code.
Signed-off-by: Andre Przywara
---
ui/vnc-tls.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/ui/vnc-tls.c b/ui/vnc-t
vPCID, RTM, RDSeed and ADX.
Sources where the AMD BKDG for Family 15h/Model 10h and the Linux kernel
for the leaf 7 bits.
Signed-off-by: Andre Przywara
---
target-i386/cpu.c | 16
target-i386/cpu.h | 21 +
2 files changed, 29 insertions(+), 8 deletions(-)
di
tched
earlier), I am all ears.
Regards,
Andre.
My question is: should we support this option format in qemu, or should
we change libvirt to use another format (that has yet to be implemented,
because currently there's no way to specify a non-contiguous set of CPUs
for a NUMA node).
Any sugg
d on either case, but first we need to figure out what are the
expectations/requirements, to know _which_ changes will be needed.
On Tue, Apr 24, 2012 at 02:19:25PM -0300, Eduardo Habkost wrote:
(CCing Andre Przywara, in case he can help to clarify what's the
expected meaning of "-cpu ho
int i;
-if (nb_numa_nodes> smp_cpus) {
-nb_numa_nodes = smp_cpus;
+if (nb_numa_nodes> MAX_NODES) {
+nb_numa_nodes = MAX_NODES;
}
/* If no memory size if given for any node, assume the default case
Acked-by: Andre Przywara
Regar
t rise due to the new model.
I can easily send patches and will try to contribute to testing, if that
plan sounds OK.
--
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
KVM handles is limited to 40.
My desktop machine (AthlonII) already has 35 and future CPUs will
expand this well beyond the limit. Extend the limit to 80 to make
room for future processors.
Signed-off-by: Andre Przywara
---
arch/x86/include/asm/kvm_host.h |2 +-
1 files changed, 1 insertions
Avi Kivity wrote:
On 12/01/2010 01:17 PM, Andre Przywara wrote:
Currently the number of CPUID leaves KVM handles is limited to 40.
My desktop machine (AthlonII) already has 35 and future CPUs will
expand this well beyond the limit. Extend the limit to 80 to make
room for future processors
Currently the number of CPUID leaves KVM handles is limited to 40.
My desktop machine (AthlonII) already has 35 and future CPUs will
expand this well beyond the limit. Extend the limit to 80 to make
room for future processors.
Signed-off-by: Andre Przywara
---
arch/x86/include/asm/kvm_host.h
VCPU1
|
+--/ kvm_guest_02
...
What do you think about it? It is worth implementing this?
Regards,
Andre.
--
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
Tel: +49 351 448-3567-12
bitmap code, maybe you could leverage this (if not
already done).
Regards,
Andre.
--
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
Tel: +49 351 448-3567-12
#ifndef __BITMAP_H__
#define __BITMAP_H__
#ifndef HOST_LONG_BITS
#define HOST_LONG_BITS (sizeof(long) * 8
Can you give more hints on how to reproduce this?
$ qemu-system-x86_64 -cdrom minix_R3.1.6-r6084.iso
works fine for me (I get to the prompt), both with --enable-kvm and without and
also with qemu-kvm. My qemu version is 0.12.4.
Do I need to install it and run it from the harddisk?
--
MINIX 3 won
Anthony Liguori wrote:
On 05/25/2010 08:21 AM, Andre Przywara wrote:
What's the benefit of exposing this information to the guest?
That is mostly to propagate the cache size and organization parameters
to the guest:
+/* safe CPUID leafs to propagate to guest if -cpu host is spec
Anthony Liguori wrote:
On 05/21/2010 02:50 AM, Andre Przywara wrote:
-cpu host currently only propagates the CPU's family/model/stepping,
the brand name and the feature bits.
Add a whitelist of safe CPUID leafs to let the guest see the actual
CPU's cache details and other things.
Sig
-cpu host currently only propagates the CPU's family/model/stepping,
the brand name and the feature bits.
Add a whitelist of safe CPUID leafs to let the guest see the actual
CPU's cache details and other things.
Signed-off-by: Andre Przywara
---
target-i386/cpu.h |6 +-
t
Create a kvm32 CPU model that describes a least common denominator
for KVM capable guest CPUs. Useful for migration purposes.
Signed-off-by: Andre Przywara
---
target-i386/cpuid.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/target-i386/cpuid.c b/target
is to propagate the host's vendor
- when explicitly requested via -cpu ,vendor=xxx obey this
and use the specified vendor
Signed-off-by: Andre Przywara
---
target-i386/cpuid.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Hi,
this hasn't been picked up the last time
Michael Tokarev wrote:
20.05.2010 02:30, Anthony Liguori wrote:
On 05/19/2010 05:29 PM, Andre Przywara wrote:
Michael Tokarev wrote:
...
Also, thanks to Andre Przywara, whole winNT thing works but it requires
-cpu qemu64,level=1 (or level=2 or =3), -- _not_ with default CPU. This
[]
It&#
Is that still a problem? What was the exact error?
I quickly tried the 3.1.2a on qemu 0.12.4 (with and without KVM) and I could
easily login.
** Changed in: qemu
Status: New => Incomplete
--
MINIX 3 won't boot in qemu 0.9.1
https://bugs.launchpad.net/bugs/267542
You received this bug no
Michael Tokarev wrote:
...
Also, thanks to Andre Przywara, whole winNT thing works but it requires
-cpu qemu64,level=1 (or level=2 or =3), -- _not_ with default CPU. This
is also testing, but it's not obvious what to do witht the result...
Can't we use the file based CPU model
Aurelien Jarno wrote:
On Sun, Apr 11, 2010 at 09:49:40PM +0200, Andre Przywara wrote:
Avi Kivity wrote:
On 04/11/2010 10:21 PM, Andre Przywara wrote:
the meaning of vendor_override is actually the opposite of how it
is currently used :-(
Fix it to allow KVM to export the non-native CPUID
Create a kvm32 CPU model that describes a least common denominator
for KVM capable guest CPUs. Useful for migration purposes.
Signed-off-by: Andre Przywara
---
target-i386/cpuid.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/target-i386/cpuid.c b/target
the meaning of vendor_override is actually the opposite of how it
is currently used :-(
Fix it to allow KVM to export the non-native CPUID vendor if
explicitly requested by the user.
Signed-off-by: Andre Przywara
---
target-i386/cpuid.c |2 +-
1 files changed, 1 insertions(+), 1 deletions
Avi Kivity wrote:
On 04/11/2010 10:21 PM, Andre Przywara wrote:
the meaning of vendor_override is actually the opposite of how it
is currently used :-(
Fix it to allow KVM to export the non-native CPUID vendor if
explicitly requested by the user.
Signed-off-by: Andre Przywara
---
target-i386
-cpu host currently only propagates the CPU's family/model/stepping,
the brand name and the feature bits.
Add a whitelist of safe CPUID leafs to let the guest see the actual
CPU's cache details and other things. A list of affected leafs is
contained in the comments.
Signed-off-by: Andr
the meaning of vendor_override is actually the opposite of how it
is currently used :-(
Fix it to allow KVM to export the non-native CPUID vendor if
explicitly requested by the user.
Signed-off-by: Andre Przywara
---
target-i386/helper.c |2 +-
1 files changed, 1 insertions(+), 1 deletions
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