Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

> > >> > It seems to me that the C extension can be enabled at any point, since >> if C is >> > off, you know that the next insn is aligned modulo 4. >> > >> > > > Ok, This is mostly right. When C extension is enabled 32-bit base > instructions can be aligned on 2 bytes boundaries instead of 4 byt

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

> > It seems to me that the C extension can be enabled at any point, since > if C is > > off, you know that the next insn is aligned modulo 4. > > > Ok, This is mostly right. When C extension is enabled 32-bit base instructions can be aligned on 2 bytes boundaries instead of 4 bytes only. So mult

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

Thank you so much, Eric. Sorry about this unclear description. I forgot to fix user name in git configuration before submitting the patch. Sorry about any inconvenience. Thanks, Ahmed On Sat, 23 Feb 2019 at 23:46, Eric Blake wrote: > On 2/22/19 10:25 AM, amagdy.af...@gmail.com wrote: > > From:

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

Thank you for your review and feedback, Richard. As Eric mentioned, this is the first time contribution. I have been exploring Qemu for some time and try to understand main flow, internals, ..etc. > You cannot manipulate env like this during translation. > Neither the write to env->pc_next nor