Re: [PATCH v2] target/riscv: Support Supm and Sspm as part of Zjpm v1.0

>I removed the lines above, as we don't want to include the changelog or rebase notes in the commit message Sure, sorry for that Thank you Alistair and Daniel! вт, 14 янв. 2025 г. в 04:43, Alistair Francis : > On Tue, Jan 14, 2025 at 5:45 AM wrote: > > > > From: Alexey

Re: [PATCH v14 0/7] Pointer Masking update for Zjpm v1.0

Hi Alistair, I rebased these patches against riscv-to-apply.next and resubmitted them. Thanks пн, 6 янв. 2025 г. в 06:36, Alistair Francis : > On Tue, Dec 17, 2024 at 6:57 PM wrote: > > > > From: Alexey Baturo > > > > Hi, > > > > Rebased and addr

Re: [PATCH v13 6/7] target/riscv: Apply pointer masking for virtualized memory accesses

ir Francis : > On Mon, Dec 16, 2024 at 10:19 PM wrote: > > > > From: Alexey Baturo > > > > Signed-off-by: Alexey Baturo > > --- > > target/riscv/cpu.h | 1 + > > target/riscv/cpu_helper.c| 18 +++ > > target/riscv/internal

Re: [PATCH v12 7/7] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

ro.com>: > > > On 12/5/24 8:23 AM, baturo.ale...@gmail.com wrote: > > From: Alexey Baturo > > > > Signed-off-by: Alexey Baturo > > > > Reviewed-by: Alistair Francis > > --- > > target/riscv/cpu.c | 6 ++ > > 1 file changed, 6 inse

Re: [PATCH v12 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

Thanks Daniel. Let's wait for about a week or so for other suggestions to the patches and then I'll send a new updated series. сб, 7 дек. 2024 г. в 00:08, Daniel Henrique Barboza < dbarb...@ventanamicro.com>: > > > On 12/5/24 8:23 AM, baturo.ale...@gmail.com wrote

Re: [PATCH v11 6/7] target/riscv: Apply pointer masking for virtualized memory accesses

t; > From: Alexey Baturo > > > > Signed-off-by: Alexey Baturo > > --- > > target/riscv/cpu.h | 2 ++ > > target/riscv/cpu_helper.c | 19 +++ > > target/riscv/insn_trans/trans_rvh.c.inc | 11 ++

Re: [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code.

07:01, Alistair Francis : > On Thu, Nov 21, 2024 at 4:13 PM wrote: > > > > From: Alexey Baturo > > > > Zjpm extension is finally ratified. And it's much simplier compared to > the experimental one. > > The newer version doesn't allow to specify custom

Re: [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0

with a lot of patches already reviewed. > > If you could re-send this series as v11, keeping reviewed-by tags from > code that you > didn't change from one version to the other, the review will go faster. > > > Thanks, > > Daniel > > On 11/21/24 3:12 AM, baturo.ale.

Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

o post a new version of this series? Aside from a few > comments > it seems like this was almost there. > > We might not be able to get it merged in time for this current release > (code freeze > is Nov 5th) but we can get it in Alistair's tree for the next release. > > &

Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

ay 13, 2024 at 9:14 PM Alistair Francis > wrote: > > > > On Mon, May 13, 2024 at 9:05 PM Alexey Baturo > wrote: > > > > > > Hi, > > > > > > > Hi, any change from v0.8 to v1.0? > > > Not in the patches that were sent. I'd still

Re: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

:44 AM liwei wrote: > > > > > > On 2024/5/11 18:10, Alexey Baturo wrote: > > > From: Alexey Baturo > > > > > > Hi, > > > > > > It looks like Pointer Masking spec has reached v1.0 and been frozen, > > > rebasing on riscv-to-app

[PATCH v9 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v9 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v9 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v9 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e350e9bd8..b3b3a6275f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v9 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 5 target/riscv/cpu_helper.c | 58 +++ 2 files changed, 63 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v9 0/6] Pointer Masking update for Zjpm v1.0

From: Alexey Baturo Hi, It looks like Pointer Masking spec has reached v1.0 and been frozen, rebasing on riscv-to-apply.next branch and resubmitting patches. Thanks. [v8]: Rebasing patches on current qemu branch and resubmitting them. [v7]: I'm terribly sorry, but previous rebase

[PATCH v9 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v8 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73c69f3d0a..9e3bf6c5c5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v8 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v8 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v8 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v8 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v8 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, Rebasing patches on current qemu branch and resubmitting them. Thanks. [v7]: I'm terribly sorry, but previous rebase went wrong and somehow I missed it. This time I double-checked rebased version. This patch series is properly rebased on https://github.com/alist

[PATCH v8 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v7 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ded84f2e09..23d1692b59 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v7 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v7 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, I'm terribly sorry, but previous rebase went wrong and somehow I missed it. This time I double-checked rebased version. This patch series is properly rebased on https://github.com/alistair23/qemu/tree/riscv-to-apply.next Thanks [v6]: This patch series is rebas

[PATCH v7 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v7 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v7 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v7 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v6 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v6 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v6 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, This patch series is rebased on https://github.com/alistair23/qemu/tree/riscv-to-apply.next Thanks [v5]: This patch series targets Zjpm v0.8 extension. The spec itself could be found here: https://github.com/riscv/riscv-j-extension/blob

[PATCH v6 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v6 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v6 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

[PATCH v6 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ded84f2e09..23d1692b59 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c

[PATCH v5 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c9bed5c9fc..1c8979c1c8 100644 --- a

[PATCH v5 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target

[PATCH v5 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d8de1f1890..bf431ab728 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ const

[PATCH v5 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b

[PATCH v5 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo Acked-by: Alista

[PATCH v5 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, This patch series targets Zjpm v0.8 extension. The spec itself could be found here: https://github.com/riscv/riscv-j-extension/blob/8088461d8d66a7676872b61c908cbeb7cf5c5d1d/zjpm-spec.pdf This patch series is updated after the suggested comments: - add "x-&qu

[PATCH v5 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c

Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

Hi, Having the feature to run binaries with pointer masking on qemu-user is really nice, but I see this patch series as an initial support. Obviously there'll be more patches and fixes for pointer masking as soon as arch tests are ready. I suggest supporting qemu-user in the next patches, but make

[PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 10 +++--- target/riscv/pmp.c | 13 ++--- target

[PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c9bed5c9fc..1c8979c1c8 100644 --- a

[PATCH v4 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson --- target/riscv/translate.c | 22 -- target/riscv/vector_helper.c | 13 + 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target/riscv/translate.c b/target

[PATCH v4 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, Patch series updated after the suggested comments: - removed J-letter extension as it's unused - renamed and fixed function to detect if address should be sign-extended - zeroed unused context variables and moved computation logic to another patch - bumped po

[PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d8de1f1890..44ebd80aba 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ const

[PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo --- target/r

Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

I think you're right, thanks. I'll add a check for M-mode as well and I guess I'll have to rename the function. Any ideas on the proper and self-describing name? Thanks пт, 5 янв. 2024 г. в 03:46, Deepak Gupta : > On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo > w

Re: [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking

> +addr = addr << pmlen; > +if (signext) { > +addr = (target_long)addr >> pmlen; > +} else { > +addr = addr >> pmlen; Could you please elaborate a bit more on your concern here? I believe this code works as intended: https://godbolt.org/z/b9c7na13a Thanks пт, 5 янв. 20

Re: [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code.

Sure, I would do it in the next updated series. пт, 5 янв. 2024 г. в 08:04, Alistair Francis : > On Thu, Jan 4, 2024 at 6:33 AM Alexey Baturo > wrote: > > > > From: Alexey Baturo > > > > Zjpm v0.8 is almost frozen and it's much simplier compared to the &g

Re: [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

xey Baturo > wrote: > > > > From: Alexey Baturo > > > > Signed-off-by: Alexey Baturo > > --- > > target/riscv/cpu.c | 8 > > 1 file changed, 8 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >

[PATCH v3 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 6 -- target/riscv/pmp.c | 13 ++--- target

[PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo --- target/r

[PATCH v3 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 11 +++ 3 files changed, 17 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c607a94bba..4df160494f 100644

[PATCH v3 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi, There patches are updated after Richard's comments: - moved new tb flags to the end - used tcg_gen_(s)extract to get the final address - properly handle CONFIG_USER_ONLY Thanks [v2]: As per Richard's suggestion I made pmm field part of tb_flags. It allowed

[PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 54 +++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bd379ee653..c607a94bba 100644 --- a

[PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 12 target/riscv/vector_helper.c | 12 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8ac2819fa5..457de381c7

[PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e6571ce99..13389ddc55 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ const

Re: [PATCH v2 4/6] target/riscv: Add pointer masking tb flags

good idea and I agree we could do it as part of future clean up. Thanks, Richard пт, 29 дек. 2023 г. в 02:33, Richard Henderson : > On 12/24/23 15:48, Alexey Baturo wrote: > > From: Alexey Baturo > > > > Signed-off-by: Alexey Baturo > > --- > > target/riscv/cpu

[PATCH v2 4/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 15 +-- target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 + 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v2 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 6 -- target/riscv/pmp.c | 13 ++--- target

[PATCH v2 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 4 +++ target/riscv/cpu_helper.c | 54 +++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bd379ee653..c607a94bba 100644 --- a

[PATCH v2 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e6571ce99..13389ddc55 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ const

[PATCH v2 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo --- target/r

[PATCH v2 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 23 +-- target/riscv/vector_helper.c | 10 ++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1eb501e0d3

[PATCH v2 0/6] Pointer Masking update for Zjpm v0.8

ly anymore. Compared to the original implementation with explicit base and mask CSRs, we now only have several fixed options for number of masked bits which are set using existing CSRs. The changes have been tested with handwritten assembly tests and LLVM HWASAN test suite. Thanks Alexey

Re: [PATCH 3/6] target/riscv: Add pointer masking tb flags

) based on those 2 extracted bits. Is it ok with you? Thanks пт, 22 дек. 2023 г. в 01:49, Richard Henderson : > On 12/21/23 21:40, Alexey Baturo wrote: > > From: Alexey Baturo > > > > Signed-off-by: Alexey Baturo > > --- > > target/riscv/cpu.h| 19 +

[PATCH 3/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 19 +-- target/riscv/cpu_helper.c | 4 target/riscv/translate.c | 10 ++ 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH 4/6] target/riscv: Add functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_helper.c | 49 +++ 2 files changed, 51 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2099168950..9a8e5bc022 100644 --- a

[PATCH 0/6] Pointer Masking update for Zjpm v0.8

From: Alexey Baturo Hi all, It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore. Compared to the original implementation with explicit base and mask CSRs, we now only have several fixed options for number of masked bits which are set using existing

[PATCH 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo --- target/r

[PATCH 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c| 9 + target/riscv/cpu_helper.c | 1 + target/riscv/csr.c| 4 target/riscv/machine.c| 1 + target/riscv/pmp.c| 1 + 5 files changed, 16 insertions(+) diff --git a/target/riscv

[PATCH 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 6 -- target/riscv/pmp.c | 13 ++--- target

[PATCH 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 21 +++-- target/riscv/vector_helper.c | 7 +++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4c0d526b58

Re: [RFC PATCH v2 1/6] target/riscv: Remove obsolete pointer masking extension code.

Hi Alistair, Thanks for the lightning fast reply! Could you please tell who should bump those numbers and to what values? Do you think I could submit this patch series for the review? Thanks пн, 18 дек. 2023 г. в 06:11, Alistair Francis : > On Sat, Dec 16, 2023 at 11:52 PM Alexey Bat

[RFC PATCH v2 4/6] target/riscv: Add functions to calculate current number of masked bits for pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_helper.c | 49 +++ 2 files changed, 51 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2099168950..9a8e5bc022 100644 --- a

[RFC PATCH v2 5/6] target/riscv: Update address modify functions to take into account pointer masking

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 21 +++-- target/riscv/vector_helper.c | 7 +++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4c0d526b58

[RFC PATCH v2 1/6] target/riscv: Remove obsolete pointer masking extension code.

From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo --- target/r

[RFC PATCH v2 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 8 target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++ target/riscv/machine.c | 6 -- target/riscv/pmp.c | 13 ++--- target

[RFC PATCH v2 0/6] Pointer Masking update to Zjpm v0.6.1

From: Alexey Baturo Hi all, It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore. Compared to the original implementation with explicit base and mask CSRs, we now only have several fixed options for number of masked bits which are set using existing

[RFC PATCH v2 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c| 9 + target/riscv/cpu_helper.c | 1 + target/riscv/csr.c| 4 target/riscv/machine.c| 1 + target/riscv/pmp.c| 1 + 5 files changed, 16 insertions(+) diff --git a/target/riscv

[RFC PATCH v2 3/6] target/riscv: Add pointer masking tb flags

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 19 +-- target/riscv/cpu_helper.c | 4 target/riscv/translate.c | 10 ++ 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[RFC v1 3/8] target/riscv: Add new bits in CSRs for Zjpm 0.6.1

Signed-off-by: Alexey Baturo --- target/riscv/cpu_bits.h | 6 ++ target/riscv/csr.c | 8 target/riscv/pmp.c | 5 + target/riscv/pmp.h | 12 +++- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv

[RFC v1 6/8] target/riscv: Add functions to calculate current N masked bits for pointer masking

Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 6 ++-- target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 17d0088cb4..c87c4f26a2 100644 --- a/target

[RFC v1 0/8] RISC-V Pointer Masking update to Zjpm v0.6.1

. Thanks Alexey Baturo (8): target/riscv: Remove obsolete pointer masking extension code target/riscv: Add new S{sn,mn,m}jpm extensions as part of Zjpm v0.6.1 target/riscv: Add new bits in CSRs for Zjpm 0.6.1 Add enum with maximum ignored bits depending on privilege level for Zjpm v0.6.1

[RFC v1 2/8] target/riscv: Add new S{sn, mn, m}jpm extensions as part of Zjpm v0.6.1

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 7 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/machine.c | 6 -- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f937820976..af8f16b94f 100644 --- a/target/riscv

[RFC v1 7/8] target/riscv: Update address modify functions to take into account pointer masking

Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 21 +++-- target/riscv/vector_helper.c | 7 +++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3434ba58b6..4aa0e2b9e1 100644 --- a

[RFC v1 5/8] target/riscv: Add pointer masking tb flags

Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 19 +-- target/riscv/cpu_helper.c | 4 target/riscv/translate.c | 10 ++ 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 25fe60476b

[RFC v1 1/8] target/riscv: Remove obsolete pointer masking extension code

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 12 -- target/riscv/cpu.h | 30 +--- target/riscv/cpu_bits.h | 82 - target/riscv/cpu_helper.c| 52 -- target/riscv/csr.c | 326 --- target/riscv/machine.c

[RFC v1 8/8] target/riscv: enable updates for pointer masking variables and thus enable pointer masking extension

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c| 1 + target/riscv/cpu_helper.c | 1 + target/riscv/csr.c| 4 target/riscv/machine.c| 1 + target/riscv/pmp.c| 1 + 5 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[RFC v1 4/8] Add enum with maximum ignored bits depending on privilege level for Zjpm v0.6.1

Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 62dabfa207..25fe60476b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,6 +88,16 @@ typedef enum

[PATCH 0/1] Fix pointer masking functionality for RISC-V

From: Alexey Baturo Hi, This patch fixes a typo which leads to broken pointer masking functionality for RISC-V. Thanks. Alexey Baturo (1): target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 1/1] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V

From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 63b04e8a94..86c19ea74e 100644 --- a/target/riscv/translate.c +++ b/target/riscv

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