On Thu, May 21, 2020 at 1:21 AM Nicolas Dufresne wrote:
>
> Le mercredi 20 mai 2020 à 12:19 +0900, Alexandre Courbot a écrit :
> > On Wed, May 20, 2020 at 2:29 AM Nicolas Dufresne
> > wrote:
> > > Le mardi 19 mai 2020 à 17:37 +0900, Keiichi Watanabe a
On Wed, May 20, 2020 at 2:29 AM Nicolas Dufresne wrote:
>
> Le mardi 19 mai 2020 à 17:37 +0900, Keiichi Watanabe a écrit :
> > Hi Nicolas,
> >
> > On Fri, May 15, 2020 at 8:38 AM Nicolas Dufresne <
> > nico...@ndufresne.ca
> > > wrote:
> > > Le lundi 11 mai 2020 à 20:49 +0900, Keiichi Watanabe a é
Update the PTEH register to contain the VPN at which an MMU
exception occured as specified by the SH4 reference.
Signed-off-by: Alexandre Courbot
---
target-sh4/helper.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index
In cpu_sh4_invalidate_tlb, the UTLB was invalidated twice and the
ITLB left unchaged, probably because of some unfortunate copy/paste.
Signed-off-by: Alexandre Courbot
---
target-sh4/helper.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-sh4/helper.c b
Update the PTEH register to contain the VPN at which an MMU
exception occured as specified by the SH4 reference.
---
target-sh4/helper.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 2d76f22..c34d2f5 100644
--- a/target-s
Exception index of address read error should be 0x0e0.
---
target-sh4/helper.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 45449ea..2d76f22 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -479,7 +479,7 @@ i
Add support for the following missing priviledged intructions:
For SH4:
- stc sgr, Rn
- stc.l sgr, @-Rn
For SH4A:
- ldc Rm, sgr
- ldc.l @Rm+, sgr
Signed-off-by: Alexandre Courbot
---
target-sh4/translate.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-sh4
redeclares LDST to use these sub-macro.
Signed-off-by: Alexandre Courbot
---
target-sh4/translate.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index d0d6c00..3abafd0 100644
--- a/target-sh4/translate.c
+++ b
This series of patch adds support for the missing ldc & stc privileged
instructions with the sgr register. In order to take the difference
of support between SH4A and SH4 (which does not recognize ldc with sgr),
the LDST macro has been split into two simpler macros.
Changelog from v1: signed off t
The LDST macro is used to generate ldc and stc instructions that work with a
specific register. However, the SGR register only supports stc up to SH4A,
which supports both stc and ldc. This patch creates two sub-macros named LD
and ST that handle generating ldc and stc instructions separately, and
This series of patch adds support for the missing ldc & stc privileged
instructions with the sgr register. In order to take the difference
of support between SH4A and SH4 (which does not recognize ldc with sgr),
the LDST macro has been split into two simpler macros.
[PATCH 1/2] target-sh4: Split t
Add support for the following missing priviledged intructions:
For SH4:
- stc sgr, Rn
- stc.l sgr, @-Rn
For SH4A:
- ldc Rm, sgr
- ldc.l @Rm+, sgr
---
target-sh4/translate.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
i
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