On 7/18/25 9:28 AM, Vasant Hegde wrote:
Alejandro, Sairaj,
On 7/17/2025 7:18 PM, Alejandro Jimenez wrote:
On 7/17/25 2:07 AM, Michael S. Tsirkin wrote:
On Thu, Jul 17, 2025 at 11:17:05AM +0530, Sairaj Kodilkar wrote:
On 7/16/2025 6:59 PM, Michael S. Tsirkin wrote:
On Wed, Jul 16
On 7/17/25 2:07 AM, Michael S. Tsirkin wrote:
On Thu, Jul 17, 2025 at 11:17:05AM +0530, Sairaj Kodilkar wrote:
On 7/16/2025 6:59 PM, Michael S. Tsirkin wrote:
On Wed, Jul 16, 2025 at 06:26:37PM +0530, Sairaj Kodilkar wrote:
On 7/16/2025 6:07 PM, Philippe Mathieu-Daudé wrote:
On 16/7/25
On 6/13/25 4:46 AM, Sairaj Kodilkar wrote:
On 5/31/2025 3:00 AM, Alejandro Jimenez wrote:
Hey Sairaj,
On 5/29/25 2:16 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:46 AM, Alejandro Jimenez wrote:
On reset, restore the default address translation mode for all the
address spaces managed by
Correctly calculate the Device Table size using the format encoded in the
Device Table Base Address Register (MMIO Offset h).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/a
...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Co-developed-by: Ethan MILON
Signed-off-by: Ethan MILON
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iom
The DeviceID bits are extracted using an incorrect offset in the call to
amdvi_iotlb_remove_page(). This field is read (correctly) earlier, so use
the value already retrieved for devid.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by:
han fixing truncation bug.
Thank you,
Alejandro
v3:
https://lore.kernel.org/all/20250529193023.3590780-1-alejandro.j.jime...@oracle.com/
Alejandro Jimenez (7):
amd_iommu: Fix Miscellaneous Information Register 0 encoding
amd_iommu: Fix Device ID decoding for INVALIDATE_IOTLB_PAGES command
amd_iom
not yet implemented.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 7 ---
hw/i386/amd_iommu.h | 9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
From: Ethan Milon
The variable `oldval` was incorrectly declared as a 32-bit `uint32_t`.
This could lead to truncation and incorrect behavior where the upper
read-only 32 bits are significant.
Fix the type of `oldval` to match the return type of `ldq_le_p()`.
Cc: qemu-sta...@nongnu.org
Fixes: d
definitions independent.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.h | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff
Table
Root Pointer[51:6] field in the Device Table Entry format.
Cc: qemu-sta...@nongnu.org
Fixes: b44159fe0078 ("x86_iommu/amd: Add interrupt remap support when VAPIC is
not enabled")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.h | 2 +-
1 file
No functional change.
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.h | 4
1 file changed, 4 deletions(-)
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 96fc5b621e609..8b42913ed8dab 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386
Hi Phil,
On 6/16/25 2:59 AM, Philippe Mathieu-Daudé wrote:
Hi Alejandro,
On 12/6/25 22:59, Alejandro Jimenez wrote:
Hi Ethan,
On 6/12/25 4:36 AM, Ethan MILON wrote:
Hi,
Is this series the right place to include the following minor fix?
I would defer this change for two reasons:
1) This
On 6/11/25 4:29 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
next:
- iova = iova_next;
+ iova = (iova & ~(pagesize - 1)) + pagesize;
Hi Alejandro,
While experimenting with iommu.forcedac=1, I found that above line
causes unsigned int
On 6/12/25 6:37 AM, Vasant Hegde wrote:
Alejandro,
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
Make amdvi_get_pte_entry() return an error value (-1) in cases where the
memory read fails, versus the current return of 0 to indicate failure.
The reason is that 0 is also a valid PTE value
On 6/12/25 2:54 AM, Vasant Hegde wrote:
Alejandro,
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
Invalidating the entire address space (i.e. range of [0, ~0ULL]) is a
valid and required operation by vIOMMU implementations. However, such
invalidations currently trigger an assertion unless
On 6/6/25 9:42 AM, Igor Mammedov wrote:
On Thu, 1 May 2025 23:04:56 +0200
Philippe Mathieu-Daudé wrote:
@@ -1486,15 +1485,8 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus,
void *opaque, int devfn)
AMDVI_INT_ADDR_FIRST,
o this series.
Alejandro
Thanks,
Ethan
On 5/29/25 9:30 PM, Alejandro Jimenez wrote:
Caution: External email. Do not open attachments or click links, unless this
email comes from a known sender and you know the content is safe.
The main reason for sending this new revision so soon is that
Hey Sairaj,
On 5/29/25 2:16 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:46 AM, Alejandro Jimenez wrote:
On reset, restore the default address translation mode for all the
address spaces managed by the vIOMMU.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 28
On 5/30/25 7:41 AM, Michael S. Tsirkin wrote:
On Fri, May 02, 2025 at 02:15:45AM +, Alejandro Jimenez wrote:
This series adds support for guests using the AMD vIOMMU to enable DMA
remapping for VFIO devices. In addition to the currently supported
passthrough (PT) mode, guest kernels are
The DeviceID bits are extracted using an incorrect offset in the call to
amdvi_iotlb_remove_page(). This field is read (correctly) earlier, so use
the value already retrieved for devid.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by:
Correctly calculate the Device Table size using the format encoded in the
Device Table Base Address Register (MMIO Offset h).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/a
not yet implemented.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 7 ---
hw/i386/amd_iommu.h | 9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
The definitions encoding the maximum Virtual, Physical, and Guest Virtual
Address sizes supported by the IOMMU are using incorrect offsets i.e. the
VASize and GVASize offsets are switched.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by:
No functional change.
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.h | 4
1 file changed, 4 deletions(-)
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 1836b7061d848..31e473924fa20 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386
/).
- Added 'Fixes:' tag to [PATCH 5/7].
- Added Vasant's R-b to patches 4,5,7.
Thank you,
Alejandro
v2:
https://lore.kernel.org/qemu-devel/20250528221725.3554040-1-alejandro.j.jime...@oracle.com/
v1:
https://lore.kernel.org/all/20250311152446.45086-1-alejandro.j.jime...@oracle.c
definitions independent.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.h | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff
Table
Root Pointer[51:6] field in the Device Table Entry format.
Cc: qemu-sta...@nongnu.org
Fixes: b44159fe0078 ("x86_iommu/amd: Add interrupt remap support when VAPIC is
not enabled")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.h | 2 +-
1 file
On 5/29/25 1:26 AM, Vasant Hegde wrote:
Hi,
On 5/29/2025 3:47 AM, Alejandro Jimenez wrote:
Correct mistakes in bitmasks, offsets, decoding of fields, and behavior that
do not match the latest AMD I/O Virtualization Technology (IOMMU)
Specification. These bugs do not trigger problems today
On 5/29/25 1:23 AM, Vasant Hegde wrote:
On 5/29/2025 3:47 AM, Alejandro Jimenez wrote:
Address various issues with definitions of the MMIO registers e.g. for the
Device Table Address Register, the size mask currently encompasses reserved
bits [11:9], so change it to only extract the bits
The DeviceID bits are extracted using an incorrect offset in the call to
amdvi_iotlb_remove_page(). This field is read (correctly) earlier, so use
the value already retrieved for devid.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by:
not yet implemented.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/amd_iommu.c | 7 ---
hw/i386/amd_iommu.h | 9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
acle.com/
[1]
https://lore.kernel.org/all/20250311152446.45086-1-alejandro.j.jime...@oracle.com/
Alejandro Jimenez (7):
amd_iommu: Fix Miscellanous Information Register 0 offsets
amd_iommu: Fix Device ID decoding for INVALIDATE_IOTLB_PAGES command
amd_iommu: Update bitmasks representing DTE reserved fie
No functional change.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.h | 4
1 file changed, 4 deletions(-)
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 1836b7061d848..31e473924fa20 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -206,10 +206,6
definitions independent.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.h | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/hw/i386/amd_iommu.h
Correctly calculate the Device Table size using the format encoded in the
Device Table Base Address Register (MMIO Offset h).
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
Reviewed-by: Vasant Hegde
---
hw/i386/a
The definitions encoding the maximum Virtual, Physical, and Guest Virtual
Address sizes supported by the IOMMU are using incorrect offsets i.e. the
VASize and GVASize offsets are switched.
Cc: qemu-sta...@nongnu.org
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by:
Table
Root Pointer[51:6] field in the Device Table Entry format.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 09352672bdcc2..1836b7061d848 100644
Table
Root Pointer[51:6] field in the Device Table Entry format.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index 09352672bdcc2..1836b7061d848 100644
Hi Ethan,
On 5/20/25 6:18 AM, Ethan MILON wrote:
Hi,
On 5/2/25 4:15 AM, Alejandro Jimenez wrote:
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common error
Hi Sairaj
On 5/16/25 4:07 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
Hi Alejandro,
Tested the v2, everything looks good when I boot guest with upstream
kernel. But I observed that NVME driver fails to load with guest kernel
version 4.15.0-213-generic. This is
On 5/12/25 3:00 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:46 AM, Alejandro Jimenez wrote:
- if (pte & AMDVI_DEV_TRANSLATION_VALID) {
- level = get_pte_translation_mode(pte);
- if (level >= 7) {
- trace_amdvi_mode_invalid(level, addr);
+ if
On 5/12/25 2:45 AM, Sairaj Kodilkar wrote:
On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
@@ -1035,13 +1070,13 @@ static void
amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr,
return;
}
- if (!amdvi_get_dte(s, devid, entry)) {
- return;
- }
+ dte_ret
that enable the synchronization of
guest I/O page tables with host IOMMU state, at which point an amd-iommu
device property will be introduced to control this capability.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 26 +++---
hw/i386/amd_iommu.h | 3 +++
2 files
Simplify amdvi_page_walk() by making it call the fetch_pte() helper that is
already in use by the shadow page synchronization code. Ensures all code
uses the same page table walking algorithm.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 59
Support dropping all existing mappings on reset. When the guest kernel
reboots it will create new ones, but other components that run before
the kernel (e.g. OVMF) should not be able to use existing mappings from
the previous boot.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 74
nt testing by Sairaj (thank you!)
Thank you,
Alejandro
[0]
https://lore.kernel.org/all/20250414020253.443831-1-alejandro.j.jime...@oracle.com/
Alejandro Jimenez (20):
memory: Adjust event ranges to fit within notifier boundaries
amd_iommu: Document '-device amd-iommu' common options
g list threads.
Signed-off-by: Alejandro Jimenez
---
qemu-options.hx | 23 +++
1 file changed, 23 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index dc694a99a30a..198acab48e8e 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1226,6 +1226,29 @@ SRST
`
whether the specific address space is using address translation (via the
newly introduced addr_translation field). Later, region activation will also
be controlled by availability of DMA remapping capability (via dma-remap
property to be introduced in follow up changes).
Signed-off-by: Alejandro Jimenez
les on the
host.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 7bcba47a01ba..5ce74f2c052d 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -879
configured with
the NpCache capability, so a guest driver issues IOMMU invalidations for
both map() and unmap() operations. This capability is already set by default
and written to the configuration in amdvi_pci_realize() as part of
AMDVI_CAPAB_FEATURES.
Signed-off-by: Alejandro Jimenez
---
hw
encountered.
Do not assume that addresses for a device with DTE[TV]=0 are passed
through (i.e. not remapped) and instead terminate the page table walk
early.
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_io
and used to issue the UNMAP
notification. Using the correct size is essential since the VFIO IOMMU
Type1v2 driver in the host kernel will reject unmap requests that do not
fully cover previous mappings.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 91
u/amd:
Remove redundant domain flush from attach_device()").
Remove the assertion altogether and adjust the range to ensure it does
not cross notifier boundaries.
Signed-off-by: Alejandro Jimenez
---
system/memory.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --gi
.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 5322a614f5d6..698967cc1a88 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -496,7 +496,7 @@ static inline
On reset, restore the default address translation mode for all the
address spaces managed by the vIOMMU.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 82 -
1 file changed, 74 insertions(+), 8 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 2f69459ab68d..bddfe2f93136 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common error conditions.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 45
and UNMAP events.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 48 +
1 file changed, 48 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 5ce74f2c052d..fa5dbc3cc700 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386
The current amdvi_page_walk() is designed to be called by the replay()
method. Rather than drastically altering it, introduce helpers to fetch
guest PTEs that will be used by a page walker implementation.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 123
The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming changes.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 34
address translation for the address space if needed. Requires dma-remap=on.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 78 +++--
1 file changed, 76 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
For the specified address range, walk the page table identifying regions
as mapped or unmapped and invoke registered notifiers with the
corresponding event type.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 75 +
1 file changed, 75
only, no functional change intended.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 170 ++--
1 file changed, 85 insertions(+), 85 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 2cf7e24a21d8..9e500121f6e8 100644
--- a
On 4/22/25 8:48 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
+ if ((ret < 0) || (!ret && !dte_mode)) {
+ /*
+ * The DTE could not be retrieved, it is not valid, or it is
not setup
+ * for paging. In either case, ens
On 4/22/25 8:38 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
When the guest issues an INVALIDATE_IOMMU_PAGES command, decode the
address and size of the invalidation and sync the guest page table state
with the host. This requires walking the guest page table
On 4/22/25 8:26 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming
On 4/22/25 8:17 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
Enable the appropriate memory region for an address space depending on
the address translation mode selected for it. This is currently based on
a generic x86 IOMMMU property, and only done during the
On 4/17/25 6:19 AM, Sairaj Kodilkar wrote:
On 4/17/2025 3:47 AM, Alejandro Jimenez wrote:
On 4/16/25 8:14 AM, Sairaj Kodilkar wrote:
+
+ /* DMA address translation */
+ bool dma_remap;
I think you should use this flag in the remapping path as well.
I am aware that you are
On 4/17/25 11:14 AM, Ethan MILON wrote:
Hi,
On 4/13/25 10:02 PM, Alejandro Jimenez wrote:
For the specified address range, walk the page table identifying regions
as mapped or unmapped and invoke registered notifiers with the
corresponding event type.
Signed-off-by: Alejandro Jimenez
On 4/17/25 8:40 AM, CLEMENT MATHIEU--DRIF wrote:
On 14/04/2025 4:02 am, Alejandro Jimenez wrote:
Caution: External email. Do not open attachments or click links, unless this
email comes from a known sender and you know the content is safe.
The current amdvi_page_walk() is designed to be
On 4/16/25 2:50 PM, Michael S. Tsirkin wrote:
On Wed, Apr 16, 2025 at 09:29:23AM -0400, Alejandro Jimenez wrote:
On 4/16/25 7:36 AM, Sairaj Kodilkar wrote:
+static int amdvi_as_to_dte(AMDVIAddressSpace *as, uint64_t *dte);
+
No need to have this function declaration as it is a
On 4/16/25 8:14 AM, Sairaj Kodilkar wrote:
+
+ /* DMA address translation support */
+ IOMMUNotifierFlag notifier_flags;
+ /* entry in list of Address spaces with registered notifiers */
+ QLIST_ENTRY(AMDVIAddressSpace) next;
+ /* DMA address translation active */
+ bool add
On 4/16/25 7:36 AM, Sairaj Kodilkar wrote:
On 4/14/2025 7:32 AM, Alejandro Jimenez wrote:
Hi Alejandro,
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common
On 4/15/25 2:38 AM, Sairaj Kodilkar wrote:
Hi Alejandro,
On 4/15/2025 1:56 AM, Alejandro Jimenez wrote:
Hi Sairaj,
I'm conflicted by the implementation of the change, so I'd like to
make sure I fully understand...
On 4/10/25 2:44 AM, Sairaj Kodilkar wrote:
Fix th
Hi Sairaj,
I'm conflicted by the implementation of the change, so I'd like to make
sure I fully understand...
On 4/10/25 2:44 AM, Sairaj Kodilkar wrote:
Current amd_iommu enables the iommu_nodma address space when pt_supported
flag is on.
As it should, that is the intended purpose of the i
Support dropping all existing mappings on reset. When the guest kernel
reboots it will create new ones, but other components that run before
the kernel (e.g. OVMF) should not be able to use existing mappings from
the previous boot.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 68
Simplify amdvi_page_walk() by making it call the fetch_pte() helper that
is already in use by the shadow page synchronization code. Ensures all
code uses the same page table walking algorithm.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 60
encountered.
Do not assume that addresses for a device with DTE[TV]=0 are passed
through (i.e. not remapped) and instead terminate the page table walk
early.
Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU")
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_io
The size of the region to invalidate depends on the S bit and address
encoded in the command. Add a helper to extract this information, which
will be used to sync shadow page tables in upcoming changes.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 34
and used to issue
the UNMAP notification. Using the correct size is essential since the
VFIO IOMMU Type1v2 driver in the host kernel will reject unmap requests
that do not fully cover previous mappings.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 98
address translation for the address space if needed.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 68 -
1 file changed, 67 insertions(+), 1 deletion(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 3bfa08419ffe..abdd67f6b12c
On reset, restore the default address translation mode for all the
address spaces managed by the vIOMMU.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index
The current amdvi_page_walk() is designed to be called by the replay()
method. Rather than drastically altering it, introduce helpers to fetch
guest PTEs that will be used by a page walker implementation.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 125
.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 110
1 file changed, 102 insertions(+), 8 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 6789e1e9b688..cf83ac607064 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386
For the specified address range, walk the page table identifying regions
as mapped or unmapped and invoke registered notifiers with the
corresponding event type.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 74 +
1 file changed, 74
les on the host.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index cf83ac607064..e24eab34c9e0 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -1902,
whether DMA remapping is available as a global capability, and
if the specific address space is using address translation.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/hw/i386/amd_iommu.c b
Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
common operation required for syncing the shadow page tables. Implement a
helper to do it and check for common error conditions.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 47
: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 34 --
hw/i386/amd_iommu.h | 6 ++
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 22d648c2e0e3..8dbb10d91339 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw
.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 0df658712ec0..5f55be1f4d36 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -958,7 +958,7 @@ static inline
evice vfio-pci,host=0000:a1:00.1,id=net0
---
Alejandro Jimenez (18):
memory: Adjust event ranges to fit within notifier boundaries
amd_iommu: Add helper function to extract the DTE
amd_iommu: Add support for IOMMU notifier
amd_iommu: Unmap all address spaces under the AMD IOMMU on reset
a
regions where a mapping
doesn't currently exist, which is not correct.
Note that after this change there are no users of amdvi_page_fault(),
but since the IO page fault handling will be addressed in upcoming work,
I am choosing to mark it as unused rather than deleting it.
Signed-off-by: Alej
and UNMAP events.
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index e24eab34c9e0..3bfa08419ffe 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386
u/amd:
Remove redundant domain flush from attach_device()").
Remove the assertion altogether and adjust the range to ensure it does
not cross notifier boundaries.
Signed-off-by: Alejandro Jimenez
---
system/memory.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --gi
en as it fails to call kvm_enable_x2apic().
Fix this by adding back kvm_enable_x2apic() call when xtsup=on.
Fixes: 8c6619f3e692 ("hw/i386/amd_iommu: Simplify non-KVM checks on XTSup
feature")
Reported-by: Alejandro Jimenez
Cc: Philippe Mathieu-Daudé
Cc: Joao Martins
Signed-off-by: V
Hi Sairaj Kodilkar,
On 3/20/25 1:11 AM, Arun Kodilkar, Sairaj wrote:
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
The AMD I/O Virtualization Technology (IOMMU) Specification (see Table
8: V,
TV, and GV Fields in Device Table Entry), specifies that a DTE with V=0,
TV=1 does not contain a
On 3/19/25 2:06 AM, Vasant Hegde wrote:
Alejandro,
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
The AMD I/O Virtualization Technology (IOMMU) Specification (see Table 8: V,
TV, and GV Fields in Device Table Entry), specifies that a DTE with V=0,
TV=1 does not contain a valid address
On 3/12/25 12:12 AM, Arun Kodilkar, Sairaj wrote:
Hi Alejandro,
On 3/11/2025 8:54 PM, Alejandro Jimenez wrote:
[...]
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -25,6 +25,8 @@
#include "hw/i386/x86-iommu.h"
#include "qom/object.h"
+#define GENMASK64(h,
not yet implemented.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Alejandro Jimenez
---
hw/i386/amd_iommu.c | 7 ---
hw/i386/amd_iommu.h | 9 ++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 068eeb0cae..8b97abe28c 100644
1 - 100 of 138 matches
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