[PATCH v7 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v7 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v7 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 6: Included "signal-common.h" in target_arch_cpu.h Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU register cloning and reset functions

[PATCH v7 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v7 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v7 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v7 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v7 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtr

[PATCH v7 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v7 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v7 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v7 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v7 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v7 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v7 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file ch

[PATCH v7 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v7 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v7 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

Re: [PULL 32/47] bsd-user: Add RISC-V signal trampoline setup function

t; > > > Implemented the 'setup_sigtramp' function for setting up the signal > > trampoline code in the RISC-V architecture. > > > > Signed-off-by: Mark Corbin > > Signed-off-by: Ajeet Singh > > Reviewed-by: Richard Henderson > > Message-ID:

[PATCH v6 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtr

[PATCH v6 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v6 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v6 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v6 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v6 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v6 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v6 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v6 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v6 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v6 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v6 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v6 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file ch

[PATCH v6 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v6 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v6 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v6 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 5: In target_arch_sigtramp.h removed static const, as there was a compile-time constant issue Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V

[PATCH v6 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v5 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v5 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file ch

[PATCH v5 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v5 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v5 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 4: Minor formatting changes Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Implement RIS

[PATCH v5 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v5 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v5 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v5 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v5 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v5 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v5 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v5 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v5 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtr

[PATCH v5 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v5 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v5 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v5 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v4 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v4 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtr

[PATCH v4 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v4 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v4 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v4 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v4 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v4 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v4 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v4 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v4 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v4 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v4 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v4 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v4 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v4 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v4 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 3: Minor comment changes and all the patches have been reviewed by Richard Henderson Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU regi

[PATCH v4 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file ch

[PATCH v3 08/17] bsd-user: Implement RISC-V sysarch system call emulation

From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corb

[PATCH v3 14/17] bsd-user: Implement RISC-V signal trampoline setup functions

the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed

[PATCH v3 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v3 15/17] bsd-user: Implement 'get_mcontext' for RISC-V

orbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 + 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signa

[PATCH v3 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling

: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index

[PATCH v3 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v3 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v3 12/17] bsd-user: Add generic RISC-V64 target definitions

From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh

[PATCH v3 06/17] bsd-user: Define RISC-V register structures and register copying

ure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv

[PATCH v3 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

[PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file changed, 47 insertions(+) create mode 1

[PATCH v3 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v3 00/17] bsd-user: Comprehensive RISCV Support

Key Changes Compared to Version 2: Patch 1: changed loop conditions to avoid setting r0 Patch 7: replaced manual byte swapping with const_le32 Patch 9: used ROUND_DOWN to align the stack Mark Corbin (15): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU exec

[PATCH v3 01/17] bsd-user: Implement RISC-V CPU initialization and main loop

From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored

[PATCH v3 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 1 file changed, 4 insertions(+) create mode 100644 configs/targets

[PATCH v3 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v3 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtr

[PATCH v3 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection

Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b

[PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions

-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h

[PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions

From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++ 1 file changed, 14 insertions

[PATCH v2 13/17] bsd-user: Define RISC-V signal handling structures and constants

From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h

[PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support

zes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans --- bsd-user/riscv/target_arch_thread.h | 47 + 1 file changed, 47 insertions(+) create mode 1

[PATCH v2 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV

From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off

[PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup

From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajee

[PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function

From: Mark Corbin Implemented the `setup_sigtramp` function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtramp.h | 46

[PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants

From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet

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