On 25 Aug 2014, at 11:20, Sergey Fedorov wrote:
> On 22.08.2014 14:29, Fabian Aggeler wrote:
>> The existing implementation does not support Security Extensions mentioned
>> in the GICv1 and GICv2 architecture specification. Security Extensions are
>> not available on all GICs. This property mak
On 19 Aug 2014, at 16:03, Peter Maydell wrote:
> On 17 August 2014 15:24, Fabian Aggeler wrote:
>> This adds a device model for the PrimeXsys System Controller (SP810)
>> which is present in the Versatile Express motherboards. It is
>> so far read-only but allows to read the SCCTRL register.
>>
On 06 Aug 2014, at 01:03, Peter Crosthwaite
wrote:
> On Tue, Aug 5, 2014 at 7:32 PM, Fabian Aggeler wrote:
>> This adds a device model for the PrimeXsys System Controller (SP810)
>> which is present in the Versatile Express motherboards. It is
>> so far read-only but allows to set the SCCTRL r
On 17 Jul 2014, at 01:29, Peter Crosthwaite
wrote:
> On Thu, Jul 17, 2014 at 1:05 AM, Alex Bennée wrote:
>>
>> Fabian Aggeler writes:
>>
>>> The SP810, which is present in the Versatile Express motherboards,
>>> allows to set the timing reference to either REFCLK or TIMCLK.
>>> QEMU currentl
On 01 Jul 2014, at 01:09, greg.bell...@linaro.org wrote:
> From: Fabian Aggeler
>
> Implements NSACR register with corresponding read/write functions
> for ARMv7 and ARMv8.
>
Actually, in this patch we could add a check in cpu_get_tb_cpu_state() (cpu.h)
to not set
the ARM_TBFLAG_CPACR_FPEN_
Hey Greg
Great to see this version. I will try to go through it in the next days.
Best,
Fabian
On 01 Jul 2014, at 01:09, greg.bell...@linaro.org wrote:
> From: Greg Bellows
>
> Updated Fabian's v3 patchset for review comments. This patchset includes
> changes in support of the security exten
Hm…yes, this case is missing, but it is only missing for ARMv7 as this bit is
RES0 in ARMv8. Even in ARMv7 it is IMPDEF whether
this bit is supported. And since ARMv7 mentions, that this bit is deprecated
from the introduction of Virtualization Extensions
I did not care to add this special case.
On 23 Jun 2014, at 23:40, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 10 June 2014 18:55, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a no
On 17 Jun 2014, at 08:12, Edgar E. Iglesias wrote:
> On Fri, Jun 13, 2014 at 05:06:15PM -0500, Greg Bellows wrote:
>> I just wanted to point out that the change from array-notation to hard-code
>> numbers in the names undoes Edgar's EL2/EL3 changes. I prefer this way
>> over the array notation.
On 13 Jun 2014, at 20:27, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 10 June 2014 18:54, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
mailto:s.fedo...@samsun
On 13 Jun 2014, at 00:43, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 10 June 2014 18:54, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
bits when modifying CPSR.
Signed-off-by: Fabian Aggeler mailto:aggel...@ethz.ch>>
---
target-arm/helper.c | 42 +
On 12 Jun 2014, at 23:56, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 10 June 2014 18:54, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
Adds a dedicated function for IRQ and FIQ exceptions to determine
target_el and mode (Aarch32) according to tables in ARM ARMv8 and
ARM ARM v7
On 12 Jun 2014, at 23:55, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
Conflict with Edgar's changes around the name of the security register group
v8_el3_cp_reginfo vs. security_cp_reginfo.
Given that there is a difference between the v7 regs and their v8 equivalents
such as encoding
On 14 Jun 2014, at 00:43, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 10 June 2014 18:55, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 a
On 14 Jun 2014, at 00:49, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 10 June 2014 18:55, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
On 17 Jun 2014, at 07:40, Edgar E. Iglesias wrote:
> On Wed, Jun 11, 2014 at 01:54:48AM +0200, Fabian Aggeler wrote:
>> Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
>> Increase MMU modes since mmu_index is directly infered from arm_
>> current_pl(). Changes assertion in arm_
On 09 Jun 2014, at 17:04, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h| 15 +++
> target-arm/helper.c | 29 +
> 2 files changed, 44 insertions(+)
>
> diff --git a/target-arm/cpu.h
On 09 Jun 2014, at 01:43, Edgar E. Iglesias wrote:
> On Sun, Jun 08, 2014 at 03:51:24PM +0000, Aggeler Fabian wrote:
>>
>> On 30 May 2014, at 09:28, Edgar E. Iglesias wrote:
>>
>>> From: "Edgar E. Iglesias"
>>>
>>> Signed-o
Obviously not v2 but v3 (subject). Sorry for that, please ignore it as I am
going to resend.
Regards,
Fabian
On 10 Jun 2014, at 16:12, Fabian Aggeler wrote:
> Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
> bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Sec
On 09 Jun 2014, at 17:18, Peter Maydell wrote:
> On 9 June 2014 12:27, Peter Maydell wrote:
>> On 5 June 2014 11:39, Fabian Aggeler wrote:
>>> Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
>>> bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
>>> Exte
On 30 May 2014, at 09:28, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-arm/cpu.h | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 9eddcc1..66c58bd 100644
> --- a/target-arm/c
On 31 May 2014, at 02:09, Peter Crosthwaite
wrote:
> On Fri, May 16, 2014 at 10:43 PM, Fabian Aggeler wrote:
>> This patch changes some readfns/writefns to use raw_write
>> and raw_read functions, wich use the fieldoffset specified
>
> "which"
>
>> in ARMCPRegInfo instead of directly accessi
On 02 Jun 2014, at 18:02, Peter Maydell wrote:
> On 30 May 2014 16:15, Fabian Aggeler wrote:
>> Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
>> bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
>> Extensions). Extracting T0SZ/T1SZ now uses 3 bits in A
Ping. This patch was suggested to be sent separately but I can also
include it to the TZ patchset again.
http://patchwork.ozlabs.org/patch/349592/
Thanks,
Fabian
On 16 May 2014, at 14:43, Fabian Aggeler wrote:
> This patch changes some readfns/writefns to use raw_write
> and raw_read function
On 22 May 2014, at 09:33, Edgar E. Iglesias wrote:
> On Tue, May 13, 2014 at 06:16:01PM +0200, Fabian Aggeler wrote:
>> Add SCTLR_EL3 and introduce new function to access correct
>> instance of SCTLR in different modes/worlds.
>
> Hi,
>
> AArch64 has a couple of insn/regs that do address trans
On 22 May 2014, at 14:18, Sergey Fedorov wrote:
>
> On 22.05.2014 15:49, Aggeler Fabian wrote:
>> On 22 May 2014, at 09:41, Edgar E. Iglesias wrote:
>>
>>> On Tue, May 13, 2014 at 06:15:59PM +0200, Fabian Aggeler wrote:
>>>> Banked CP registers can
On 22 May 2014, at 09:41, Edgar E. Iglesias wrote:
> On Tue, May 13, 2014 at 06:15:59PM +0200, Fabian Aggeler wrote:
>> Banked CP registers can be defined with a A32_BANKED_REG macro which defines
>> a non-secure instance of the register followed by an adjacent secure
>> instance.
>> Using a un
On 21 May 2014, at 16:51, Peter Maydell wrote:
> On 13 May 2014 17:15, Fabian Aggeler wrote:
>> --- a/target-arm/cpu.h
>> +++ b/target-arm/cpu.h
>> @@ -631,6 +631,7 @@ enum arm_features {
>> ARM_FEATURE_CBAR, /* has cp15 CBAR */
>> ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
>> AR
On 21 May 2014, at 18:12, Peter Maydell wrote:
> On 14 May 2014 06:43, Sergey Fedorov wrote:
>>
>> On 13.05.2014 20:15, Fabian Aggeler wrote:
>>> From: Svetlana Fedoseeva
>>>
>>> Signed-off-by: Svetlana Fedoseeva
>>> Signed-off-by: Sergey Fedorov
>>> Signed-off-by: Fabian Aggeler
>>> ---
-env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32,
- env->exception.vaddress);
+BANKED_CP15_REG_SET(env, esr_el1, env->exception.fsr);
+BANKED_CP15_REG_SET(env, far_el1,
+deposit64(BANKED_
I guess this makes sense. Shouldn’t we implement two more MMUs to separate
S-EL0/EL0 and S-EL1/EL1
at least for ARMv8 with EL3 running in Aarch64 state? For ARMv7 and ARMv8 with
EL3 in Aarch32 S-PL1
is mapped to PL3, so we only need one additional MMU for S-PL0. If you agree I
could add this ch
You’re configuration works for me on 10.9 with clang from the XCode command
line tools.
$ xcode-select --install
$ clang --version
Apple LLVM version 5.1 (clang-503.0.40) (based on LLVM 3.4svn)
Target: x86_64-apple-darwin13.2.0
Thread model: posix
Best,
Fabian
On 19 May 2014, at 10:19, Peter M
Yes, sorry about that.
Best,
Fabian
> On 15.05.2014, at 20:58, "Sergey Fedorov" wrote:
>
> Can s.fedo...@samsung.com be removed from CC list since this mailbox has
> been deleted? That was my address when I worked for Samsung. Now sending
> to this address results with annoying delivery failur
On 15 May 2014, at 20:42, Sergey Fedorov wrote:
> 13.05.2014 20:15, Fabian Aggeler wrote:
>> @@ -771,6 +862,14 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
>> * IO indicates that this register does I/O and therefore its accesses
>> * need to be surrounded by gen_io_start()/gen_i
On 14 May 2014, at 23:20, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 13 May 2014 11:16, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
Some of SCTRL bits are common for secure and non-secure state.
Translation table base masks are updated on NS-bit switch as
well as on TTBCR wr
The v8 ARM ARM only leaves it as implementation defined when EL2 is not
implemented,
otherwise is has only a non-secure state as Peter said. Another reason why I
chose to make
the default non-secure is the suggested mapping of non-secure Aarch32 registers
to EL1 and
secure Aarch32 registers to E
On 14 May 2014, at 16:19, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 13 May 2014 11:15, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
From: Sergey Fedorov mailto:s.fedo...@samsung.com>>
Define a new ARM CP register info list for the Security Extension feature.
Register that l
making comments.
One thing that held me up from committing sooner was testing my changes. Do
you have a good approach for testing the changes?
Regards,
Greg
On 14 May 2014 03:58, Aggeler Fabian
mailto:aggel...@student.ethz.ch>> wrote:
I see. What is Greg Bellows working on exactly? Also
On 14 May 2014, at 18:42, Greg Bellows
mailto:greg.bell...@linaro.org>> wrote:
On 13 May 2014 11:15, Fabian Aggeler
mailto:aggel...@ethz.ch>> wrote:
Banked CP registers can be defined with a A32_BANKED_REG macro which defines
a non-secure instance of the register followed by an adjacent secure i
...@linaro.org]
Sent: Monday, May 12, 2014 10:39 PM
To: Aggeler Fabian
Cc: Edgar E. Iglesias; Rob Herring; Peter Crosthwaite; QEMU Developers;
Alexander Graf; John Williams; Alex Bennée; Greg Bellows
Subject: Re: [Qemu-devel] [PATCH v1 00/22] target-arm: Preparations for A64 EL2
and 3
On 12 May 2014 20:13
Hi
I’ve been reworking the Samsung patches as part of my Master thesis and I
wanted to send them some time this week. I am currently rebasing them when I
noticed Edgar’s patches. Is there some branch with the patches so I could
rebase on them?
Thanks,
Fabian
On 07 May 2014, at 05:46, Edgar E.
41 matches
Mail list logo
