Hello,
Ping. Any comments on the series ? This doesn't have any code changes
from v6, other than fixing merge conflicts on rebase to upstream.
Thanks,
- Aditya G
On 25/06/08 11:58PM, Aditya Gupta wrote:
> Overview
>
>
> Note: No changes from v7, fixed minor m
Hello,
Ping. Any comments on the series ?
Thanks,
- Aditya G
On 25/06/07 04:34PM, Aditya Gupta wrote:
> Note: No changes, only change compared to v6 is rebased to upstream
>
> Power8E and Power8NVL are not maintained, and not useful to qemu, and
> upstream skiboot also has removed
Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 133
iewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
docs/system/ppc/powernv.rst | 9 +
hw/ppc/pnv.c| 34 ++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa6763077ea8..a61c8d6b203a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1564,6 +1564,7 @@ F: tests/functional/test_ppc64_tuxrun.py
PowerNV (Non
With all Power11 support in place, add Power11 PowerNV test.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
tests/functional/test_ppc64_powernv.py | 4
1 file
Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod
code as the Power11 core is same as Power10 core.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
ttps://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64le_powernv8-2025.02
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Suggested-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Signed-off-by:
Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementation.
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 57
: no change
- remove commit to make Power11 as default
v2:
+ split powernv patch into homer,lpc,occ,psi,sbe
+ reduce code duplication by reusing power10 code
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ update docs
+ update sk
Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 311 +
hw/ppc/pnv_core.c | 17 ++
include/hw/ppc/pnv.h | 20 +++
include/hw/ppc/pnv_chip.h | 7 +
include/hw/ppc/pnv_xscom.h
OWERPC_DEPRECATED_CPU macro
v2:
+ add mention to docs/about/deprecated.rst
+ add '(deprecated)' in output of qemu-system-ppc64 --cpu help
Base Commit: 96215036f47403438c7c7869b7cd419bd7a11f82
Aditya Gupta (2):
target/ppc: Introduce macro for deprecating PowerPC CPUs
target/
power8nvl(alias for power8nvl_v1.0)
power8_v2.0 PVR 004d0200
...
Suggested-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Aditya Gupta
---
target/ppc/cpu-models.c | 12 +++-
target/ppc/cpu_init.c | 7 ++-
2
.
Suggested-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
docs/about/deprecated.rst | 9 +
target/ppc/cpu-models.c | 8
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/docs/about/deprec
On 25/04/22 07:53AM, Cédric Le Goater wrote:
> On 4/22/25 06:41, Aditya Gupta wrote:
> > <...snip...>
> >
> > diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
> > index 05381441a9ff..527f2613dcb5 100644
> > --- a/docs/about/deprecated.
.
Suggested-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Aditya Gupta
---
docs/about/deprecated.rst | 9 +
target/ppc/cpu-models.c | 8
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/depre
power8nvl(alias for power8nvl_v1.0)
power8_v2.0 PVR 004d0200
...
Suggested-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Aditya Gupta
---
target/ppc/cpu-models.c | 12 +++-
target/ppc/cpu_init.c | 7 ++-
2
)' in output of qemu-system-ppc64 --cpu help
Base Commit: a9cd5bc6399a80fcf233ed0fffe6067b731227d8
Aditya Gupta (2):
target/ppc: Introduce macro for deprecating PowerPC CPUs
target/ppc: Deprecate Power8E and Power8NVL
docs/about/deprecated.rst | 9 +
target/ppc/cpu-models.c
Hi Harsh,
Thanks for reviewing.
On 25/04/21 04:21PM, Harsh Prateek Bora wrote:
>
>
> On 3/23/25 23:10, Aditya Gupta wrote:
> > <...snip...>
> >
> > +switch (cmd) {
> > +case FADUMP_CMD_REGISTER:
> > +ret_val = do_fadump_register();
power8nvl(alias for power8nvl_v1.0)
power8_v2.0 PVR 004d0200
...
Suggested-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Aditya Gupta
---
target/ppc/cpu-models.c | 12 +++-
target/ppc/cpu_init.c | 7 ++-
2 files changed, 17 insertions(+)
.
Suggested-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Aditya Gupta
---
docs/about/deprecated.rst | 9 +
target/ppc/cpu-models.c | 8
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/depre
ry 'if'
v3:
+ add 'deprecation_note' argument to the POWERPC_DEPRECATED_CPU macro
v2:
+ add mention to docs/about/deprecated.rst
+ add '(deprecated)' in output of qemu-system-ppc64 --cpu help
Base Commit: a9cd5bc6399a80fcf233ed0fffe6067b731227d8
Aditya Gupta (2):
target/
Please ignore this mail (only cover letter got sent). Resent another v5.
Sorry for posting this so late, had gone on a vacation.
Thanks,
- Aditya G
ry 'if'
v3:
+ add 'deprecation_note' argument to the POWERPC_DEPRECATED_CPU macro
v2:
+ add mention to docs/about/deprecated.rst
+ add '(deprecated)' in output of qemu-system-ppc64 --cpu help
Base Commit: a9cd5bc6399a80fcf233ed0fffe6067b731227d8
Aditya Gupta (2):
target/
ry 'if'
v3:
+ add 'deprecation_note' argument to the POWERPC_DEPRECATED_CPU macro
v2:
+ add mention to docs/about/deprecated.rst
+ add '(deprecated)' in output of qemu-system-ppc64 --cpu help
Base Commit: a9cd5bc6399a80fcf233ed0fffe6067b731227d8
Aditya Gupta (2):
target/
Hi,
Any comments on the series ?
Thanks,
- Aditya Gupta
On 23/03/25 23:09, Aditya Gupta wrote:
Overview
=
Implemented Firmware Assisted Dump (fadump) on PSeries machine in QEMU.
Fadump is an alternative dump mechanism to kdump, in which we the firmware
does a memory preserving
On 25/03/29 06:42PM, Philippe Mathieu-Daudé wrote:
> Hi Aditya,
>
> On 29/3/25 15:26, Aditya Gupta wrote:
> > <...snip...>
> >
> > --- a/target/ppc/cpu-models.c
> > +++ b/target/ppc/cpu-models.c
> > @@ -32,
0)
power8_v2.0 PVR 004d0200
power8 (alias for power8_v2.0)
power9_v2.0 PVR 004e1200
power9_v2.2 PVR 004e1202
...
Suggested-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Cover Letter
Power8E and Power8NVL are not maintaine
l will boot
assuming fadump dump is "NOT" active, and try to register for fadump,
but since we already have fadump registered in QEMU internal state, the
register rtas call will fail with: "DUMP ACTIVE"
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_fadump.c | 161 ++
On 25/03/25 20:08, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc:
s of this patch, the "kernel-dump" device tree entry is still not
added for the second boot, so after crash, the second kernel will boot
assuming fadump dump is "NOT" active, and try to register for fadump,
but since we already have fadump registered in QEMU internal state, the
regis
i Jan 3 00:15:17 IST 2025
MACHINE: ppc64le (1000 Mhz)
MEMORY: 4 GB
PANIC: "Kernel panic - not syncing: sysrq triggered crash"
PID: 269
COMMAND: "sh"
TASK: ca050b00 [THREAD_INFO: ca050b00]
CPU: 0
oduced in any patch
+ add functional test for pseries as suggested by nick
+ fix multiple issues pointed by harsh and nick
+ fix bug in cpu register saving where it was being stored in
little-endian
- removed 'is_next_boot_fadump' and used fadump header's status flag to
On 25/03/31 01:37PM, Philippe Mathieu-Daudé wrote:
> On 30/3/25 23:10, Aditya Gupta wrote:
> > <...snip...>
> >
> Reviewed-by: Philippe Mathieu-Daudé
Thanks for the tag, Philippe !
I will be posting a v5 with this patch split into 2 as suggested by
Ced
On 25/03/31 08:41AM, Cédric Le Goater wrote:
> On 3/29/25 15:26, Aditya Gupta wrote:
> > Power8E and Power8NVL variants are not of much use in QEMU now, and not
> > being maintained either.
> >
> > Newer skiboot might not be able to boot Power8NVL since skiboot
On 25/03/30 10:24AM, Philippe Mathieu-Daudé wrote:
> On 29/3/25 19:04, Aditya Gupta wrote:
> > <...snip...>
> >
> > +if (_deprecation_note) {
> > \
> > +cc->deprecation_note = _deprecation_
ption ..."
Signed-off-by: Aditya Gupta
---
hw/ppc/meson.build| 1 +
hw/ppc/spapr_fadump.c | 22 +++
hw/ppc/spapr_rtas.c | 66 +
include/hw/ppc/spapr.h| 11 +-
include/hw/ppc/spapr_fadump.h | 69 ++
0)
power8_v2.0 PVR 004d0200
power8 (alias for power8_v2.0)
power9_v2.0 PVR 004e1200
power9_v2.2 PVR 004e1202
...
Suggested-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Cover Letter
Power8E and Power8NVL are not maintaine
0)
power8_v2.0 PVR 004d0200
power8 (alias for power8_v2.0)
power9_v2.0 PVR 004e1200
power9_v2.2 PVR 004e1202
...
Suggested-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Cover Letter
Power8E and Power8NVL are not maintaine
On 25/03/28 08:23AM, Cédric Le Goater wrote:
> On 3/28/25 05:06, Aditya Gupta wrote:
> > Power8E and Power8NVL variants are not of much use in QEMU now, and not
> > being maintained either.
> >
> > Deprecate the 8E and 8NVL variants.
> >
> > After depr
On 25/03/28 09:02AM, Cédric Le Goater wrote:
> On 3/27/25 21:07, Aditya Gupta wrote:
> > <...snip...>
>
> In OPAL, the Power11 "CPU: PXYZ generation processor" string seems
> inconsistent with the previous generations :
Yes, that was intentional due to how
On 28/03/25 13:29, Cédric Le Goater wrote:
On 3/27/25 21:07, Aditya Gupta wrote:
<...snip...>
Reviewed-by: Cédric Le Goater
Thanks for the tag, and all your reviews and the help in fixes, Cédric !
- Aditya G
Thanks,
C.
.
...
$ ./build/qemu-system-ppc64 -M pseries --cpu power8e -nographic
qemu-system-ppc64: warning: CPU model power8e_v2.1-powerpc64-cpu is
deprecated -- CPU is unmaintained.
...
Suggested-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Cover Letter
For me, Power8NVL won&#
Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 133
Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementation.
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 57
ttps://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64le_powernv8-2025.02
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Suggested-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
tests/fu
Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod
code as the Power11 core is same as Power10 core.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c
iewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
docs/system/ppc/powernv.rst | 9 +
hw/ppc/pnv.c| 34 ++
2 files changed, 39 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 311 +
hw/ppc/pnv_core.c | 17 ++
include/hw/ppc/pnv.h | 20 +++
include/hw/ppc/pnv_chip.h | 7 +
include/hw/ppc/pnv_xscom.h
review
+ patch #6-#11: no change
- remove commit to make Power11 as default
v2:
+ split powernv patch into homer,lpc,occ,psi,sbe
+ reduce code duplication by reusing power10 code
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ upd
With all Power11 support in place, add Power11 PowerNV test.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
tests/functional/test_ppc64_powernv.py | 4
1 file changed, 4 insertions(+)
diff
On 25/03/26 11:09PM, Cédric Le Goater wrote:
> On 3/26/25 18:21, Aditya Gupta wrote:
> > On 26/03/25 13:39, Cédric Le Goater wrote:
> >
> > > On 3/25/25 18:38, Aditya Gupta wrote:
> > > > <...snip...>
> > > >
> > > > On 25/03/25 2
image boots but since it doesn't "print" p11 in its dmesg log, the
powernv test fails with it. Will use your images.
Thanks,
- Aditya Gupta
Thanks,
C.
On 26/03/25 13:39, Cédric Le Goater wrote:
On 3/25/25 18:38, Aditya Gupta wrote:
<...snip...>
On 25/03/25 22:45, Cédric Le Goater wrote:
One nice about it IIRC was being able to tune the number of
PHBs per chip, which reduced booting time (for 16s) and also
provided support to test v
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-
On 25/03/25 22:50, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
Implement Pnv11Chip, currently without chiptod, xive and phb.
Chiptod, XIVE, PHB are implemented in later patches.
Since Power11 core is same as Power10, the implementation of Pnv11Chip
is a duplicate of
On 25/03/25 22:45, Cédric Le Goater wrote:
On 3/25/25 18:07, Aditya Gupta wrote:
On 25/03/25 20:17, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
<...snip...>
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
There was a lot of work done to have dynami
Could you please consider deprecating the POWER8NVL and POWER8E CPUs
and associated chips and machines ? I think keeping POWER8 is fine
since it has different HW implementation from the following
generations.
However, the POWER8NVL and POWER8E variants don't add much to QEMU.
They were practical
On 25/03/25 22:36, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
On 25/03/25 20:17, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
<...snip...>
+static void pnv_machine_power11_class_init(ObjectClass *oc, void
*data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ static cons
On 25/03/25 20:08, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
<...snip...>
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -366,6 +366,20 @@ static const TypeInfo pnv_sbe_power10_type_info = {
.name = TYPE_PNV10_SBE,
.parent = TYPE_PN
Hi Cedric,
Thanks for your reviews.
On 25/03/25 20:04, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
<...snip...>
@@ -238,6 +238,13 @@ static const TypeInfo
pnv_homer_power10_type_info = {
.parent = TYPE_PNV_HOMER,
.instance_size = sizeof(Pn
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 306 +
hw/ppc/pnv_core.c | 17 +++
include/hw/ppc/pnv.h | 20 +++
include/hw/ppc/pnv_chip.h | 7 +
include/hw/ppc/pnv_xscom.h | 49
Hi Cedric,
On 24/03/25 13:11, Cédric Le Goater wrote:
Hello Aditya,
On 3/8/25 21:51, Aditya Gupta wrote:
Overview
Add support for Power11 powernv machine type, to emulate PowerNV VMs
running on Power11.
Could you please consider deprecating the POWER8NVL and POWER8E CPUs
and
as Piggin
Signed-off-by: Aditya Gupta
---
docs/system/ppc/powernv.rst | 9 +
hw/ppc/pnv.c| 36
2 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
index f3e
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementation.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 57
Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 132
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod
code as the Power11 core is same as Power10 core.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c
+ patch #6-#11: no change
- remove commit to make Power11 as default
v2:
+ split powernv patch into homer,lpc,occ,psi,sbe
+ reduce code duplication by reusing power10 code
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ upda
l crash due to no special handling for fadump in ibm,os-term
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_fadump.c | 111 --
hw/ppc/spapr_rtas.c | 2 +-
include/hw/ppc/spapr_fadump.h | 2 +-
3 files changed, 108 insertions(+), 7 deletion
boot in QEMU if fadump is
registered, and the second kernel will boot as a normal boot (not
fadump boot)
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_fadump.c | 77 +++
hw/ppc/spapr_rtas.c | 5 +++
include/hw/ppc/spapr_fadump.h | 6 +++
3 fil
On 24/03/25 13:05, Cédric Le Goater wrote:
On 3/24/25 08:13, Aditya Gupta wrote:
Hi Cedric,
<...snip...>
When I do this, every function using Pnv10Chip* will need to be
duplicated to use Pnv11Chip*.
I will do that.
But what do you say about changing Pnv10 chip to Pnv1x chip ?
Hi Cedric,
On 09/03/25 19:38, Cédric Le Goater wrote:
On 3/8/25 21:51, Aditya Gupta wrote:
<...snip...>
static void pnv_chip_power8_instance_init(Object *obj)
{
Pnv8Chip *chip8 = PNV8_CHIP(obj);
@@ -1966,6 +1996,20 @@ static void
pnv_chip_power10_instance_init(Objec
fadump will print the success/failure in earlyboot of
the kernel, while kernel without support of fadump won't print anything
for long time, and without a timeout the testcase keeps waiting till
longer test timeout
Signed-off-by: Aditya Gupta
---
PowerNV also can be tested with th
g fadump dump is "NOT" active, and try to register for fadump,
but since we already have fadump registered in QEMU internal state, the
register rtas call will fail with: "DUMP ACTIVE"
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr.c | 57
On 17/03/25 12:30, Thomas Huth wrote:
On 17/03/2025 07.51, Aditya Gupta wrote:
Hi Thomas,
<...snip...>
+ def test_fadump_pseries_kvm(self):
+ """
+ Test Fadump in PSeries with KVM accel
+ """
+ self.do_test_fadump(is_kvm=Tr
Hi Thomas,
On 17/03/25 11:55, Thomas Huth wrote:
Hi!
On 15/03/2025 07.46, Aditya Gupta wrote:
Add testcases for testing fadump with PSeries and PSeries+KVM
combinations
...
diff --git a/tests/functional/test_ppc64_fadump.py
b/tests/functional/test_ppc64_fadump.py
new file mode 100755
Seems 'Asset' got missed in the documentation by mistake.
Also fix the one spellcheck issue pointed by spellcheck
Signed-off-by: Aditya Gupta
---
docs/devel/testing/functional.rst | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/docs/devel/testing/functio
On 09/03/25 19:40, Cédric Le Goater wrote:
On 3/8/25 21:51, Aditya Gupta wrote:
Update skiboot.lid to below commit which adds support for booting on
Power11:
commit 785a5e3070a8 ("platform: Identify correct bmc platform
based on bmc hw version")
Built with glibc 2.40 an
boot in QEMU if fadump is
registered, and the second kernel will boot as a normal boot (not
fadump boot)
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_fadump.c | 77 +++
hw/ppc/spapr_rtas.c | 5 +++
include/hw/ppc/spapr_fadump.h | 6 +++
3 fil
i Jan 3 00:15:17 IST 2025
MACHINE: ppc64le (1000 Mhz)
MEMORY: 4 GB
PANIC: "Kernel panic - not syncing: sysrq triggered crash"
PID: 269
COMMAND: "sh"
TASK: ca050b00 [THREAD_INFO: ca050b00]
CPU: 0
ption ..."
Signed-off-by: Aditya Gupta
---
hw/ppc/meson.build| 1 +
hw/ppc/spapr_fadump.c | 22 +++
hw/ppc/spapr_rtas.c | 66 +
include/hw/ppc/spapr.h| 11 +-
include/hw/ppc/spapr_fadump.h | 69 ++
g fadump dump is "NOT" active, and try to register for fadump,
but since we already have fadump registered in QEMU internal state, the
register rtas call will fail with: "DUMP ACTIVE"
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr.c | 57
l will boot
assuming fadump dump is "NOT" active, and try to register for fadump,
but since we already have fadump registered in QEMU internal state, the
register rtas call will fail with: "DUMP ACTIVE"
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_fadump.c | 161 ++
fadump will print the success/failure in earlyboot of
the kernel, while kernel without support of fadump won't print anything
for long time, and without a timeout the testcase keeps waiting till
longer test timeout
Signed-off-by: Aditya Gupta
---
PowerNV also can be tested with th
l crash due to no special handling for fadump in ibm,os-term
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_fadump.c | 111 --
hw/ppc/spapr_rtas.c | 2 +-
include/hw/ppc/spapr_fadump.h | 2 +-
3 files changed, 108 insertions(+), 7 deletion
s of this patch, the "kernel-dump" device tree entry is still not
added for the second boot, so after crash, the second kernel will boot
assuming fadump dump is "NOT" active, and try to register for fadump,
but since we already have fadump registered in QEMU internal state, the
regis
ggested by nick
+ fix multiple issues pointed by harsh and nick
+ fix bug in cpu register saving where it was being stored in
little-endian
- removed 'is_next_boot_fadump' and used fadump header's status flag to
store it
+ fixed multiple style issues (naming, unnee
s of this patch, the "kernel-dump" device tree entry is still not
added for the second boot, so after crash, the second kernel will boot
assuming fadump dump is "NOT" active, and try to register for fadump,
but since we already have fadump registered in QEMU internal state, the
regis
i Jan 3 00:15:17 IST 2025
MACHINE: ppc64le (1000 Mhz)
MEMORY: 4 GB
PANIC: "Kernel panic - not syncing: sysrq triggered crash"
PID: 269
COMMAND: "sh"
TASK: ca050b00 [THREAD_INFO: ca050b00]
CPU: 0
fadump will print the success/failure in earlyboot of
the kernel, while kernel without support of fadump won't print anything
for long time, and without a timeout the testcase keeps waiting till
longer test timeout
Signed-off-by: Aditya Gupta
---
PowerNV also can be tested with th
On 11/03/25 10:48, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
When MPIPL is used, OPAL/Linux registers memory regions to be preserved
on a Memory-Preserving boot ('crashkernel boot').
The regions are added to two tables: MDST and MDDT (source and
destination ta
l crash due to no special handling for fadump in ibm,os-term
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_fadump.c | 111 --
hw/ppc/spapr_rtas.c | 2 +-
include/hw/ppc/spapr_fadump.h | 2 +-
3 files changed, 108 insertions(+), 7 deletion
On 11/03/25 11:11, Harsh Prateek Bora wrote:
On 2/17/25 12:49, Aditya Gupta wrote:
Linux expect a "ibm,opal/dump" node to know whether MPIPL (aka fadump)
is supported on the hardware.
Export the "ibm,opal/dump" node in QEMU's device tree for Linux to know
that Powe
g fadump dump is "NOT" active, and try to register for fadump,
but since we already have fadump registered in QEMU internal state, the
register rtas call will fail with: "DUMP ACTIVE"
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr.c | 58
boot in QEMU if fadump is
registered, and the second kernel will boot as a normal boot (not
fadump boot)
Signed-off-by: Aditya Gupta
---
hw/ppc/spapr_fadump.c | 77 +++
hw/ppc/spapr_rtas.c | 5 +++
include/hw/ppc/spapr_fadump.h | 1 +
3 fil
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