[PATCH qemu] target/riscv: Add check for 16-bit aligned PC for different priv versions.

From: Yu-Ming Chang For privilege version 1.12 or newer, C always implies Zca. We can only check ext_zca to allow 16-bit aligned PC addresses. For older privilege versions, we only check C. Signed-off-by: Yu-Ming Chang --- target/riscv/cpu.h | 12 target/riscv

[PATCH qemu] target/riscv: Only check ext_zca for 16-bit aligned PC.

From: Yu-Ming Chang Since C always implies Zca, Zca is always enabled when 16-bit insructions are supported. we can only check ext_zca to allow 16-bit aligned PC addresses. Signed-off-by: Yu-Ming Chang --- target/riscv/insn_trans/trans_rvi.c.inc | 5 ++--- target/riscv/op_helper.c

[PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret.

From: Yu-Ming Chang We only check RVC to allow 16-bit aligned return addreses. This will cause issues when only ext_zca is enabled without RVC: 16-bit instructions are allowed, but 16-bit aligned return address are not. We should also check ext_zca to permit 16-bit aligned return addresses. Sign

[PATCH qemu] target/riscv: Check ext_zca for misaligned return address of mret/sret.

From: Yu-Ming Chang Only check misa.C will cause issues when ext_zca is enabled without misa.C being set. For example, only enable ext_zce. Signed-off-by: Yu-Ming Chang --- target/riscv/op_helper.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/op

[PATCH qemu v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

of riscv_csrrw_debug(). And tried solve the issue of `From` email address. Best regards, Yuming target/riscv/cpu.h | 4 +++ target/riscv/csr.c | 57 target/riscv/op_helper.c | 6 ++--- 3 files changed, 58 insertions(+), 9 deletions