[PATCH qemu] target/riscv/cpu.c: Fix elen check

From: Dongxue Zhang Should be cpu->cfg.elen in range [8, 64]. Signed-off-by: Dongxue Zhang Reviewed-by: LIU Zhiwei Message-ID: Reviewed-by: Frank Chang Message-ID: --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/c

[PATCH qemu] target/riscv/cpu.c: Fix elen check

From: Dongxue Zhang Should be cpu->cfg.elen in range [8, 64]. Signed-off-by: Dongxue Zhang Reviewed-by: LIU Zhiwei Reviewed-by: Frank Chang --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6fe176e483..5dc

[PATCH qemu] target/riscv/cpu.c: Fix elen check

From: Dongxue Zhang Should be cpu->cfg.elen in range [8, 64]. Signed-off-by: Dongxue Zhang --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6fe176e483..5dc51f7912 100644 --- a/target/riscv/cpu.c +++ b/targe

[PATCH qemu] target/riscv/cpu.c: Fix elen check

From: Dongxue Zhang Should be cpu->cfg.elen in range [8, 64]. Signed-off-by: Dongxue Zhang --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6fe176e483..5dc51f7912 100644 --- a/target/riscv/cpu.c +++ b/targe

[PATCH] target/riscv/cpu.c: Fix elen check

Should be cpu->cfg.elen in range [8, 64]. Signed-off-by: Dongxue Zhang

Re: [Qemu-devel] [PATCH 2/2] target-mips/translate.c: Add judgement for msb and lsb

On 07/29/2014 06:52 AM, Aurelien Jarno wrote: On Mon, Jul 28, 2014 at 11:34:30PM +0100, Peter Maydell wrote: On 28 July 2014 23:32, Aurelien Jarno wrote: On Mon, Jul 28, 2014 at 11:01:02PM +0100, Peter Maydell wrote: This may be true, but the TCG README doesn't define negative lengths as bein

[Qemu-devel] Some patch about mips, gen_HILO bug fix.

Hi all, I make three patch about mips 1: Fix my email address in dsp_helper.c 2: Fix repl_ph, value should sign-extend to target_long 3: Fix gen_HILO, there is a bug when we use dsp arch, at that time acc index will be 0-3, and mipsdsp already add in. mipsdsp just take acc index from opcode, on ot

[Qemu-devel] How to get gpr register contents in translate.c

Hello everyone, I'm a newcomer here, nice to see you! Now I get trouble in translate.c. I really want to get gpr value in translate.c, but cpu_gpr[rs]'s type is TCGv, can not get the real value of rs. Is the have any method or macro can made it? Thanks for your attention, have a nice day!