On Wed, Jul 9, 2025 at 12:53 AM Philippe Mathieu-Daudé
wrote:
>
> Check endianness at runtime to remove the target-specific
> TARGET_BIG_ENDIAN definition. Use cpu_to_[be,le]XX() from
> "qemu/bswap.h" instead of tswapXX() from "exec/tswap.h".
>
> Suggested-by: Richard Henderson
> Signed-off-by: P
Hi
On Tue, Jul 8, 2025 at 9:07 PM Andrew Keesler wrote:
>
> Thanks to 72d277a7, 1ed2cb32, and others, EDID (Extended Display
> Identification Data) is propagated by QEMU such that a virtual display
> presents legitimate metadata (e.g., name, serial number, preferred
> resolutions, etc.) to its co
Philippe Mathieu-Daudé writes:
> Hi Steve,
>
> On 8/7/25 19:24, Steve Sistare wrote:
>> Add a unit test for qom-list-getv.
>> Signed-off-by: Steve Sistare
>> ---
>> tests/qtest/qom-test.c | 64
>> ++
>> 1 file changed, 64 insertions(+)
>> diff
Hi Bernhard,
Thanks for your patch!
There was an identical patch last week on the list:
https://lore.kernel.org/qemu-rust/20250703-rust_bindings_allow_unnecessary_transmutes-v1-1-692ca210d...@linaro.org/
--
Manos Pitsidianakis
Emulation and Virtualization Engineer at Linaro Ltd
>-Original Message-
>From: Nicolin Chen
>Subject: Re: [PATCH v3 02/20] hw/pci: Introduce
>pci_device_get_viommu_cap()
>
>On Wed, Jul 09, 2025 at 03:38:49AM +, Duan, Zhenzhong wrote:
>> >> +enum {
>> >> +VIOMMU_CAP_STAGE1 = BIT_ULL(0), /* stage1 page table
>> >supported */
>> >>
On Wed, Jul 09, 2025 at 03:38:49AM +, Duan, Zhenzhong wrote:
> >> +enum {
> >> +VIOMMU_CAP_STAGE1 = BIT_ULL(0), /* stage1 page table
> >supported */
> >> +};
> >
> >Thanks for this work. I am happy to see that we can share the
> >common code that allocates a NESTING_PARENT in the core usin
>-Original Message-
>From: Nicolin Chen
>Subject: Re: [PATCH v3 02/20] hw/pci: Introduce
>pci_device_get_viommu_cap()
>
>On Tue, Jul 08, 2025 at 07:05:43AM -0400, Zhenzhong Duan wrote:
>> diff --git a/include/hw/iommu.h b/include/hw/iommu.h
>> new file mode 100644
>> index 00..e
On 25.05.2025 16:27, marcandre.lur...@redhat.com wrote:
From: Volker Rümelin
The buffer size calculated by AUD_get_buffer_size_out() is often
incorrect. sw->hw->samples * sw->hw->info.bytes_per_frame is the
size of the mixing engine buffer in audio frames multiplied by
the size of one frame of
Hi maintainers,
This is a kindly ping, could you help to review this patch series?
Thanks,
Shaoqin
On 7/4/25 11:03 AM, Shaoqin Huang wrote:
Currently the ramfb device loads the vgabios-ramfb.bin unconditionally, but only
the x86 need the vgabios-ramfb.bin, this can cause that when use the
rele
On Tue, Jul 8, 2025, 7:23 PM Paolo Bonzini wrote:
> On 7/8/25 22:36, John Snow wrote:
> > centos_stream_9 3.9.23 21.3.1 53.0.0 3.4.3 BaseOS, CRB
>
> Ok, so the lowest version of Sphinx (3.4.3) is currently used for CentOS
> Stream 9. It's supported for roughly 2 more years, until 1
Function loongarch_cpu_post_init() is implemented and used in the
same file target/loongarch/cpu.c, it can be defined as static function.
This patch moves implementation about function loongarch_cpu_post_init()
before it is referenced. And it is only code movement, no function
change.
Signed-off-
With VTLB different TLB entry may have different page size, and
page size is set in PS field of TLB misc. However with STLB, all the
TLB entries have the same page size, page size comes from register
CSR_STLBPS, PS field of TLB misc is not used.
Here PS field of TLB misc is used with all TLB entri
New header file cpu-mmu.h is added and move mmu relative function
declaration to this file.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 30 ++
target/loongarch/cpu.c| 1 +
target/loongarch/cpu_helper.c | 1 +
target/loongarch/inte
Function loongarch_check_pte() can get physical address and access
priviledge, it works on both TLB entry and pte entry. It can be used
at page table walking.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 35 ++-
1 file changed, 10 insertions(+), 25
There is some enhance about LoongArch mmu tcg emulation, add new
header file cpu-mmu.h and function loongarch_check_pte(). Function
loongarch_check_pte() can work on both TLB entry and pte entry.
This patchset mainly is code cleanup and enhancement, its main
purpose is to work for hardware page ta
Common function loongarch_check_pte() is to check tlb entry, return
the physical address and access priviledge. Also it can be used with
page table entry, which is used in page table walker.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu-mmu.h| 9 +
target/loongarch/cpu_helper.c
Move function definition specified with kvm to the corresponding
directory. Also remove header file "cpu.h" including outside of
macro QEMU_KVM_LOONGARCH_H.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 1 +
target/loongarch/cpu.h | 9 -
target/loongarc
On Tue, Jul 08, 2025 at 07:05:43AM -0400, Zhenzhong Duan wrote:
> diff --git a/include/hw/iommu.h b/include/hw/iommu.h
> new file mode 100644
> index 00..e80aaf4431
> --- /dev/null
> +++ b/include/hw/iommu.h
> @@ -0,0 +1,16 @@
> +/*
> + * General vIOMMU capabilities, flags, etc
> + *
> + *
On 7/8/25 22:36, John Snow wrote:
centos_stream_9 3.9.23 21.3.1 53.0.0 3.4.3 BaseOS, CRB
Ok, so the lowest version of Sphinx (3.4.3) is currently used for CentOS
Stream 9. It's supported for roughly 2 more years, until 12.0.
opensuse_leap_15_6 3.6.15 20.0.2 44.1.1 2.
Hi Jonathan,
On 7/3/25 5:09 PM, Jonathan Cameron wrote:
> On Thu, 3 Jul 2025 14:35:36 +0200
> Eric Auger wrote:
>
>> The disassembled DSDT table is given below.
> I think the aim for this one should be to highlight the blobs where it differs
> from the previous rather than having the whole thing
Hi Michael,
On 7/7/25 7:53 PM, Michael S. Tsirkin wrote:
> On Mon, Jul 07, 2025 at 07:09:34PM +0200, Eric Auger wrote:
>> Hi,
>>
>> On 7/3/25 2:35 PM, Eric Auger wrote:
>>> This series enables ACPI PCI hotplug/hotunplug on ARM.
>>> It is not enabled by default and ACPI PCI hotplug can
>>> be selec
The QEMU GDB stub does not expose the ZA storage SME register to GDB via
the remote serial protocol, which can be a useful functionality to debug SME
code. To provide this functionality in Aarch64 target, this patch registers the
SME register set with the GDB stub. To do so, this patch implements t
Am 30. Juni 2025 08:59:22 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 29/6/25 22:48, Bernhard Beschow wrote:
>> Allows to run KVM guests inside the imx8mp-evk machine.
>>
>> Fixes: a4eefc69b237 ("hw/arm: Add i.MX 8M Plus EVK board")
>> CC: qemu-stable
>> Signed-off-by: Bernhard Beschow
>> ---
On 8/7/25 22:53, Philippe Mathieu-Daudé wrote:
On 8/7/25 10:58, Philippe Mathieu-Daudé wrote:
Commit f5fd677ae7c ("win32/socket: introduce qemu_socket_select()
helper") included the "qemu/typedefs.h" header for the Error type,
but files including "system/os-win32.h" should already include
"qemu/
Hi Steve,
On 8/7/25 19:24, Steve Sistare wrote:
Add a unit test for qom-list-getv.
Signed-off-by: Steve Sistare
---
tests/qtest/qom-test.c | 64 ++
1 file changed, 64 insertions(+)
diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c
Missing review: #6 (gdbstub)
Since v7:
- Fixed e.g. typo
- Keep "do *not* use target_big_endian()" warning
- Do not use tswap() in gdbstub
Since v6:
- Added R-b tags
- Fixed typos
- Dropped "Introduce target_base_arch()" because unused so far
- Dropped unrelated patches
Philippe Mathieu-Daudé (8
Reviewed-by: Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/exec/tswap.h | 13 +
include/qemu/target-info.h | 12
cpu-target.c | 7 ---
hw/core/cpu-system.c | 2 +-
hw/display/vga.c
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
target/arm/arm-qmp-cmds.c | 3 ++-
target/loongarch/loongarch-qmp-cmds.c | 3 ++-
target/mips/system/mips-qmp-cmds.c| 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
d
On 8/7/25 19:24, Steve Sistare wrote:
Define the qom-list-getv command, which fetches all the properties and
values for a list of paths. This is faster than qom-tree-get when
fetching a subset of the QOM tree. See qom.json for details.
Signed-off-by: Steve Sistare
---
qapi/qom.json | 5
Restrict "exec/tswap.h" to the tswap*() methods,
move the load/store helpers with the other ones
declared in "qemu/bswap.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
---
include/exec/tswap.h | 70 --
include/qemu/bswap.h
Missing review: #6 (gdbstub)
Since v7:
- Fixed e.g. typo
- Keep "do *not* use target_big_endian()" warning
- Do not use tswap() in gdbstub
Since v6:
- Added R-b tags
- Fixed typos
- Dropped "Introduce target_base_arch()" because unused so far
- Dropped unrelated patches
Philippe Mathieu-Daudé (8
Now that various VirtIO files don't use target specific
API anymore, we can move them to the system_ss[] source
set to build them once.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Manos Pitsidianakis
Reviewed-by: Pierrick Bouvier
---
hw/virtio/virtio-config-io.c | 1 -
hw/block/meson.b
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
---
include/qemu/target-info-impl.h | 4 +++-
target-info-stub.c | 1 +
target-info.c | 9 +++--
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/
Check endianness at runtime to remove the target-specific
TARGET_BIG_ENDIAN definition. Use cpu_to_[be,le]XX() from
"qemu/bswap.h" instead of tswapXX() from "exec/tswap.h".
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/gdbstub/helpers.h | 48 +
target_endian_mode() returns the default endianness (QAPI type)
of a target.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Richard Henderson
---
include/qemu/target-info-impl.h | 2 ++
include/qemu/target-info-qapi.h | 8
target-info-stub.c
To keep "qemu/target-info.h" self-contained to native
types, declare target_arch() -- which returns a QAPI
type -- in "qemu/target-info-qapi.h".
No logical change.
Keeping native types in "qemu/target-info.h" is necessary
to keep building tests such tests/tcg/plugins/mem.c, as
per the comment add
On 8/7/25 22:51, Philippe Mathieu-Daudé wrote:
On 8/7/25 19:39, Richard Henderson wrote:
On 7/8/25 11:19, Philippe Mathieu-Daudé wrote:
-/**
- * target_big_endian:
- * Returns true if the (default) endianness of the target is big
endian,
- * false otherwise. Common code should normally never n
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
target/arm/arm-qmp-cmds.c | 3 ++-
target/loongarch/loongarch-qmp-cmds.c | 3 ++-
target/mips/system/mips-qmp-cmds.c| 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
d
On Tue, Jul 08, 2025 at 04:40:51PM +0100, Shameer Kolothum wrote:
> Allow cold-plugging of an SMMUv3 device on the virt machine when no
> global (legacy) SMMUv3 is present or when a virtio-iommu is specified.
>
> This user-created SMMUv3 device is tied to a specific PCI bus provided
> by the user,
On Tue, Jul 08, 2025 at 04:40:50PM +0100, Shameer Kolothum wrote:
> @@ -2909,6 +2909,19 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice
> *dev,
> }
> }
>
> +/*
> + * When multiple PCI Express Root Buses are defined using pxb-pcie,
> + * the I
On 8/7/25 19:36, Richard Henderson wrote:
On 7/8/25 11:19, Philippe Mathieu-Daudé wrote:
+/**
+ * target_endian_mode:
+ *
+ * Returns: QAPI EndianMode enum (i.e. ENDIAN_MODE_LITTLE).
s/i.e./e.g./
TIL i.e. vs e.g. :)
Otherwise,
Reviewed-by: Richard Henderson
r~
On 12/5/25 15:47, Steve Sistare wrote:
Add a unit test for qom-tree-get
Signed-off-by: Steve Sistare
---
tests/qtest/qom-test.c | 49 +
1 file changed, 49 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
Steven Sistare writes:
> On 7/4/2025 8:22 AM, Markus Armbruster wrote:
>> Steve Sistare writes:
>>
>>> Define the qom-tree-get QAPI command, which fetches an entire tree of
>>> properties and values with a single QAPI call. This is much faster
>>> than using qom-list plus qom-get for every nod
"Michael S. Tsirkin" writes:
> On Mon, Jul 07, 2025 at 07:19:54PM +0200, Philippe Mathieu-Daudé wrote:
>> Rather than re-spinning the whole "single-binary: Make hw/arm/
>> common" series, restrict to the API additions, but include
>> examples of their usefulness (hundreds of virtio objects
>> rem
Steven Sistare writes:
> On 7/4/2025 8:22 AM, Markus Armbruster wrote:
>> Steve Sistare writes:
>>
>>> Define the qom-list-getv command, which fetches all the properties and
>>> values for a list of paths. This is faster than qom-tree-get when
>>> fetching a subset of the QOM tree. See qom.js
On Tue, Jul 08, 2025 at 04:40:45PM +0100, Shameer Kolothum wrote:
> @@ -937,11 +939,32 @@ static void smmu_base_realize(DeviceState *dev, Error
> **errp)
> g_free, g_free);
> s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL);
Although this is not i
On 7/8/25 2:53 AM, Alex Bennée wrote:
Yodel Eldar writes:
This patch adds TCG plugin register tracking support for the Alpha
target and resolves gitlab issue #2569:
https://gitlab.com/qemu-project/qemu/-/issues/2569
As mentioned in the bug report by Alex Bennée, the register list is
bu
These boards ship with a bundled DTB, and dtc will be required for generating
these from device tree sources. Prepare for that by adding an FDT dependency.
Signed-off-by: Bernhard Beschow
---
hw/microblaze/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/microbl
On 8/7/25 19:39, Richard Henderson wrote:
On 7/8/25 11:19, Philippe Mathieu-Daudé wrote:
-/**
- * target_big_endian:
- * Returns true if the (default) endianness of the target is big endian,
- * false otherwise. Common code should normally never need to know
about the
- * endianness of the targ
We don't generally like DPRINTF debug macros, preferring tracepoints.
In this case the macro is used in only three places (reset, realize,
and in the unlikely event the host kernel doesn't have GICv3 register
access support). These don't seem worth converting to tracepoints,
so simply delete the ma
This series removes the bundled device tree blobs from the repository which are
redundant to the bundled device tree sources. To make this work, the device tree
compiler 'dtc' is now required whenever libfdt is used. Furthermore, dtc can now
be built from the bundled libfdt if needed.
v2:
* Allow
The next patch relies on dtc for boards with a bundled DTB. These boards
depend on libfdt already. Make sure that there is a dtc iff libfdt is used
such that the DTBs can be generated.
Co-developed-by: Paolo Bonzini
Signed-off-by: Bernhard Beschow
---
meson.build
On 8/7/25 10:58, Philippe Mathieu-Daudé wrote:
Commit f5fd677ae7c ("win32/socket: introduce qemu_socket_select()
helper") included the "qemu/typedefs.h" header for the Error type,
but files including "system/os-win32.h" should already include
"qemu/osdep.h", and thus "qemu/typedefs.h".
Signed-of
On Tue, Jul 08, 2025 at 08:57:37AM +, Shameerali Kolothum Thodi wrote:
> > Thank you for the effort and the work here.
> >
> > A separate topic: do you have any preparation for the vIOMMU uAPI
> > patches (iommufd backends) in QEMU?
> >
> > I think it should be the next step after this series
On 7/7/25 21:30, Volker Rümelin wrote:
Change the block structure according to the QEMU Coding Style
documentation.
Signed-off-by: Volker Rümelin
---
hw/audio/sb16.c | 57 +
1 file changed, 20 insertions(+), 37 deletions(-)
Reviewed-by: Phili
Hi, recently there was some discussion and debate over what versions
of which things in the Python ecosystem we need to support with
regards to our build platform promise. I don't address those issues in
this mail at all. O:-)
In researching that problem, I created a CLI script to automatically
po
The GICD_TYPER2 register is new for GICv4.1. As an ID register, we
migrate it so that on the destination the kernel can check that the
destination supports the same configuration that the source system
had. This avoids confusing behaviour if the user tries to migrate a
VM from a GICv3 system to a
Ping
It would be nice to have all CSRs for 'info registers' for the next release.
We have one week before the freeze :D
Thanks,
Daniel
On 6/23/25 2:21 PM, Daniel Henrique Barboza wrote:
Hi,
The output of HMP 'info registers', implemented by the cpu_dump_state
callback, returns way less CSRs
On 7/7/25 19:09, Philippe Mathieu-Daudé wrote:
"qemu/typedefs.h" is already included by "qemu/osdep.h".
Signed-off-by: Philippe Mathieu-Daudé
---
hw/vfio/vfio-migration-internal.h | 1 -
include/system/os-win32.h | 1 -
hw/intc/loongarch_extioi_kvm.c| 1 -
3 files changed, 3 de
Now that the existance of a device tree compiler is enusred, it is possible to
always generate the DTBs from sources. This avoids checked in DTBs to become
inconsistent with their sources.
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 2 +-
pc-bios/dtb/bamboo.dtb
On 12/5/25 15:47, Steve Sistare wrote:
Define the qom-tree-get QAPI command, which fetches an entire tree of
properties and values with a single QAPI call. This is much faster
than using qom-list plus qom-get for every node and property of the
tree. See qom.json for details.
Signed-off-by: Ste
v2: Split as 1 patch per MAINTAINERS section.
Philippe Mathieu-Daudé (3):
hw/intc/loongarch_extioi: Remove unnecessary 'qemu/typedefs.h' include
hw/vfio/vfio-migration: Remove unnecessary 'qemu/typedefs.h' include
system/os-win32: Remove unnecessary 'qemu/typedefs.h' include
hw/vfio/vfio-m
Rustc v1.88 ships with a new lint `unnecessary_transmutes` which triggers the
following error when compiling code generated by bindgen:
error: unnecessary transmute
--> rust/qemu-api/libqemu_api.rlib.p/structured/bindings.inc.rs:792:18
|
792 | unsafe { ::std::mem::transmute(
"qemu/typedefs.h" is already included by "qemu/osdep.h".
Signed-off-by: Philippe Mathieu-Daudé
---
hw/vfio/vfio-migration-internal.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/vfio/vfio-migration-internal.h
b/hw/vfio/vfio-migration-internal.h
index a8b456b239d..00e2badd889 100644
---
Add PCI device related code in the TYPE_HOTPLUG_HANDLER
implementation.
For a PCI device hotplug/hotunplug event, the code routes to
acpi_pcihp_device callbacks (pre_plug_cb, plug_cb, unplug_request_cb,
unplug_cb).
Signed-off-by: Eric Auger
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Camer
PCI device supports two request types, Requests-without-PASID and
Requests-with-PASID. Requests-without-PASID doesn't include a PASID TLP
prefix, IOMMU fetches rid_pasid from context entry and use it as IOMMU's
pasid to index pasid table.
So we need to translate between PCI's pasid and IOMMU's pas
On 08/07/2025 15.13, Jared Rossi wrote:
On 7/8/25 8:56 AM, Thomas Huth wrote:
From: Thomas Huth
Since we're linking the network booting code into the main firmware
binary nowadays, we can support the "loadparm" parameter now quite
easily for pxelinux.cfg config files that contain multiple en
From: Yi Liu
When either 'Set Root Table Pointer' or 'Translation Enable' bit is changed,
all pasid bindings on host side become stale and need to be updated.
Introduce a helper function vtd_replay_pasid_bindings_all() to go through all
pasid entries in all passthrough devices to update host sid
> -Original Message-
> From: Eric Auger
> Sent: Tuesday, July 8, 2025 10:47 AM
> To: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; imamm...@redhat
(Forgot to Cc Manos)
On 7/7/25 19:20, Philippe Mathieu-Daudé wrote:
Now than various VirtIO files don't use target specific
API anymore, we can move them to the system_ss[] source
set to build them once.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/virtio/virtio-config-io.c | 1 -
hw/block
From: Thomas Huth
Show a simple boot menu for pxelinux.cfg, too, if the user requested it.
Signed-off-by: Thomas Huth
---
pc-bios/s390-ccw/netmain.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/pc-bios/s390-ccw/netmain.c b/pc-bios/s390-ccw/netmain.c
index 4f7
Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and
SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx
ones.
Because the bits in these registers depend on other CPU features, and
only FEAT_MEC is supported at the moment, this commit only implements
the EMEC bits in
In order to simplify the next commit where s390_count_running_cpus()
is split out of s390_cpu_halt(), make its prototype public as a
preliminary step.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/s390x-internal.h | 1 +
target/s390x/cpu-system.c | 2 +-
2 files changed, 2 insertion
On 7/8/2025 3:14 AM, Philippe Mathieu-Daudé wrote:
On 12/5/25 15:47, Steve Sistare wrote:
Define the qom-tree-get QAPI command, which fetches an entire tree of
properties and values with a single QAPI call. This is much faster
than using qom-list plus qom-get for every node and property of the
On 7/4/25 12:26, Manos Pitsidianakis wrote:
We don't currently test our proc macros and it'd be nice to do so.
Usually this would be done with something like
https://crates.io/crates/trybuild which runs cargo and tries to compile
a test input, and checks for success/failure. However we cannot us
Allow cold-plugging of an SMMUv3 device on the virt machine when no
global (legacy) SMMUv3 is present or when a virtio-iommu is specified.
This user-created SMMUv3 device is tied to a specific PCI bus provided
by the user, so ensure the IOMMU ops are configured accordingly.
Due to current limitat
We don't implement the Debug Communications Channel (DCC), but
we do attempt to provide dummy versions of its system registers
so that software that tries to access them doesn't fall over.
However, we got the tx/rx register definitions wrong. These
should be:
AArch32:
DBGDTRTX p14 0 c0 c5 0
The tests to be added exercise both legacy(iommu=smmuv3) and new
-device arm-smmuv3,.. cases.
Reviewed-by: Jonathan Cameron
Reviewed-by: Eric Auger
Tested-by: Eric Auger
Signed-off-by: Shameer Kolothum
---
tests/data/acpi/aarch64/virt/DSDT.smmuv3-dev| 0
tests/data/acpi/aarch64/virt/DSDT.
From: Thomas Huth
Check the various ways of booting a kernel via pxelinux.cfg file,
e.g. by specifying the config file name via the MAC address or the
UUID of the guest. Also check whether we can successfully load an
alternate kernel via the "loadparm" parameter here and whether the
boot menu sho
On 7/7/25 19:19, Philippe Mathieu-Daudé wrote:
Rather than re-spinning the whole "single-binary: Make hw/arm/
common" series, restrict to the API additions, but include
examples of their usefulness (hundreds of virtio objects
removed from default Linux build).
Time passed since I context-switched
We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra
root complexes to be associated with SMMU.
Although this change does not affect functionality at present, it is
required when we add support for user-creatable SMMUv3 devices in
future patches.
Note: Added a specific check to
On 7/8/25 10:19 AM, Philippe Mathieu-Daudé wrote:
To keep "qemu/target-info.h" self-contained to native
types, declare target_arch() -- which returns a QAPI
type -- in "qemu/target-info-qapi.h".
No logical change.
Keeping native types in "qemu/target-info.h" is necessary
to keep building tests
On 7/8/25 10:19 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/arm-qmp-cmds.c | 3 ++-
target/loongarch/loongarch-qmp-cmds.c | 3 ++-
target/mips/system/mips-qmp-cmds.c| 3 ++-
3 files changed, 6 inserti
Reviewed-by: Manos Pitsidianakis
On Tue, Jul 8, 2025 at 1:17 PM Philippe Mathieu-Daudé wrote:
>
> (Forgot to Cc Manos)
>
> On 7/7/25 19:20, Philippe Mathieu-Daudé wrote:
> > Now than various VirtIO files don't use target specific
> > API anymore, we can move them to the system_ss[] source
> > se
When bypass_ro is true, read only memory section is bypassed from
mapping in the container.
This is a preparing patch to workaround Intel ERRATA_772415.
Signed-off-by: Zhenzhong Duan
---
hw/vfio/listener.c| 13 +
include/hw/vfio/vfio-container-base.h | 1 +
2 fi
Restrict "exec/tswap.h" to the tswap*() methods,
move the load/store helpers with the other ones
declared in "qemu/bswap.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/tswap.h | 70 --
include/qemu/bswap.h | 73 +
Currently we don't support nested translation for passthrough device with
emulated device under same PCI bridge, because they require different address
space when x-flts=on.
In theory, we do support if devices under same PCI bridge are all passthrough
devices. But emulated device can be hotplugged
From: Gustavo Romero
This commit adds DSDT blobs to the whilelist in the prospect to
allow changes in the GPEX _OSC method.
Signed-off-by: Gustavo Romero
Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
Acked-by: Igor Mammedov
---
v3 -> v4:
- add missed tests/data/acpi/riscv64/virt/D
Hi Eric,
> -Original Message-
> From: Eric Auger
> Sent: Tuesday, July 8, 2025 8:41 AM
> To: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.com;
> ddut...@redhat.com; berra...@redhat.com; imamm...
On Tue, Jul 08, 2025 at 09:28:28AM +0200, Markus Armbruster wrote:
> Use the conventional "- If " phrasing, optionally
> with ", ".
>
> Signed-off-by: Markus Armbruster
> ---
> qapi/misc-i386.json | 7 +++
> qapi/qom.json | 4 ++--
> 2 files changed, 5 insertions(+), 6 deletions(-)
Re
On Mon, Jul 07, 2025 at 01:19:03PM +0100, Alireza Sanaee via wrote:
> Date: Mon, 7 Jul 2025 13:19:03 +0100
> From: Alireza Sanaee via
> Subject: [PATCH v14 2/7] hw/core/machine: topology functions capabilities
> added
> X-Mailer: git-send-email 2.34.1
>
> Add two functions one of which finds the
Hi,
For passthrough device with intel_iommu.x-flts=on, we don't do shadowing of
guest page table for passthrough device but pass stage-1 page table to host
side to construct a nested domain. There was some effort to enable this feature
in old days, see [1] for details.
The key design is to utiliz
Queued, thanks.
Paolo
Now that arm,virt can have user-creatable smmuv3 devices, document it.
Reviewed-by: Jonathan Cameron
Reviewed-by: Eric Auger
Tested-by: Eric Auger
Signed-off-by: Shameer Kolothum
---
qemu-options.hx | 7 +++
1 file changed, 7 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
i
Jonah Palmer writes:
> On 7/4/25 11:00 AM, Markus Armbruster wrote:
>> Jonah Palmer writes:
[...]
>> So, total time increases: early pinning (before main loop) takes more
>> time than we save pinning (in the main loop). Correct?
>
> Correct. We only save ~0.07s from the pinning that happens i
Let pass the root bus to ich9 and piix4 through a property link
instead of through an argument passed to acpi_pcihp_init().
Also make sure the root bus is set at the entry of acpi_pcihp_init().
The rationale of that change is to be consistent with the forecoming ARM
implementation where the machi
Am 30. Juni 2025 21:03:06 UTC schrieb Peter Maydell :
>On Mon, 30 Jun 2025 at 21:22, Bernhard Beschow wrote:
>>
>>
>>
>> Am 30. Juni 2025 09:09:31 UTC schrieb Peter Maydell
>> :
>> >On Sun, 29 Jun 2025 at 21:49, Bernhard Beschow wrote:
>> >>
>> >> Allows the imx8mp-evk machine to be run with
Introduce a new struct AcpiIortSMMUv3Dev to hold all the information
required for SMMUv3 IORT node and use that for populating the node.
The current machine wide SMMUv3 is named as legacy SMMUv3 as we will
soon add support for user-creatable SMMUv3 devices. These changes will
be useful to have com
For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes,
one of which has bypass_iommu enabled. The generated IORT table contains
a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node.
RC node features 4 ID mappings, of which 2 points to SMMU node and the
remaining ones poin
On Thu, Jul 03, 2025 at 04:58:12PM +0300, Manos Pitsidianakis wrote:
> Date: Thu, 03 Jul 2025 16:58:12 +0300
> From: Manos Pitsidianakis
> Subject: [PATCH 2/3] memattrs.h: make MemTxAttrs into enum
> X-Mailer: b4 0.14.2
>
> Convert MemTxResult defines into an enum. This will allow bindgen to
> ge
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