Re: [PATCH] target/riscv: Fix pmp range wraparound on zero

On Sun, Jul 6, 2025 at 11:04 PM Vac Chen wrote: > > pmp_is_in_range() prefers to match addresses within the interval > [start, end]. To archieve this, pmpaddrX is decremented during the end > address update. > > In TOR mode, a rule is ignored if its start address is greater than or > equal to its

Re: [PATCH] target/riscv: Fix pmp range wraparound on zero

On Sun, Jul 6, 2025 at 11:04 PM Vac Chen wrote: > > pmp_is_in_range() prefers to match addresses within the interval > [start, end]. To archieve this, pmpaddrX is decremented during the end > address update. > > In TOR mode, a rule is ignored if its start address is greater than or > equal to its

Re: [PATCH-for-10.1 v6 12/14] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine

On 7/7/25 11:20, Philippe Mathieu-Daudé wrote: When we'll start to use target_machine_typename() to filter machines for the ARM/Aarch64 binaries, the 'none' machine would be filtered out. Register the proper interfaces to keep it available. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pie

Re: [PATCH-for-10.1 v6 10/14] hw/core/null-machine: Define machine as generic QOM type

On 7/7/25 11:20, Philippe Mathieu-Daudé wrote: While DEFINE_MACHINE() is a succinct macro, it doesn't allow registering QOM interfaces to the defined machine. Convert to the generic DEFINE_TYPES() in preparation to register interfaces. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick

Re: [PATCH] tests/functional/test_ppc_bamboo: Replace broken link with working assets

On 7/7/25 20:47, Thomas Huth wrote: From: Thomas Huth The old image that we used for testing the bamboo machine has disappeared from the internet. Fortunately there is another kernel + initrd provided by Cédric that can be used for testing this machine, too. Reported-by: Stefan Hajnoczi Sugge

Re: Bamboo ppc Linux image URL is 404

On 7/7/25 20:55, Thomas Huth wrote: On 07/07/2025 19.35, Cédric Le Goater wrote: Hello Thomas, On 7/7/25 19:07, Thomas Huth wrote: On 07/07/2025 16.13, Stefan Hajnoczi wrote: Hi Thomas, The following URL is 404 and is causing the functional-system-fedora CI job to fail: qemu_test.asset.Asset

[PATCH 1/1] qemu-img: add sub-command --remove-all to 'qemu-img bitmap'

>From time to time it is needed to remove all bitmaps from the image. Before this patch the process is not very convinient. One should perform qemu-img info and parse the output to obtain all names. After that one should sequentially call qemu-img bitmap --remove for each present bitmap. T

[PATCH 18/20] target/arm: Convert do_ats_write to access_perm

Signed-off-by: Richard Henderson --- target/arm/tcg/cpregs-at.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index e79866e651..39141c83aa 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cp

[PATCH 20/20] target/arm: Implement FEAT_ATS1A

Implement FEAT_ATS1A and enable for -cpu max. Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpu-features.h | 5 target/arm/tcg/cpregs-at.c| 44 +++ target/arm/tcg/cpu64.c| 1 + docs/system/arm/emulatio

[PATCH 16/20] target/arm: Introduce get_phys_addr_for_at

Rename get_phys_addr_with_space_nogpc for its only caller, do_ats_write. Drop the MemOp memop argument as it doesn't make sense in the new context. Signed-off-by: Richard Henderson --- target/arm/internals.h | 17 +++-- target/arm/ptw.c | 17 ++--- target/a

[PATCH 14/20] target/arm: Convert get_phys_addr to access_perm

Complete the conversion of all routines in ptw.c from MMUAccessType access_type to an access_perm bitmask. Signed-off-by: Richard Henderson --- target/arm/internals.h| 4 ++-- target/arm/ptw.c | 4 ++-- target/arm/tcg/m_helper.c | 8 3 files changed, 8 insertions(+), 8 dele

[PATCH 13/20] target/arm: Convert get_phys_addr_with_space_nogpc to access_perm

Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 ++-- target/arm/ptw.c | 4 ++-- target/arm/tcg/cpregs-at.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1781943fac..20b49201cb 100644 ---

[PATCH 12/20] target/arm: Convert get_phys_addr_gpc to access_perm

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fef9e9a7cb..adc681da41 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -80,7 +80,7 @@ static bool get_phys_addr_

[PATCH 06/20] target/arm: Convert pmsav8_mpu_lookup to access_perm

Signed-off-by: Richard Henderson --- target/arm/internals.h| 2 +- target/arm/ptw.c | 6 +++--- target/arm/tcg/m_helper.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index c4765e4489..629aa7bc23 100644 --- a/t

[PATCH 11/20] target/arm: Convert get_phys_addr_nogpc to access_perm

Because of the recursion with get_phys_addr_twostage, we must convert the two functions at the same time. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 39 --- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/target/

[PATCH 19/20] target/arm: Fill in HFGITR_EL2 bits for Arm v9.5

Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c9506aa6d5..88b3d63424 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -512,6 +512,11 @@ FIELD(HFGITR_EL2, SVC_EL1, 53, 1

[PATCH 17/20] target/arm: Skip AF and DB updates for AccessType_AT

We are required to skip DB update for AT instructions, and we are allowed to skip AF updates. Choose to skip both. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1

[PATCH 07/20] target/arm: Convert v8m_is_sau_exempt to access_perm

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a11df31b18..78a9c21fab 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2754,14 +2754,14 @@ bool pmsav8_mpu_lookup(CPUA

[PATCH 09/20] target/arm: Convert get_phys_addr_pmsav8 to access_perm

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 709dfa2684..f1edbbee5b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2881,7 +2881,7 @@ void v8m_security_lookup

[PATCH 08/20] target/arm: Convert v8m_security_lookup to access_perm

Signed-off-by: Richard Henderson --- target/arm/internals.h| 2 +- target/arm/ptw.c | 8 target/arm/tcg/m_helper.c | 7 +++ 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 629aa7bc23..1781943fac 100644

[PATCH 03/20] target/arm: Convert get_phys_addr_lpae to access_perm

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 39ecc093a5..7503d1de6f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1643,14 +1643,14 @@ static bool nv_nv1_e

[PATCH 02/20] target/arm: Convert get_phys_addr_v6 to access_perm

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 760387b4da..39ecc093a5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1103,7 +1103,7 @@ do_fault: } static bool g

[PATCH 04/20] target/arm: Convert get_phys_addr_pmsav5 to access_perm

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7503d1de6f..adceeabfe4 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2182,7 +2182,7 @@ static bool get_phys_addr_lpa

[PATCH 01/20] target/arm: Convert get_phys_addr_v5 to access_perm

Begin conversion of get_phys_addr and all subroutines from MMUAccessType to a mask of required permissions. Notably, access_perm may be 0 in order to disable the permissions check. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH 15/20] target/arm: Skip permission check from arm_cpu_get_phys_page_attrs_debug

Do not require read permission when translating addresses for debugging purposes. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fe005622da..c1fe53965c 100644 --- a/target/arm/ptw

[PATCH 10/20] target/arm: Convert get_phys_addr_disabled to access_perm

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f1edbbee5b..5b8040a174 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3193,7 +3193,7 @@ static ARMCacheAttrs com

[PATCH 05/20] target/arm: Convert get_phys_addr_pmsav7 to access_perm

Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index adceeabfe4..b71c963f67 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2350,7 +2350,7 @@ static bool pmsav7_use_backgr

[PATCH 00/20] target/arm: Implement FEAT_ATS1A

Based-on: 20250707151547.196393-1-richard.hender...@linaro.org ("[PATCH 0/3] target/arm: Split out AT and PMU cpregs") (1) Lots of tiny cleanups allowing the permission check to be skipped. (2) Skip the permission check for gdbstub. (3) A fix for existing AT instructions in that hw should not upda

Re: [PATCH-for-10.1 v6 02/14] qemu/target-info: Factor target_arch() out

On 7/7/25 11:19, Philippe Mathieu-Daudé wrote: To keep "qemu/target-info.h" self-contained to native types, declare target_arch() -- which returns a QAPI type -- in "qemu/target-info-qapi.h". No logical change. Keeping native types in "qemu/target-info.h" is necessary to keep building tests suc

Re: [PATCH-for-10.1 v6 01/14] target/qmp: Use target_cpu_type()

On 7/7/25 11:19, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- target/arm/arm-qmp-cmds.c | 3 ++- target/loongarch/loongarch-qmp-cmds.c | 3 ++- target/mips/system/mips-qmp-cmds.c| 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) Reviewed-by

Re: [PATCH] i386/cpu: ARCH_CAPABILITIES should not be advertised on AMD

On Mon, Jul 07, 2025, Daniel P. Berrangé wrote: > On Tue, Jul 01, 2025 at 03:59:12PM -0400, Konrad Rzeszutek Wilk wrote: > > ..snip.. > > > OK, back to the original question "what should the code do?" > > > > > > My answer is, it can behave with any of below option: > > > > > > - Be vendor agnost

Re: [PATCH] i386/cpu: ARCH_CAPABILITIES should not be advertised on AMD

On Wed, Jul 02, 2025, Igor Mammedov wrote: > Or even better a single KVM optin feature > 'do_not_advertise_features_not_supported_by_host_cpu', > and then QEMU could use that for disabling all nonsense in one go. > Plus all of that won't be breaking KVM ABI nor qemu had to add fixups for > this a

Re: [PATCH 2/2] target/s390x/tcg: Use vaddr in s390_probe_access()

On 7/7/25 11:10, Philippe Mathieu-Daudé wrote: Commit 70ebd9ce1cb ("s390x/tcg: Fault-safe memset") passed vaddr type to access_prepare(), and commit b6c636f2cd6 ("s390x/tcg: Fault-safe memmove") to do_access_get_byte(), but declared S390Access::vaddr[1,2] as target_ulong. Directly declare these a

Re: [PATCH 1/2] target/s390x/kvm: Use vaddr in find/insert_hw_breakpoint()

On 7/7/25 11:10, Philippe Mathieu-Daudé wrote: Since commit b8a6eb1862a both kvm_arch_insert_hw_breakpoint() and kvm_arch_remove_hw_breakpoint() use a vaddr type. Use the same type for the callees. Fixes: b8a6eb1862a ("sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint") Signed-of

Re: [PATCH] i386/cpu: ARCH_CAPABILITIES should not be advertised on AMD

On Tue, Jul 01, 2025 at 11:25:36AM +0200, Maciej S. Szmigiero wrote: > On 1.07.2025 10:23, Xiaoyao Li wrote: > > On 6/30/2025 9:30 PM, Alexandre Chartre wrote: > > > KVM emulates the ARCH_CAPABILITIES on x86 for both Intel and AMD > > > cpus, although the IA32_ARCH_CAPABILITIES MSR is an Intel-spec

Re: [PATCH] i386/cpu: ARCH_CAPABILITIES should not be advertised on AMD

On Tue, Jul 01, 2025 at 03:59:12PM -0400, Konrad Rzeszutek Wilk wrote: > ..snip.. > > OK, back to the original question "what should the code do?" > > > > My answer is, it can behave with any of below option: > > > > - Be vendor agnostic and stick to x86 architecture. If CPUID enumerates a > > fe

[PATCH 2/3] hw/audio/sb16: improve DMA handling

The Soundblaster 16 audio device is strange and works differently compared to the other audio frontends. For audio playback, a BH routine copies the audio samples from the DMA buffer to the audio backend. The BH routine then immediately reschedules itself. As far fewer samples are required from the

[PATCH 3/3] hw/audio/sb16: block structure coding style fixes

Change the block structure according to the QEMU Coding Style documentation. Signed-off-by: Volker Rümelin --- hw/audio/sb16.c | 57 + 1 file changed, 20 insertions(+), 37 deletions(-) diff --git a/hw/audio/sb16.c b/hw/audio/sb16.c index 714144eb6

[PATCH 1/3] hw/audio/sb16: introduce DMA helper functions

Introduce the hold_DREQ() and release_DREQ() functions to ease the review of the next patch. Signed-off-by: Volker Rümelin --- hw/audio/sb16.c | 27 +-- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/audio/sb16.c b/hw/audio/sb16.c index bac64118fe..5c51

[PATCH 0/3] hw/audio/sb16: reduce the CPU load

Three patches for the Sound Blaster 16 emulation. Patch 2/3 "improve DMA handling" reduces the CPU load and fixes issue #469 at https://gitlab.com/qemu-project/qemu/-/issues/469. Don't forget to add the AdLib device to the QEMU command line if you want to test the patches. The OPL2 chip is part o

Re: [PATCH] i386/cpu: ARCH_CAPABILITIES should not be advertised on AMD

On Wed, Jul 02, 2025, Zhao Liu wrote: > > I think we need firstly aligned on what the behavior of the Windows that hit > > "unsupported processor" is. > > > > My understanding is, the Windows is doing something like > > > > if (is_AMD && CPUID(arch_capabilities)) > > error(unsuppo

Re: [PATCH 2/2] hw/intc/arm_gicv3_kvm: Migrate GICD_TYPER2

On Mon, 7 Jul 2025 at 18:31, Peter Maydell wrote: > > On Mon, 7 Jul 2025 at 18:25, Eric Auger wrote: > > > > Hi Peter, > > > > On 7/7/25 6:10 PM, Peter Maydell wrote: > > > The GICD_TYPER2 register is new for GICv4.1. As an ID register, we > > > migrate it so that on the destination the kernel c

Re: [PATCH] i386/cpu: ARCH_CAPABILITIES should not be advertised on AMD

On Tue, Jul 01, 2025, Konrad Rzeszutek Wilk wrote: > On Tue, Jul 01, 2025 at 03:05:00PM +0200, Igor Mammedov wrote: > > On Tue, 1 Jul 2025 20:36:43 +0800 > > Zhao Liu wrote: > > > > > On Tue, Jul 01, 2025 at 07:12:44PM +0800, Xiaoyao Li wrote: > > > > Date: Tue, 1 Jul 2025 19:12:44 +0800 > > > >

Re: Bamboo ppc Linux image URL is 404

On 07/07/2025 19.35, Cédric Le Goater wrote: Hello Thomas, On 7/7/25 19:07, Thomas Huth wrote: On 07/07/2025 16.13, Stefan Hajnoczi wrote: Hi Thomas, The following URL is 404 and is causing the functional-system-fedora CI job to fail: qemu_test.asset.AssetError: http://landley.net/aboriginal/

[PATCH] tests/functional/test_ppc_bamboo: Replace broken link with working assets

From: Thomas Huth The old image that we used for testing the bamboo machine has disappeared from the internet. Fortunately there is another kernel + initrd provided by Cédric that can be used for testing this machine, too. Reported-by: Stefan Hajnoczi Suggested-by: Cédric Le Goater Signed-off-

Re: [RFC PATCH-for-10.1 v6 00/14] target-info: Add more API for VirtIO cleanups & introduce ARM macros

On Mon, Jul 07, 2025 at 07:19:54PM +0200, Philippe Mathieu-Daudé wrote: > Rather than re-spinning the whole "single-binary: Make hw/arm/ > common" series, restrict to the API additions, but include > examples of their usefulness (hundreds of virtio objects > removed from default Linux build). > Tim

Re: [PATCH v5 00/36] ACPI PCI Hotplug support on ARM

On Mon, Jul 07, 2025 at 07:09:34PM +0200, Eric Auger wrote: > Hi, > > On 7/3/25 2:35 PM, Eric Auger wrote: > > This series enables ACPI PCI hotplug/hotunplug on ARM. > > It is not enabled by default and ACPI PCI hotplug can > > be selected by setting: > > > > -global acpi-ged.acpi-pci-hotplug-with

Re: Bamboo ppc Linux image URL is 404

Hello Thomas, On 7/7/25 19:07, Thomas Huth wrote: On 07/07/2025 16.13, Stefan Hajnoczi wrote: Hi Thomas, The following URL is 404 and is causing the functional-system-fedora CI job to fail: qemu_test.asset.AssetError: http://landley.net/aboriginal/downloads/binaries/system-image-powerpc-440fp.

Re: [PATCH 2/2] hw/intc/arm_gicv3_kvm: Migrate GICD_TYPER2

On Mon, 7 Jul 2025 at 18:25, Eric Auger wrote: > > Hi Peter, > > On 7/7/25 6:10 PM, Peter Maydell wrote: > > The GICD_TYPER2 register is new for GICv4.1. As an ID register, we > > migrate it so that on the destination the kernel can check that the > > destination supports the same configuration t

[PATCH-for-10.1 v6 11/14] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces

Define the TYPE_TARGET_ARM_MACHINE and TYPE_TARGET_AARCH64_MACHINE QOM interface names to allow machines to implement them. Register these interfaces in common code in target_info-qom.c used by all binaries because QOM interfaces must be registered before being checked (see next commit with the 'n

[PATCH-for-10.1 v6 10/14] hw/core/null-machine: Define machine as generic QOM type

While DEFINE_MACHINE() is a succinct macro, it doesn't allow registering QOM interfaces to the defined machine. Convert to the generic DEFINE_TYPES() in preparation to register interfaces. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/core/null-machine.c | 14 ++

[PATCH-for-10.1 v6 01/14] target/qmp: Use target_cpu_type()

Signed-off-by: Philippe Mathieu-Daudé --- target/arm/arm-qmp-cmds.c | 3 ++- target/loongarch/loongarch-qmp-cmds.c | 3 ++- target/mips/system/mips-qmp-cmds.c| 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds

[RFC PATCH-for-10.1 v6 14/14] hw/arm: Add DEFINE_MACHINE_[ARM_]AARCH64() macros

A machine defined with the DEFINE_MACHINE_ARM_AARCH64() macro will be available on qemu-system-arm and qemu-system-aarch64 binaries. One defined with DEFINE_MACHINE_AARCH64() will only be available in the qemu-system-aarch64 binary. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/machi

[PATCH-for-10.1 v6 09/14] hw/virtio: Build various files once

Now than various VirtIO files don't use target specific API anymore, we can move them to the system_ss[] source set to build them once. Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-config-io.c | 1 - hw/block/meson.build | 6 -- hw/virtio/meson.build| 20 +

Re: [PATCH 2/2] hw/intc/arm_gicv3_kvm: Migrate GICD_TYPER2

Hi Peter, On 7/7/25 6:10 PM, Peter Maydell wrote: > The GICD_TYPER2 register is new for GICv4.1. As an ID register, we > migrate it so that on the destination the kernel can check that the > destination supports the same configuration that the source system > had. This avoids confusing behaviour

[RFC PATCH-for-10.1 v6 00/14] target-info: Add more API for VirtIO cleanups & introduce ARM macros

Rather than re-spinning the whole "single-binary: Make hw/arm/ common" series, restrict to the API additions, but include examples of their usefulness (hundreds of virtio objects removed from default Linux build). Time passed since I context-switched out of this work so I'm not sure the DEFINE_MACH

Re: [RFC PATCH-for-10.1 v6 08/14] qemu: Declare all load/store helpert in 'qemu/bswap.h'

On 7/7/25 19:20, Philippe Mathieu-Daudé wrote: Oops typo "helper" in subject. Restrict "exec/tswap.h" to the tswap*() methods, move the load/store helpers with the other ones declared in "qemu/bswap.h". Signed-off-by: Philippe Mathieu-Daudé --- include/exec/tswap.h | 70

[PATCH-for-10.1 v6 13/14] hw/boards: Introduce DEFINE_MACHINE_WITH_INTERFACES() macro

DEFINE_MACHINE_WITH_INTERFACES() is similar to DEFINE_MACHINE() but allows to pass a InterfaceInfo[] pointer. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/hw/boards.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h

[RFC PATCH-for-10.1 v6 08/14] qemu: Declare all load/store helpert in 'qemu/bswap.h'

Restrict "exec/tswap.h" to the tswap*() methods, move the load/store helpers with the other ones declared in "qemu/bswap.h". Signed-off-by: Philippe Mathieu-Daudé --- include/exec/tswap.h | 70 -- include/qemu/bswap.h | 73 +

[PATCH-for-10.1 v6 07/14] gdbstub/helpers: Replace TARGET_BIG_ENDIAN -> target_big_endian()

Check endianness at runtime to remove the target-specific TARGET_BIG_ENDIAN definition. Signed-off-by: Philippe Mathieu-Daudé --- include/gdbstub/helpers.h | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h in

[PATCH-for-10.1 v6 06/14] qemu: Convert target_words_bigendian() to TargetInfo API

Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé --- include/exec/tswap.h | 13 + include/qemu/target-info.h | 8 cpu-target.c | 7 --- hw/core/cpu-system.c | 2 +- hw/display/vga.c | 2 +- hw/virtio/virtio.c

[PATCH-for-10.1 v6 12/14] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine

When we'll start to use target_machine_typename() to filter machines for the ARM/Aarch64 binaries, the 'none' machine would be filtered out. Register the proper interfaces to keep it available. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- hw/core/null-machine.c | 6 ++

[PATCH-for-10.1 v6 05/14] qemu/target-info: Add target_endian_mode()

target_endian_mode() returns the default endianness (QAPI type) of a target. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/target-info-impl.h | 2 ++ include/qemu/target-info-qapi.h | 8 target-info-stub.c | 1 + target-info.c | 5 + 4 files c

[PATCH-for-10.1 v6 04/14] qemu/target-info: Introduce target_base_arch()

target_base_arch() returns the base architecture as in QEMU target/$arch/ path. For example, X86_64 is implemented in the target/i386/ so its QEMU base arch is 'i386'. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/target-info-impl.h | 2 ++ include/qemu/target-info-qapi.h | 7 +++

[PATCH-for-10.1 v6 03/14] qemu/target-info: Add %target_arch field to TargetInfo

Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/target-info-impl.h | 4 +++- target-info-stub.c | 1 + target-info.c | 9 +++-- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/qemu/target-info-impl.h

[PATCH-for-10.1 v6 02/14] qemu/target-info: Factor target_arch() out

To keep "qemu/target-info.h" self-contained to native types, declare target_arch() -- which returns a QAPI type -- in "qemu/target-info-qapi.h". No logical change. Keeping native types in "qemu/target-info.h" is necessary to keep building tests such tests/tcg/plugins/mem.c, as per the comment add

[PATCH 0/2] target/s390x: Few target_ulong -> vaddr replacements

Replace few 'target_ulong' by 'vaddr' in target/s390x/ (the other lefts aren't in my way, so I'm ignoring them). Philippe Mathieu-Daudé (2): target/s390x/kvm: Use vaddr in find/insert_hw_breakpoint() target/s390x/tcg: Use vaddr in s390_probe_access() target/s390x/kvm/kvm.c| 4 ++--

[PATCH 1/2] target/s390x/kvm: Use vaddr in find/insert_hw_breakpoint()

Since commit b8a6eb1862a both kvm_arch_insert_hw_breakpoint() and kvm_arch_remove_hw_breakpoint() use a vaddr type. Use the same type for the callees. Fixes: b8a6eb1862a ("sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint") Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/k

[PATCH 2/2] target/s390x/tcg: Use vaddr in s390_probe_access()

Commit 70ebd9ce1cb ("s390x/tcg: Fault-safe memset") passed vaddr type to access_prepare(), and commit b6c636f2cd6 ("s390x/tcg: Fault-safe memmove") to do_access_get_byte(), but declared S390Access::vaddr[1,2] as target_ulong. Directly declare these as vaddr type, and have s390_probe_access() use th

Re: Bamboo ppc Linux image URL is 404

On 07/07/2025 16.13, Stefan Hajnoczi wrote: Hi Thomas, The following URL is 404 and is causing the functional-system-fedora CI job to fail: qemu_test.asset.AssetError: http://landley.net/aboriginal/downloads/binaries/system-image-powerpc-440fp.tar.gz: Unable to download: HTTP error 404 https://

Re: [PATCH v5 00/36] ACPI PCI Hotplug support on ARM

Hi, On 7/3/25 2:35 PM, Eric Auger wrote: > This series enables ACPI PCI hotplug/hotunplug on ARM. > It is not enabled by default and ACPI PCI hotplug can > be selected by setting: > > -global acpi-ged.acpi-pci-hotplug-with-bridge-support=on > > Expected benefits should be similar to those listed i

[PATCH] bulk: Remove unnecessary 'qemu/typedefs.h' include

"qemu/typedefs.h" is already included by "qemu/osdep.h". Signed-off-by: Philippe Mathieu-Daudé --- hw/vfio/vfio-migration-internal.h | 1 - include/system/os-win32.h | 1 - hw/intc/loongarch_extioi_kvm.c| 1 - 3 files changed, 3 deletions(-) diff --git a/hw/vfio/vfio-migration-inter

Re: [PATCH v5 35/36] qtest/bios-tables-test: Generate reference blob for DSDT.hpoffacpiindex

Hi Jonathan, On 7/3/25 5:02 PM, Jonathan Cameron wrote: > On Thu, 3 Jul 2025 14:35:35 +0200 > Eric Auger wrote: > >> The disassembled DSDT table is given below > I'd suggest maybe a spot of cropping to bring this down to a reasonable > length. > See inline. Yup. I can do that. > > Otherwise LGT

[PATCH] Adds the GDB register XML files for Sparc and Sparc64.

From 6c116b968cb28bcc0d0236913f1926206f50a9b4 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 27 Jun 2025 04:51:25 -0500 Subject: [PATCH] Adds the GDB register XML files for Sparc and Sparc64. The xml files are copied from binutils-gdb. The `-core.xml` files are just assembled from the others

Re: [PATCH v2 09/19] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked

Hi Zhenzhong, On 7/7/25 5:12 AM, Duan, Zhenzhong wrote: > Hi Eric, > >> -Original Message- >> From: Duan, Zhenzhong >> Subject: RE: [PATCH v2 09/19] intel_iommu: Introduce two helpers >> vtd_as_from/to_iommu_pasid_locked >> >> >> >>> -Original Message- >>> From: Eric Auger >>> Sub

[PATCH v9 5/5] hw/arm/virt: Allow virt extensions with KVM

From: Haibo Xu Up to now virt support on guest has been only supported with TCG. Now it becomes feasible to use it with KVM acceleration. Check neither in-kernel GICv3 nor aarch64=off is used along with KVM EL2. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Rev

[PATCH v9 0/5] ARM Nested Virt Support

This is candidate for 10.1. For gaining virt functionality in KVM accelerated L1, The host needs to be booted with "kvm-arm.mode=nested" option and qemu needs to be invoked with: -machine virt,virtualization=on. This series can be found at: https://github.com/eauger/qemu/tree/v10.0.0-nv-v9 previo

[PATCH v9 3/5] target/arm: Enable feature ARM_FEATURE_EL2 if EL2 is supported

From: Haibo Xu KVM_CAP_ARM_EL2 must be supported by the cpu to enable ARM_FEATURE_EL2. In case the host does support NV, expose the feature. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Reviewed-by: Richard Henderson --- v2 -> v3: - check pmu->has_el2 on kvm_

[PATCH v9 1/5] hw/arm: Allow setting KVM vGIC maintenance IRQ

From: Haibo Xu Allow virt arm machine to set the interrupt ID for the KVM GIC maintenance interrupt. This setting must be done before the KVM_DEV_ARM_VGIC_CTRL_INIT hence the choice to perform the setting in the GICv3 realize instead of proceeding the same way as kvm_arm_pmu_set_irq(). Signed-o

[PATCH v9 2/5] target/arm/kvm: Add helper to detect EL2 when using KVM

From: Haibo Xu Introduce query support for KVM_CAP_ARM_EL2. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/kvm_arm.h | 7 +++ target/arm/kvm-stub.c | 5 + target/arm/kvm

[PATCH v9 4/5] hw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virt

We may be miss some NV related GIC register save/restore. Until we complete the study, let's add a migration blocker when the maintenance IRQ is set. Signed-off-by: Eric Auger Suggested-by: Peter Maydell --- hw/intc/arm_gicv3_kvm.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/

Re: [PATCH] hw/uefi: Create and use trace.h wrapper header

On 7/7/25 16:24, Peter Maydell wrote: The documentation of the trace subsystem (docs/devel/tracing.rst) says that each subdirectory which uses trace events should create a wrapper trace.h file which includes the trace/trace-foo.h generated header, and that .c files then #include "trace.h". We di

Re: [PATCH 1/2] hw/intc/arm_gicv3_dist: Implement GICD_TYPER2 as 0

On 7/7/25 6:10 PM, Peter Maydell wrote: > The GIC distributor registers GICD_TYPER2 is present when the > GICv4.1 is implemented, and RES0 otherwise. QEMU's TCG implementation > is only GICv4.0, so this register is RES0. However, since it's > reasonable for GICv4.1-aware software to read the reg

Re: [PATCH 3/3] target/arm: Split out performance monitor regs to cpregs-pmu.c

On 7/7/25 17:15, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/arm/cpregs.h |3 + target/arm/internals.h |2 + target/arm/cpregs-pmu.c | 1309 +++ target/arm/helper.c | 1287 +-

Re: [PATCH 1/3] target/arm: Drop stub for define_tlb_insn_regs

On 7/7/25 17:15, Richard Henderson wrote: Allow the call to be compiled out by protecting it with tcg_enabled. Signed-off-by: Richard Henderson --- target/arm/helper.c| 4 +++- target/arm/tcg-stubs.c | 5 - 2 files changed, 3 insertions(+), 6 deletions(-) Reviewed-by: Philippe Mat

[PATCH 0/2] hw/intc: handle GICD_TYPER2 for KVM GICv3

The GICD_TYPER2 GICv3 distributor register is one that is added for GICv4.1; previously this was architected as a RES0 location. Our TCG GIC doesn't implement GICv4.1, but for KVM the kernel might support it. This patchset: * makes GICD_TYPER0 reads not trigger a bad-read trace event on the TC

[PATCH 1/2] hw/intc/arm_gicv3_dist: Implement GICD_TYPER2 as 0

The GIC distributor registers GICD_TYPER2 is present when the GICv4.1 is implemented, and RES0 otherwise. QEMU's TCG implementation is only GICv4.0, so this register is RES0. However, since it's reasonable for GICv4.1-aware software to read the register, expecting the zero for GICv3 and GICv4.0, im

[PATCH 2/2] hw/intc/arm_gicv3_kvm: Migrate GICD_TYPER2

The GICD_TYPER2 register is new for GICv4.1. As an ID register, we migrate it so that on the destination the kernel can check that the destination supports the same configuration that the source system had. This avoids confusing behaviour if the user tries to migrate a VM from a GICv3 system to a

Re: [PATCH v7 4/4] hw/arm/virt: Allow virt extensions with KVM

On Mon, 7 Jul 2025 at 16:44, Marc Zyngier wrote: > > On Mon, 07 Jul 2025 15:46:04 +0100, > Peter Maydell wrote: > > Speaking of GIC ID registers, we never updated QEMU to > > handle the GICv4.1 GICD_TYPER2 register, so we don't try > > to send and sanity check that on migration at the moment. > >

Re: [PATCH v8 4/4] hw/arm/virt: Allow virt extensions with KVM

Hi Peter, On 7/7/25 3:29 PM, Peter Maydell wrote: > On Mon, 7 Jul 2025 at 14:16, Eric Auger wrote: >> From: Haibo Xu >> >> Up to now virt support on guest has been only supported with TCG. >> Now it becomes feasible to use it with KVM acceleration. >> >> Check neither in-kernel GICv3 nor aarch64

Re: [PATCH v7 4/4] hw/arm/virt: Allow virt extensions with KVM

On Mon, 07 Jul 2025 15:46:04 +0100, Peter Maydell wrote: > > On Mon, 7 Jul 2025 at 15:32, Marc Zyngier wrote: > > > > On Mon, 07 Jul 2025 10:53:38 +0100, > > Peter Maydell wrote: > > > > > > On Mon, 7 Jul 2025 at 10:30, Eric Auger wrote: > > > > > > > > Hi Peter, Marc, > > > > > > > > On 7/4/2

Re: [Regression] Re: [PULL 35/35] qom: reverse order of instance_post_init calls

Il gio 3 lug 2025, 06:51 Paolo Bonzini ha scritto: > > > Il mer 2 lug 2025, 23:36 Xiaoyao Li ha scritto: > >> The reason why accelerator's instance_init() was moved to post_init, was >> just it needs to consider other factors. Please see commit 4db4385a7ab6 >> ("i386: run accel_cpu_instance_init

[PATCH 2/3] target/arm: Split out AT insns to tcg/cpregs-at.c

Split out all "system instructions for address translation". While mapped into "cpregs", these are instructions, and thus are handled in hardware by virtualization. They are all priviledged, and thus not reachable for user-only. Signed-off-by: Richard Henderson --- target/arm/internals.h |

[PATCH 0/3] target/arm: Split out AT and PMU cpregs

Rather than the wholesale movement of cpregs out of helper.c, split out two subsets: address translation and performance monitoring. r~ Richard Henderson (3): target/arm: Drop stub for define_tlb_insn_regs target/arm: Split out AT insns to tcg/cpregs-at.c target/arm: Split out performance

[PATCH 1/3] target/arm: Drop stub for define_tlb_insn_regs

Allow the call to be compiled out by protecting it with tcg_enabled. Signed-off-by: Richard Henderson --- target/arm/helper.c| 4 +++- target/arm/tcg-stubs.c | 5 - 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c311d2df21..

[PATCH 3/3] target/arm: Split out performance monitor regs to cpregs-pmu.c

Signed-off-by: Richard Henderson --- target/arm/cpregs.h |3 + target/arm/internals.h |2 + target/arm/cpregs-pmu.c | 1309 +++ target/arm/helper.c | 1287 +- target/arm/meson.build |2 + 5 files changed

[PATCH] docs/devel/tracing: Update trace.h creation rune to include SPDX

checkpatch now checks that new files have an SPDX line. If you use the shell rune in tracing.rst to create a trace.h wrapper header, this triggers checkpatch to complain. Although these files are tiny, it's worth having the SPDX line to avoid having to add extra exception cases to checkpatch. Upd

Re: [PATCH V2 0/5] fast qom tree get

On 7/4/2025 8:26 AM, Markus Armbruster wrote: Steve Sistare writes: Using qom-list and qom-get to get all the nodes and property values in a QOM tree can take multiple seconds because it requires 1000's of individual QOM requests. Some managers fetch the entire tree or a large subset of it wh

Re: [PATCH v7 4/4] hw/arm/virt: Allow virt extensions with KVM

On Mon, 7 Jul 2025 at 15:32, Marc Zyngier wrote: > > On Mon, 07 Jul 2025 10:53:38 +0100, > Peter Maydell wrote: > > > > On Mon, 7 Jul 2025 at 10:30, Eric Auger wrote: > > > > > > Hi Peter, Marc, > > > > > > On 7/4/25 2:22 PM, Peter Maydell wrote: > > > > I suppose the system registers probably g

Re: [PATCH V2 1/5] qom: qom-tree-get

On 7/4/2025 8:22 AM, Markus Armbruster wrote: Steve Sistare writes: Define the qom-tree-get QAPI command, which fetches an entire tree of properties and values with a single QAPI call. This is much faster than using qom-list plus qom-get for every node and property of the tree. See qom.json

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