Hi Bibo Mao:
On 2025/6/13 上午9:31, Xianglai Li wrote:
The expire time is sent to the timer only
when the expire Time is greater than 0 or
greater than now. Otherwise, the timer
will trigger interruption continuously.
Timer interrupts are sent using pulse functions.
Signed-off-by: Xianglai Li
On 2025/07/01 20:30, Liu Jaloo wrote:
in the source code "hw/net/e1000.c"
[LEDCTL] = 0x602,
maybe should be:
[LEDCTL] = 0x07068302,
according to the "*Table 13-60. LED Control Bit Description*" of the doc:
https://www.intel.com/content/dam/doc/manual/pci-pci-x-family-gbe-
controllers-softwar
On Thu, Jul 3, 2025 at 10:59 PM Daniil Tatianin
wrote:
>
> On 7/3/25 1:55 PM, Vladimir Sementsov-Ogievskiy wrote:
>
> > Theoretically tap_read_packet() may return size less than
> > s->host_vnet_hdr_len, and next, we'll work with negative size
> > (in case of !s->using_vnet_hdr). Let's avoid it.
>
I think others should weigh in on the higher level abstractions you're
adding for vhost_user_blk_force_stop() - I don't have a strong
perspective on them. I'm ok with this for vhost-user-blk.
Acked-by: Raphael Norwitz
On Mon, Jun 9, 2025 at 5:26 PM Daniil Tatianin
wrote:
>
> If we have a server
Hi Eric,
>-Original Message-
>From: Duan, Zhenzhong
>Subject: RE: [PATCH v2 09/19] intel_iommu: Introduce two helpers
>vtd_as_from/to_iommu_pasid_locked
>
>
>
>>-Original Message-
>>From: Eric Auger
>>Subject: Re: [PATCH v2 09/19] intel_iommu: Introduce two helpers
>>vtd_as_from/t
On Thu, Jun 26, 2025 at 04:31:00PM +0800, Zhao Liu wrote:
> Add the cache model to SapphireRapids (v4) to better emulate its
> environment.
>
> The cache model is based on SapphireRapids-SP (Scalable Performance):
>
> --- cache 0 ---
> cache type = data cache (
On Thu, Jun 26, 2025 at 04:30:59PM +0800, Zhao Liu wrote:
> Add the cache model to GraniteRapids (v3) to better emulate its
> environment.
>
> The cache model is based on GraniteRapids-SP (Scalable Performance):
>
> --- cache 0 ---
> cache type = data cache (1)
On Thu, Jun 26, 2025 at 04:30:58PM +0800, Zhao Liu wrote:
> Add the cache model to SierraForest (v3) to better emulate its
> environment.
>
> The cache model is based on SierraForest-SP (Scalable Performance):
>
> --- cache 0 ---
> cache type = data cache (1)
>
On Fri, Jun 27, 2025 at 11:51:25AM +0800, Zhao Liu wrote:
> Hi,
>
> Since the previsor unified cache model series has already introduced a
> new compat property "x-vendor-cpuid-only-v2", it's a chance to once
> again consolidate more vendor-specific CPUIDs.
>
> I also checked the CPUID leaves cur
On 6/27/25 02:26, Alex Williamson wrote:
> On Tue, 17 Jun 2025 08:56:41 +0800
> Tomita Moeko wrote:
>
>> On 2025/5/29 18:41, Tomita Moeko wrote:
>>> On 2025/5/29 2:30, Alex Williamson wrote:
On Wed, 28 May 2025 23:55:48 +0800
Tomita Moeko wrote:
> Introduce x-pci-class-cod
On 7/6/2025 6:06 PM, Zhao Liu wrote:
On Fri, Jul 04, 2025 at 10:45:04PM +0800, Xiaoyao Li wrote:
Date: Fri, 4 Jul 2025 22:45:04 +0800
From: Xiaoyao Li
Subject: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10
X-Mailer: git-send-email 2.43.0
Intel AVX10 spec has been updated to make the bit 16-
pmp_is_in_range() prefers to match addresses within the interval
[start, end]. To archieve this, pmpaddrX is decremented during the end
address update.
In TOR mode, a rule is ignored if its start address is greater than or
equal to its end address.
However, if pmpaddrX is set to 0, this decrement
On Fri, Jul 04, 2025 at 10:45:04PM +0800, Xiaoyao Li wrote:
> Date: Fri, 4 Jul 2025 22:45:04 +0800
> From: Xiaoyao Li
> Subject: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10
> X-Mailer: git-send-email 2.43.0
>
> Intel AVX10 spec has been updated to make the bit 16-18 of
Th
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