Re: [WIP-for-10.1 v2 5/5] target/arm: Advertise FEAT_MEC in cpu max

On 7/4/25 09:14, Gustavo Romero wrote: Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a first step to fully support FEAT_MEC. The FEAT_MEC is an extension to FEAT_RME that implements multiple Memory Encryption Contexts (MEC) so the memory in a realm can be encrypted and acc

[PATCH v4 10/11] MAX78000: AES implementation

This commit implements AES for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig| 3 + hw/misc/max78000_aes.c | 223 + hw/misc/max78000_gcr.c |

[PATCH v4 07/11] MAX78000: Add GCR to SOC

This commit adds the Global Control Register to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/max78000_soc.c | 18 -- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/arm/max78

[PATCH v4 00/11] MAX78000FTHR Implementation

v4: Spacing and style standard changes in GCR SOC, TRNG SOC, and AES SOC v3: Addresses a few more comments by Peter. Really appreciate the review, thank you. ICC SOC: Gave each device a unique name UART SOC: Removed references to DeviceState and gave each device a unique name GCR SOC: Set obj

[PATCH v4 08/11] MAX78000: TRNG Implementation

This commit implements the True Random Number Generator for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/max78000_gcr.c | 6 ++ hw/misc/max78000_trng.c |

[PATCH v4 11/11] MAX78000: Add AES to SOC

This commit adds AES to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/max78000_soc.c | 12 +--- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_so

[PATCH v4 02/11] MAX78000: ICC Implementation

This commit implements the Instruction Cache Controller for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig| 3 + hw/misc/max78000_icc.c | 120 + hw/mis

[PATCH v4 01/11] MAX78000: Add MAX78000FTHR Machine

This patch adds support for the MAX78000FTHR machine. The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch implements only the MAX78000, which is Cortex-M4 based. Details can be found at: https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf Sig

[PATCH v4 04/11] MAX78000: UART Implementation

This commit implements UART support for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/char/Kconfig | 3 + hw/char/max78000_uart.c | 285 hw/char/meson.build

[PATCH v4 06/11] MAX78000: GCR Implementation

This commit implements the Global Control Register for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig| 3 + hw/misc/max78000_gcr.c | 339 + hw/misc/mes

[PATCH v4 03/11] MAX78000: Add ICC to SOC

This commit adds the instruction cache controller to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/max78000_soc.c | 20 include/hw/arm/max78000_soc.h | 6 ++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/h

[PATCH v4 05/11] MAX78000: Add UART to SOC

This commit adds UART to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/max78000_soc.c | 28 include/hw/arm/max78000_soc.h | 3 +++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/hw/arm/max78000_soc.c b/

[PATCH v4 09/11] MAX78000: Add TRNG to SOC

This commit adds TRNG to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 10 +- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 45c6088312..3f2069fb0

Re: [WIP-for-10.1 v2 4/5] target/arm: Add FEAT_TCR2

On 7/4/25 09:14, Gustavo Romero wrote: +static CPAccessResult tcr2_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ +return CP_ACCESS_OK; +}; Eh? This is missing everything: TRVM, HCRX_EL2.TCR2En, SCR_EL3.TCR2En. Two different functions re

Re: [WIP-for-10.1 v2 3/5] target/arm: Add FEAT_SCTLR2

On 7/4/25 09:14, Gustavo Romero wrote: diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4452e7c21e..a42d1133c2 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -296,6 +296,11 @@ static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id

شهادة الأبوة في المغرب

*كل ما تحتاج معرفته حول شهادة الأبوة بالمغرب * * يمكنك تحميل الطلب من خلال الرابط المباشر * *معلومات شاملة لاستخراج شهادة الأبوة والإجراءات القانونية المرتبطة بها* ما هي شهادة الأبوة

Re: [WIP-for-10.1 v2 2/5] target/arm: Add FEAT_MEC registers

On 7/4/25 09:14, Gustavo Romero wrote: +/* MEC registers */ +uint64_t mecidr_el2; Don't need this one. +uint64_t mecid_p0_el2; +uint64_t mecid_a0_el2; +uint64_t mecid_p1_el2; +uint64_t mecid_a1_el2; +uint64_t mecid_rl_a_el3; +uin

Re: [WIP-for-10.1 v2 1/5] target/arm: Add the MECEn SCR_EL3 bit

On 7/4/25 09:14, Gustavo Romero wrote: The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from EL2, so add it to the SCR mask list to use it later on. Signed-off-by: Gustavo Romero --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/tar

Re: [PULL 00/31] Accelerators patches for 2025-07-04

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/11] aspeed queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/40] riscv-to-apply queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/27] vfio queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH 0/5] arm: followup on the ID register storage series

On 7/4/25 08:19, Cornelia Huck wrote: Cornelia Huck (5): arm/cpu: store id_afr0 into the idregs array arm/cpu: store id_aa64afr{0,1} into the idregs array arm/cpu: fix trailing ',' for SET_IDREG arm/cpu: store clidr into the idregs array arm/kvm: shorten one overly long line Revi

Re: [PATCH] target/arm: Don't enforce NSE,NS check for EL3->EL3 returns

On 7/4/25 10:56, Peter Maydell wrote: In the Arm ARM, rule R_TYTWB that defines illegal exception return cases includes the case: If FEAT_RME is implemented, then if SCR_EL3.{NSE, NS} is {1, 0}, an exception return from EL3 to a lower Exception level Our implementation of this check fails to

Re: [PATCH v3 10/11] MAX78000: AES implementation

On Fri, 4 Jul 2025 at 17:57, Jackson Donaldson wrote: > > This commit implements AES for the MAX78000 > > Signed-off-by: Jackson Donaldson > --- Your signed-off-by line seems to have lost the email address part here. Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v3 08/11] MAX78000: TRNG Implementation

On Fri, 4 Jul 2025 at 17:57, Jackson Donaldson wrote: > > This commit implements the True Random Number > Generator for the MAX78000 > > Signed-off-by: Jackson Donaldson > --- > + > +static uint64_t max78000_trng_read(void *opaque, hwaddr addr, > +unsigned int

Re: [PATCH v3 11/11] MAX78000: Add AES to SOC

On Fri, 4 Jul 2025 at 17:57, Jackson Donaldson wrote: > > This commit adds AES to max78000_soc > > Signed-off-by: Jackson Donaldson > --- > hw/arm/max78000_soc.c | 14 +++--- > include/hw/arm/max78000_soc.h | 2 ++ > 2 files changed, 13 insertions(+), 3 deletions(-) > > diff --g

Re: [PATCH v3 09/11] MAX78000: Add TRNG to SOC

On Fri, 4 Jul 2025 at 17:57, Jackson Donaldson wrote: > > This commit adds TRNG to max78000_soc > > Signed-off-by: Jackson Donaldson > --- > hw/arm/max78000_soc.c | 12 +++- > include/hw/arm/max78000_soc.h | 2 ++ > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git

Re: [PATCH v3 07/11] MAX78000: Add GCR to SOC

On Fri, 4 Jul 2025 at 17:57, Jackson Donaldson wrote: > > This commit adds the Global Control Register to > max78000_soc > > Signed-off-by: Jackson Donaldson > @@ -94,12 +101,14 @@ static void max78000_soc_realize(DeviceState *dev_soc, > Error **errp) > return; > } > > + > fo

Re: [PATCH v3 05/11] MAX78000: Add UART to SOC

On Fri, 4 Jul 2025 at 17:57, Jackson Donaldson wrote: > > This commit adds UART to max78000_soc > > Signed-off-by: Jackson Donaldson > --- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH v3 03/11] MAX78000: Add ICC to SOC

On Fri, 4 Jul 2025 at 17:57, Jackson Donaldson wrote: > > This commit adds the instruction cache controller > to max78000_soc > > Signed-off-by: Jackson Donaldson > --- > hw/arm/max78000_soc.c | 20 > include/hw/arm/max78000_soc.h | 6 ++ > 2 files changed, 22 i

[PATCH v3 02/11] MAX78000: ICC Implementation

This commit implements the Instruction Cache Controller for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig| 3 + hw/misc/max78000_icc.c | 120 + hw/mis

[PATCH v3 06/11] MAX78000: GCR Implementation

This commit implements the Global Control Register for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig| 3 + hw/misc/max78000_gcr.c | 339 + hw/misc/mes

[PATCH v3 10/11] MAX78000: AES implementation

This commit implements AES for the MAX78000 Signed-off-by: Jackson Donaldson --- hw/arm/Kconfig | 1 + hw/misc/Kconfig| 3 + hw/misc/max78000_aes.c | 223 + hw/misc/max78000_gcr.c | 6 + hw/misc/meson.build

[PATCH v3 07/11] MAX78000: Add GCR to SOC

This commit adds the Global Control Register to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 22 -- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78

[PATCH v3 11/11] MAX78000: Add AES to SOC

This commit adds AES to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 14 +++--- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 074fb1da8b..39ae

[PATCH v3 05/11] MAX78000: Add UART to SOC

This commit adds UART to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 28 include/hw/arm/max78000_soc.h | 3 +++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index

[PATCH v3 09/11] MAX78000: Add TRNG to SOC

This commit adds TRNG to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 12 +++- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index eddd9616f0..074fb1d

[PATCH v3 01/11] MAX78000: Add MAX78000FTHR Machine

This patch adds support for the MAX78000FTHR machine. The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch implements only the MAX78000, which is Cortex-M4 based. Details can be found at: https://www.analog.com/media/en/technical-documentation/user-guides/max78000-user-guide.pdf Sig

[PATCH v3 00/11] MAX78000FTHR Implementation

v3: Addresses a few more comments by Peter. Really appreciate the review, thank you. ICC SOC: Gave each device a unique name UART SOC: Removed references to DeviceState and gave each device a unique name GCR SOC: Set object property links statically, instead of by reference to device id TRNG:

[PATCH v3 08/11] MAX78000: TRNG Implementation

This commit implements the True Random Number Generator for the MAX78000 Signed-off-by: Jackson Donaldson --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/max78000_gcr.c | 6 ++ hw/misc/max78000_trng.c | 139

[PATCH v3 03/11] MAX78000: Add ICC to SOC

This commit adds the instruction cache controller to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 20 include/hw/arm/max78000_soc.h | 6 ++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/ar

[PATCH v3 04/11] MAX78000: UART Implementation

This commit implements UART support for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/char/Kconfig | 3 + hw/char/max78000_uart.c | 285 hw/char/meson.build

[PATCH] target/arm: Don't enforce NSE,NS check for EL3->EL3 returns

In the Arm ARM, rule R_TYTWB that defines illegal exception return cases includes the case: If FEAT_RME is implemented, then if SCR_EL3.{NSE, NS} is {1, 0}, an exception return from EL3 to a lower Exception level Our implementation of this check fails to check that the return is to a lower excep

[PULL 070/119] target/arm: Use do_[us]sat_[bhs] in sve_helper.c

From: Richard Henderson Replace and remove do_sat_bhs. This avoids multiple repetitions of INT*_MIN/MAX. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-59-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c

[PULL 073/119] target/arm: Implement SME2 SUNPK, UUNPK

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20250704142112.1018902-62-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 13 target/arm/tcg/sme.decode | 18 targe

[PULL 100/119] target/arm: Implement DUPQ for SME2p1/SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-89-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 6 ++ target/arm/tcg/translate-sve.c | 21 + 2 file

[PULL 010/119] target/arm: Fix VLD2 helper load alignment checks

From: William Kosasih This patch adds alignment checks in the load operations in the VLD2 instruction. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154 Signed-off-by: William Kosasih Reviewed-by: Richard Henderson Message-id: 20250703085604.154449-10-kosasihwilli...@gmail.com Signe

[PULL 078/119] target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-67-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 15 +++ target/arm/tcg/sme.decode | 17 target/arm/tcg/sme

[PULL 107/119] target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-96-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 22 + target/arm/tcg/sve_ldst_internal.h | 26 ++ target/arm/t

[PULL 119/119] linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-108-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- linux-user/elfload.c | 8 1 file changed, 8 insertions(+) diff --git a/linux-user/elfload.c b/linu

[PULL 061/119] target/arm: Implement SME2 BFMLA, BFMLS

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-50-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper.h| 9 + target/arm/tcg/sme.decode | 18 ++ target

[PULL 091/119] target/arm: Implement SVE2p1 WHILE (predicate as counter)

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-80-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 3 ++ target/arm/tcg/sve.decode | 11 +++ target/arm/tcg/sve_helpe

[PULL 019/119] target/arm: Fix PSEL size operands to tcg_gen_gvec_ands

From: Richard Henderson Gvec only operates on size 8 and multiples of 16. Predicates may be any multiple of 2. Round up the size using the appropriate function. Cc: qemu-sta...@nongnu.org Fixes: 598ab0b24c0 ("target/arm: Implement PSEL") Reviewed-by: Peter Maydell Signed-off-by: Richard Henders

[PULL 007/119] target/arm: Fix VLDR_SG helper load alignment checks

From: William Kosasih This patch adds alignment checks in the load operations in the VLDR_SG instructions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154 Signed-off-by: William Kosasih Reviewed-by: Richard Henderson Message-id: 20250703085604.154449-7-kosasihwilli...@gmail.com Si

[PULL 009/119] target/arm: Fix VLD4 helper load alignment checks

From: William Kosasih This patch adds alignment checks in the load operations in the VLD4 instruction. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154 Signed-off-by: William Kosasih Reviewed-by: Richard Henderson Message-id: 20250703085604.154449-9-kosasihwilli...@gmail.com Signed

[PULL 113/119] target/arm: Rename FMOPA_h to FMOPA_w_h

The pattern we currently have as FMOPA_h is the "widening" insn that takes fp16 inputs and produces single-precision outputs. This is unlike FMOPA_s and FMOPA_d, which are non-widening produce outputs the same size as their inputs. SME2 introduces a non-widening fp16 FMOPA operation; rename FMOPA_

[PULL 094/119] target/arm: Implement SVE2p1 PEXT

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-83-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 2 + target/arm/tcg/vec_internal.h | 74 ++

[PULL 077/119] target/arm: Implement SME2 ZIP, UZP (two registers)

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-66-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 12 +++ target/arm/tcg/sme.decode | 12 +++ target/arm/tcg/sme_

[PULL 022/119] target/arm: Remove CPUARMState.vfp.scratch

From: Richard Henderson The last use of this field was removed in b2fc7be972b9. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-11-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 ---

[PULL 080/119] target/arm: Implement FCLAMP for SME2, SVE2p1

From: Richard Henderson This is the single vector version within SVE decode space. Tested-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-69-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode

Re: [PATCH v2 16/24] migration: Add capabilities into MigrationParameters

On Mon, Jun 30, 2025 at 04:59:05PM -0300, Fabiano Rosas wrote: > Add capabilities to MigrationParameters. This structure will hold all > migration options. Capabilities will go away in the next patch. > > Also add capabilities to MigrationParameter as the enum needs to be > kept in sync with Migra

[PULL 013/119] target/arm: Fix SME vs AdvSIMD exception priority

From: Richard Henderson We failed to raise an exception when sme_excp_el == 0 and fp_excp_el == 1. Cc: qemu-sta...@nongnu.org Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-2-richard.he

[PULL 104/119] target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-93-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 10 ++ target/arm/tcg/sve.decode | 3 +++ target/arm/tcg/sve_h

[PULL 112/119] target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-101-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper.h| 24 ++ target/arm/tcg/sme.decode | 42 target

[PULL 051/119] target/arm: Implement SME2 FVDOT, BFVDOT

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-40-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 2 ++ target/arm/tcg/helper.h| 2 ++ target/arm/tcg/sme.decode

[PULL 106/119] target/arm: Split the ST_zpri and ST_zprr patterns

From: Richard Henderson The msz > esz encodings are reserved, and some of them are about to be reused. Split these patterns so that the new insns do not overlap. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-95-richard.hender...@linaro.org Sign

[PULL 084/119] target/arm: Expand do_zero inline

From: Richard Henderson Expand to memset plus the return value, when used. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20250704142112.1018902-73-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 28 +++-

[PULL 074/119] target/arm: Implement SME2 ZIP, UZP (four registers)

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-63-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 12 ++ target/arm/tcg/sme.decode | 11 ++ target/arm/tcg/sme_he

[PULL 069/119] target/arm: Introduce do_[us]sat_[bhs] macros

From: Richard Henderson Inputs are a wider type of indeterminate sign. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-58-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/vec_internal.h | 7 +++ 1 file changed, 7

[PULL 101/119] target/arm: Implement EXTQ for SME2p1/SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-90-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 2 ++ target/arm/tcg/translate-sve.c | 49 +

[PULL 108/119] target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h

From: Richard Henderson Move from sme_helper.c to the shared header. Add a comment noting the lack of atomicity. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-97-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_

[PULL 093/119] target/arm: Implement {ADD, SMIN, SMAX, UMIN, UMAX}QV for SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-82-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 25 ++ target/arm/tcg/sve.decode | 7 ++ target/ar

[PULL 060/119] target/arm: Implement SME2 FMLA, FMLS

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-49-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 48 + target/arm/tcg/translate-sme.c | 95 ++

[PULL 012/119] target/arm: Fix VST2 helper store alignment checks

From: William Kosasih This patch adds alignment checks in the store operations in the VST2 instruction. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154 Signed-off-by: William Kosasih Reviewed-by: Richard Henderson Message-id: 20250703085604.154449-12-kosasihwilli...@gmail.com Sign

[PULL 086/119] target/arm: Split out do_whileg from helper_sve_whileg

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20250704142112.1018902-75-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 39 +++-- 1 file changed, 20 insertions(+), 19

[PULL 102/119] target/arm: Implement PMOV for SME2p1/SVE2p1

From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-91-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 8 +++ target/arm/tcg/vec_internal.h | 34 target/arm/tcg/sve

[PULL 085/119] target/arm: Split out do_whilel from helper_sve_whilel

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-74-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-

[PULL 099/119] target/arm: Implement CNTP (predicate as counter) for SME2/SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-88-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 1 + target/arm/tcg/sve.decode | 3 ++- target/arm/tcg/sve_helper.c

[PULL 062/119] target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-51-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper.h| 2 ++ target/arm/tcg/sme.decode | 25 +++ target/arm/t

[PULL 046/119] target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s

From: Richard Henderson Indicate whether to use FPST_FPCR or FPST_ZA via bit 2 of simd_data(desc). For SVE, this bit remains zero. For do_FMLAL_zzzw, this requires no change. For do_FMLAL_zzxw, move the index up one bit. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id:

[PULL 115/119] target/arm: Support FPCR.AH in SME FMOPS, BFMOPS

From: Richard Henderson For non-widening, we can use float_muladd_negate_product, For widening, which uses dot-product, we need to handle the negation explicitly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-104-richard.hender...@linaro.org Sig

[PULL 002/119] target/arm: Bring VLSTM/VLLDM helper store/load closer to the ARM pseudocode

From: William Kosasih This patch brings the VLSTM and VLLDM helper functions closer to the ARM pseudocode by adding MO_ALIGN to the MemOpIdx of the associated store (`cpu_stl_mmu`) operations and load (`cpu_ldl_mmu`) operations. Note that this is not a bug fix: an 8-byte alignment check already

[PULL 081/119] target/arm: Implement SME2p1 Multiple Zero

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-70-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 23 +++ target/arm/tcg/translate-sme.c | 20

[PULL 097/119] target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-86-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 49 target/arm/tcg/sve.decode | 8 targe

[PULL 072/119] target/arm: Implement SQCVTN, UQCVTN, SQCVTUN for SME2/SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-61-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 20 target/arm/tcg/translate-sve.c | 7 +++ 2 file

[PULL 053/119] target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20250704142112.1018902-42-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper.h| 8 target/arm/tcg/sme.decode | 63 - targ

[PULL 117/119] target/arm: Implement SME2 BFMOPA (non-widening)

Reviewed-by: Alex Bennée Signed-off-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-106-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 6 target/arm/tcg/sme.decode | 2 ++ target/arm/tcg/sme_helpe

[PULL 042/119] target/arm: Implement SME2 Multiple and Single SVE Destructive

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-31-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 13 target/arm/tcg/helper.h| 8 ++ target/arm/tcg/vec_intern

[PULL 109/119] target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-98-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 32 + target/arm/tcg/sve.decode | 31 + target/arm/tc

[PULL 015/119] target/arm: Fix 128-bit element ZIP, UZP, TRN

From: Richard Henderson We missed the instructions UDEF when the vector size is too small. We missed marking the instructions non-streaming with SME. Cc: qemu-sta...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-4-richard.hender...@li

[PULL 067/119] target/arm: Implement SME2 SCVTF, UCVTF

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-56-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 2 ++ target/arm/tcg/sme.decode | 5 + target/arm/tcg/sme_helper.

[PULL 110/119] target/arm: Implement LD1Q, ST1Q for SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-99-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sve.h| 16 target/arm/tcg/sve.decode | 8 target/ar

[PULL 005/119] target/arm: Fix VLDR helper load alignment checks

From: William Kosasih This patch adds alignment checks in the load operations in the VLDR instruction. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1154 Signed-off-by: William Kosasih Reviewed-by: Richard Henderson Message-id: 20250703085604.154449-5-kosasihwilli...@gmail.com Signed

[PULL 098/119] target/arm: Implement BFMLSLB{L, T} for SME2/SVE2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-87-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve.decode | 6 ++ target/arm/tcg/translate-sve.c | 30 +

[PULL 050/119] target/arm: Implement SME2 BFDOT

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-39-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme.decode | 9 + target/arm/tcg/translate-sme.c | 17 + 2 files

[PULL 116/119] target/arm: Implement FMOPA (non-widening) for fp16

Reviewed-by: Alex Bennée Signed-off-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-105-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 6 target/arm/tcg/sme.decode | 2 ++ target/arm/tcg/sme_helpe

[PULL 118/119] target/arm: Enable FEAT_SME2p1 on -cpu max

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-107-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 6 ++ target/arm/tcg/cpu64.c| 10 -- 2 files changed, 1

[PULL 057/119] target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-46-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 11 + target/arm/tcg/sme.decode | 11 + target/arm/tcg/

[PULL 111/119] target/arm: Implement MOVAZ for SME2p1

From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-100-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-sme.h| 6 target/arm/tcg/sme.decode | 36 target/a

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