> On 3 Jul 2025, at 7:22 PM, Roy Hopkins wrote:
>
> On Fri, 2025-06-27 at 16:58 +0530, Ani Sinha wrote:
>> On Fri, Jun 13, 2025 at 8:52 PM Roy Hopkins
>> wrote:
>>>
>>> The initialization sections in IGVM files contain configuration that
>>> should be applied to the guest platform before it
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
In order to dispatch over AccelOpsClass::handle_interrupt(),
we need it always defined,
It seems I can only understand it until I see the code to really require
it to be mandatory.
But anyway, the change itself is correct.
Reviewed-by: Xia
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Update CPUState::interrupt_request once in cpu_interrupt().
Pass the old and new masks along.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-accel-ops-icount.h | 2 +-
accel/tcg/tcg-accel-ops.h
On 02.07.2025 09:03, Thomas Huth wrote:
From: Thomas Huth
Since commit 126e7f78036 ("kvm: require KVM_CAP_IOEVENTFD and
KVM_CAP_IOEVENTFD_ANY_LENGTH") we require at least kernel 4.4 to
be able to use KVM. Adjust the upgrade_note accordingly.
While we're at it, remove the text about kvm-kmod and
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
'dummy' helpers are specific to accelerator implementations,
no need to expose them via "system/cpus.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_cpu_synchronize_state() stub is not
necessary.
Fixes: e0715f6abce ("kvm: remove kvm specific functions from global includes")
Signed-off-by: Philippe Mathieu-D
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
---
include/hw/core/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Common code only needs to know whether HVF is enabled and
the QOM type. Move the rest to "hvf_int.h", removing the
need for COMPILING_PER_TARGET #ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xia
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
AccelOpsClass is for methods dealing with vCPUs.
When only dealing with AccelState, AccelClass is sufficient.
Move cpus_are_resettable() declaration to accel/accel-system.c.
I don't think this is necessary unless a solid justfication provided.
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
AccelOpsClass is for methods dealing with vCPUs.
When only dealing with AccelState, AccelClass is sufficient.
In order to have AccelClass methods instrospect their state,
we need to pass AccelState by argument.
Restrict kvm_supports_guest_debug
Peter Xu writes:
> On Tue, Jul 01, 2025 at 08:12:27AM +0200, Markus Armbruster wrote:
>> Fabiano Rosas writes:
>>
>> > Caught by inspection, but ASAN also reports:
>> >
>> > Direct leak of 16 byte(s) in 1 object(s) allocated from:
>> > #0 in malloc
>> > #1 in g_malloc
>> > #2 in g_memdup
>>
On Wed, Jul 2, 2025 at 5:31 PM Alexandre Ghiti wrote:
>
> The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
> for software to use.
>
> Reviewed-by: Deepak Gupta
> Signed-off-by: Alexandre Ghiti
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Changes in v2:
>
Philippe Mathieu-Daudé writes:
> Display the CPU model in 'info cpus'. Example before:
>
> $ qemu-system-aarch64 -M xlnx-versal-virt -S -monitor stdio
> QEMU 10.0.0 monitor - type 'help' for more information
> (qemu) info cpus
> * CPU #0: thread_id=42924
>CPU #1: thread_id=42924
>CPU
Philippe Mathieu-Daudé writes:
> Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER",
> released with QEMU v8.1.0) we get pointless output:
>
> (qemu) info opcount
> [TCG profiler not compiled]
>
> Remove that unstable and unuseful command.
>
> Signed-off-by: Philippe Mathieu-Daudé
On Thu, Jul 03, 2025 at 11:41:05AM +0100, Jonathan Cameron wrote:
> v17: Thanks to Eric for review
> - Add a comment to the high memory map to reduce the chance of nasty
> surprises in the future as similar to device_memory, the CXL
> Fixed Memory Windows are of variable size as so can't be rep
On 7/4/2025 12:27 PM, Xiaoyao Li wrote:
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
---
accel/tcg/monitor.c | 27 +--
1 file changed, 17 insertions(+), 10 deletio
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
---
accel/tcg/monitor.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/accel/tcg/monitor.c b
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Fabiano Rosas writes:
>>
>>> Now that the TLS options have been made the same between
>>> migrate-set-parameters and query-migrate-parameters, a single type can
>>> be used. Remove MigrateSetParameters.
>>>
>>> The TLS options documentation
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER",
released with QEMU v8.1.0) we get pointless output:
(qemu) info opcount
[TCG profiler not compiled]
Remove that unstable and unuseful command.
Signed-off-by: Philippe Mathieu
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
TCG profiler was removed in commit 1b65b4f54c7.
Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
kvm_create_vcpu() is only used within the same file unit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
---
include/system/kvm.h | 8
accel/kvm/kvm-all.c | 8 +++-
2 files c
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_init_cpu_signals() stub is not necessary.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
BTW, it seems we c
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-accel-ops.c | 2 --
system/cpus.c | 2 ++
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tc
On Tue, Jun 24, 2025 at 12:54 AM Daniel Henrique Barboza
wrote:
>
> Commit b84694defb added the CPU_DUMP_VPU to allow vector registers to be
> logged by log_cpu_exec() in TCG. This flag was then used in commit
> b227f6a8a7 to print RISC-V vector registers using this flag. Note that
> this change w
On Thu, Jun 19, 2025 at 7:36 AM Vasilis Liaskovitis
wrote:
>
> Usage of vsetvli instruction is reserved if VLMAX is changed when vsetvli rs1
> and rd arguments are x0.
>
> In this case, if the new property is true, only the vill bit will be set.
>
> See
> https://github.com/riscv/riscv-isa-manual
On 6/26/2025 4:31 PM, Zhao Liu wrote:
> Host SapphireRapids CPU has 0x1f leaf by default, so that enable it for
> Guest CPU by default as well.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Zhao Liu
> ---
> Changes since RFC:
> * Rename the property to "x-force-cpuid-0x1f". (Igor)
> ---
>
On 6/26/2025 4:31 PM, Zhao Liu wrote:
> Host GraniteRapids CPU has 0x1f leaf by default, so that enable it for
> Guest CPU by default as well.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Zhao Liu
> ---
> Changes since RFC:
> * Rename the property to "x-force-cpuid-0x1f". (Igor)
> ---
> t
On 6/26/2025 4:31 PM, Zhao Liu wrote:
> Host SierraForest CPU has 0x1f leaf by default, so that enable it for
> Guest CPU by default as well.
>
> Suggested-by: Igor Mammedov
> Signed-off-by: Zhao Liu
> ---
> Changes since RFC:
> * Rename the property to "x-force-cpuid-0x1f". (Igor)
> ---
> ta
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
include/system/runstate.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/system/runstate.h b/include/system/runstate.
On 6/26/2025 4:31 PM, Zhao Liu wrote:
> From: Manish Mishra
>
> Add a "x-force-cpuid-0x1f" property so that CPU models can enable it and
> have 0x1f CPUID leaf natually as the Host CPU.
>
> The advantage is that when the CPU model's cache model is already
> consistent with the Host CPU, for exam
On 6/26/2025 4:31 PM, Zhao Liu wrote:
> Add the cache model to SapphireRapids (v4) to better emulate its
> environment.
>
> The cache model is based on SapphireRapids-SP (Scalable Performance):
>
> --- cache 0 ---
> cache type = data cache (1)
> cache lev
On 6/26/2025 4:30 PM, Zhao Liu wrote:
> Add the cache model to GraniteRapids (v3) to better emulate its
> environment.
>
> The cache model is based on GraniteRapids-SP (Scalable Performance):
>
> --- cache 0 ---
> cache type = data cache (1)
> cache level
On 6/26/2025 4:30 PM, Zhao Liu wrote:
> Add the cache model to SierraForest (v3) to better emulate its
> environment.
>
> The cache model is based on SierraForest-SP (Scalable Performance):
>
> --- cache 0 ---
> cache type = data cache (1)
> cache level
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Commit 8c56c1a592b ("memory: emulate ioeventfd") added a !KVM
check because the only accelerator available back then were TCG,
QTest and KVM. Then commit 126e7f78036 ("kvm: require
KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH") suggested
'!
On Thu, Jun 19, 2025 at 11:56 PM Roan Richmond
wrote:
>
> This is based on version v0.8.3 of the ZALASR specification [1].
> The specification is listed as in Frozen state [2].
>
> [1]: https://github.com/riscv/riscv-zalasr/tree/v0.8.3
> [2]:
> https://lf-riscv.atlassian.net/wiki/spaces/HOME/page
On 7/3/25 11:32, Philippe Mathieu-Daudé wrote:
I'd like to be informed of overall changes of accelerators.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e3e08d4607f..a8bf3f9ccfa 100644
--- a/MAINTAINE
On 7/3/25 11:17, Alex Bennée wrote:
Richard Henderson writes:
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpu64.c| 10 --
docs/system/arm/emulation.rst | 6 ++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Display the CPU model in 'info cpus'. Example before:
$ qemu-system-aarch64 -M xlnx-versal-virt -S -monitor stdio
QEMU 10.0.0 monitor - type 'help' for more information
(qemu) info cpus
* CPU #0: thread_id=42924
CPU #1: thread_id=429
ramfb is a sysbus device so it can only used for machine types where it
is explicitly enabled:
# git grep machine_class_allow_dynamic_sysbus_dev.*TYPE_RAMFB_DEVICE
hw/arm/virt.c:machine_class_allow_dynamic_sysbus_dev(mc,
TYPE_RAMFB_DEVICE);
hw/i386/microvm.c:machine
Currently the ramfb device loads the vgabios-ramfb.bin unconditionally, but only
the x86 need the vgabios-ramfb.bin, this can cause that when use the
release package on arm64 it can't find the vgabios-ramfb.bin.
Because only seabios will use the vgabios-ramfb.bin, load the rom logic
is x86-specifi
Currently the ramfb device loads the vgabios-ramfb.bin unconditionally,
but only the x86 need the vgabios-ramfb.bin, this can cause that when
use the release package on arm64 it can't find the vgabios-ramfb.bin.
Because only seabios will use the vgabios-ramfb.bin, load the rom logic
is x86-specifi
On Thu, Jun 19, 2025 at 11:56 PM Roan Richmond
wrote:
>
> This is based on version v0.8.3 of the ZALASR specification [1].
> The specification is listed as in Frozen state [2].
>
> [1]: https://github.com/riscv/riscv-zalasr/tree/v0.8.3
> [2]:
> https://lf-riscv.atlassian.net/wiki/spaces/HOME/page
On Tue, Jun 17, 2025 at 4:29 PM ~liuxu wrote:
>
> Thanks for Alistair's correction on the V8 version.
>
> Now Zclsd has been disabled for the "max" CPU as C and F are already
> enabled.
>
> lxx (1):
> target/riscv: Add Zilsd and Zclsd extension support
Thanks!
Applied to riscv-to-apply.next
A
* Daniel Henrique Barboza (dbarb...@ventanamicro.com) wrote:
> The MonitorDef API is related to two HMP monitor commands: 'p' and 'x':
>
> (qemu) help p
> print|p /fmt expr -- print expression value (use $reg for CPU register access)
> (qemu) help x
> x /fmt addr -- virtual memory dump starting at
On Fri, Jul 4, 2025 at 4:24 AM Charalampos Mitrodimas
wrote:
>
> This patch series fixes incorrect behavior in MEPC/SEPC CSRs where the
> lower bits were not properly masked according to the RISC-V specification.
>
> The issue was discovered when vectored mode bits from STVEC were
> written to MEP
On Fri, Jul 4, 2025 at 4:25 AM Charalampos Mitrodimas
wrote:
>
> According to the RISC-V Privileged Architecture specification, the low
> bit of MEPC/SEPC must always be zero. When IALIGN=32, the two low bits
> must be zero.
>
> This commit fixes the behavior of MEPC/SEPC CSR reads and writes, and
On Mon, Jun 16, 2025 at 5:02 PM wrote:
>
> Address an error in migration when aia is configured as 'aplic-imsic' in
> riscv kvm vm by adding riscv_aplic_state_needed() and
> riscv_imsic_state_needed() to determine whether the corresponding sates are
> needed.
>
> Previously, the fields in the vmsd
On 7/3/25 07:24, Peter Maydell wrote:
On Wed, 2 Jul 2025 at 13:38, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sve.h| 8 +
target/arm/tcg/sve_helper.c| 317 +
target/arm/tcg/translate-sve.c | 93 ++
On 3/7/25 19:32, Philippe Mathieu-Daudé wrote:
I'd like to be informed of overall changes of accelerators.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e3e08d4607f..a8bf3f9ccfa 100644
--- a/MAINTAINE
On Tue, Jul 01, 2025 at 08:38:19AM +0200, Markus Armbruster wrote:
> Fabiano Rosas writes:
>
> > The MigrationState is a QOM object with TYPE_DEVICE as a parent. This
> > was done about eight years ago so the migration code could make use of
> > qdev properties to define the defaults for the migr
On Thu, Jul 03, 2025 at 11:41:10AM +0100, Jonathan Cameron wrote:
> Add a single complex case for aarch64 virt machine.
>
> Given existing much more comprehensive tests for x86 cover the common
> functionality, a single test should be enough to verify that the aarch64
> part continues to work.
>
On Thu, Jul 03, 2025 at 11:21:38PM +0200, Cédric Le Goater wrote:
> On 7/3/25 21:45, Peter Xu wrote:
> > On Wed, Jul 02, 2025 at 03:41:08PM -0400, Steven Sistare wrote:
> > > The irq producer is not closed, but it is detached from the kvm consumer.
> > > It's eventfd is preserved in new QEMU, and i
On Tue, Jul 01, 2025 at 08:12:27AM +0200, Markus Armbruster wrote:
> Fabiano Rosas writes:
>
> > Caught by inspection, but ASAN also reports:
> >
> > Direct leak of 16 byte(s) in 1 object(s) allocated from:
> > #0 in malloc
> > #1 in g_malloc
> > #2 in g_memdup
> > #3 in qapi_clone_start_stru
On 7/3/25 21:45, Peter Xu wrote:
On Wed, Jul 02, 2025 at 03:41:08PM -0400, Steven Sistare wrote:
The irq producer is not closed, but it is detached from the kvm consumer.
It's eventfd is preserved in new QEMU, and interrupts that arrive during
transition are pended there.
Ah I see, looks reaso
On 7/3/25 3:21 PM, Charalampos Mitrodimas wrote:
Add a regression test to verify that MEPC properly masks the lower
bits when an address with mode bits is written to it, as required by
the RISC-V Privileged Architecture specification.
The test sets STVEC to an address with bit 0 set (vectored
On 7/3/25 3:21 PM, Charalampos Mitrodimas wrote:
According to the RISC-V Privileged Architecture specification, the low
bit of MEPC/SEPC must always be zero. When IALIGN=32, the two low bits
must be zero.
This commit fixes the behavior of MEPC/SEPC CSR reads and writes, and
the implicit reads
On Tue, Jul 1, 2025 at 4:58 AM Thomas Huth wrote:
>
> From: Thomas Huth
>
> The original image has been removed from the server, so the test
> currently fails if it has to fetch the asset, but we can still
> download the ISO from the archive server. While we're at it, prefer
> the XZ compressed i
On Wed, Jul 02, 2025 at 03:41:08PM -0400, Steven Sistare wrote:
> The irq producer is not closed, but it is detached from the kvm consumer.
> It's eventfd is preserved in new QEMU, and interrupts that arrive during
> transition are pended there.
Ah I see, looks reasonable.
So can I understand the
* Pierrick Bouvier (pierrick.bouv...@linaro.org) wrote:
> Hi,
>
> I recently needed to slow down time within a virtual machine, due to a
> timeout being hit because my QEMU binary which was not fast enough (gcov
> debug build if you're curious about the use case).
>
> Currently, people tend to us
Markus Armbruster writes:
> Fabiano Rosas writes:
>
>> Now that the TLS options have been made the same between
>> migrate-set-parameters and query-migrate-parameters, a single type can
>> be used. Remove MigrateSetParameters.
>>
>> The TLS options documentation from MigrationParameters were rep
This patch series fixes incorrect behavior in MEPC/SEPC CSRs where the
lower bits were not properly masked according to the RISC-V specification.
The issue was discovered when vectored mode bits from STVEC were
written to MEPC and not properly cleared, causing incorrect behavior
on MRET.
Charalam
According to the RISC-V Privileged Architecture specification, the low
bit of MEPC/SEPC must always be zero. When IALIGN=32, the two low bits
must be zero.
This commit fixes the behavior of MEPC/SEPC CSR reads and writes, and
the implicit reads by MRET/SRET instructions to properly mask the
lowest
Add a regression test to verify that MEPC properly masks the lower
bits when an address with mode bits is written to it, as required by
the RISC-V Privileged Architecture specification.
The test sets STVEC to an address with bit 0 set (vectored mode),
triggers an illegal instruction exception, cop
hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL),
while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/hvf/hvf-accel-ops.c | 274 +-
accel/hvf/hvf-all.c
Currently nvmm_enabled() is restricted to target-specific code.
By defining CONFIG_NVMM_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/system/nvmm.h | 23 ---
accel/stubs/nvmm-stub.c | 12
'dummy' helpers are specific to accelerator implementations,
no need to expose them via "system/cpus.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
MAINTAINERS | 1 +
accel/dummy-cpus.h| 14 ++
include/system/cpus.h | 5 -
accel/dumm
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/accel.h | 2 +-
accel/kvm/kvm-all.c | 4 ++--
system/memory.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/qemu/accel.h b/include/qemu/accel.h
index b040fa104b6..44189b77
Allow dereferencing AccelOpsClass outside of accel/accel-system.c.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
include/qemu/accel.h | 3 +++
include/system/accel-ops.h | 3 ++-
accel/accel-common.c | 1 +
accel/accel-system.c
Only accelerator implementations (and the common accelator
code) need to know about AccelClass internals. Move the
definition out but forward declare AccelState and AccelClass.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 2 +-
include/accel/accel-ops.h | 50 +++
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Zhao Liu
---
include/hw/core/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 162a56a5daa..5eaf41a566f 100644
--- a/include/hw/core/cp
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/system/accel-ops.h | 8
include/system/hw_accel.h | 8
2 files changed, 16 insertions(+)
diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h
index 6eed1a3cfc8..2075691331c 100644
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/kvm/kvm-all.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 1b6b7006470..a6ea2c7f614 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER",
released with QEMU v8.1.0) we get pointless output:
(qemu) info opcount
[TCG profiler not compiled]
Remove that unstable and unuseful command.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Dr. David Alan Gilbert
Reviewed-by:
Update CPUState::interrupt_request once in cpu_interrupt().
Pass the old and new masks along.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-accel-ops-icount.h | 2 +-
accel/tcg/tcg-accel-ops.h| 2 +-
include/system/accel-ops.h | 2 +-
ac
AccelOpsClass is for methods dealing with vCPUs.
When only dealing with AccelState, AccelClass is sufficient.
In order to have AccelClass methods instrospect their state,
we need to pass AccelState by argument.
Restrict kvm_supports_guest_debug() scope.
Signed-off-by: Philippe Mathieu-Daudé
Rev
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/tcg-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 7ae7d552d9e..969c50c87ea 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/system/hvf_int.h | 1 -
accel/hvf/hvf-accel-ops.c | 10 +-
target/arm/hvf/hvf.c | 4 ++--
target/i386/hvf/hvf.c |
Since commit 57038a92bb0 ("cpus: extract out kvm-specific code
to accel/kvm") the kvm_cpu_synchronize_state() stub is not
necessary.
Fixes: e0715f6abce ("kvm: remove kvm specific functions from global includes")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/stub
In order to dispatch over AccelOpsClass::handle_interrupt(),
we need it always defined, not calling a hidden handler under
the hood. Make AccelOpsClass::handle_interrupt() mandatory.
Expose generic_handle_interrupt() prototype and register it
for each accelerator.
Suggested-by: Richard Henderson
This method only accesses xen_domid/xen_domid_restrict, which are both
related to the 'accelerator', not the machine. Besides, xen_domid aims
to be in Xen AccelState and xen_domid_restrict a xen_domid_restrict
QOM property.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
In order to avoid init_machine() to call current_accel(),
pass AccelState along.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
include/qemu/accel.h| 2 +-
accel/accel-system.c| 2 +-
accel/hvf/hvf-all.c | 2 +-
accel/k
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/system/accel-ops.h | 8
include/system/hw_accel.h | 13 +++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h
index f19245d0
In order to have AccelClass methods instrospect their state,
we need to pass AccelState by argument.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/qemu/accel.h | 2 +-
accel/accel-common.c | 2 +-
accel/hvf/hvf-all.c | 2 +-
accel/kvm/kvm-all.c | 2 +-
accel
AccelOpsClass is for methods dealing with vCPUs.
When only dealing with AccelState, AccelClass is sufficient.
Move cpus_are_resettable() declaration to accel/accel-system.c.
In order to have AccelClass methods instrospect their state,
we need to pass AccelState by argument.
Adapt KVM handler.
S
Currently whpx_enabled() is restricted to target-specific code.
By defining CONFIG_WHPX_IS_POSSIBLE we allow its use anywhere.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/system/whpx.h | 27 ++-
accel/stubs/whpx-stub.c | 12
Common code only needs to know whether HVF is enabled and
the QOM type. Move the rest to "hvf_int.h", removing the
need for COMPILING_PER_TARGET #ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/system/hvf.h | 38
I'd like to be informed of overall changes of accelerators.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e3e08d4607f..a8bf3f9ccfa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -495,6 +495,7 @@ Guest CPU
Unfortunately "system/accel-ops.h" handlers are not only
system-specific. For example, the cpu_reset_hold() hook
is part of the vCPU creation, after it is realized.
Mechanical rename to drop 'system' using:
$ sed -i -e s_system/accel-ops.h_accel/accel-cpu-ops.h_g \
$(git grep -l s
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/kvm/kvm-all.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 0cd9b2f29ab..f1c3d4d27c7 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-al
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/i386/whpx/whpx-all.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/i386/whpx/whp
Display the CPU model in 'info cpus'. Example before:
$ qemu-system-aarch64 -M xlnx-versal-virt -S -monitor stdio
QEMU 10.0.0 monitor - type 'help' for more information
(qemu) info cpus
* CPU #0: thread_id=42924
CPU #1: thread_id=42924
CPU #2: thread_id=42924
CPU #3: thread_id=42924
Commit 8c56c1a592b ("memory: emulate ioeventfd") added a !KVM
check because the only accelerator available back then were TCG,
QTest and KVM. Then commit 126e7f78036 ("kvm: require
KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH") suggested
'!KVM' check should be '(TCG || QTest)'. Later more acc
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/monitor.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c
index 344ec500473..6d9cc11d94c 100644
--- a/accel/tcg/monitor.c
No need for accel-specific @dirty field when we have
a generic one in CPUState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/i386/nvmm/nvmm-all.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/target/i386/nvmm/nvmm-
hvf-all.c aims to contain the generic accel methods (TYPE_ACCEL),
while hvf-accel-ops.c the per-vcpu methods (TYPE_ACCEL_OPS).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/hvf/hvf-accel-ops.c | 30 ++
accel/hvf/hvf-all.c | 28 -
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
include/system/runstate.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/system/runstate.h b/include/system/runstate.h
index fdd5c4a5172..b6e8d6beab7 100644
--- a/include/s
Statistic code is not specific to system emulation (except
cross-page checks) and can be used to analyze user-mode binaries.
Extract statistic related code to its own file: tcg-stats.c,
keeping the original LGPL-2.1-or-later license tag.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/monito
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